The default application memory (DAM) is an SRI peripheral device that provides access to volatile memory resources. Its main purpose is to provide 64 kBytes or 32 kBytes of local memory for general purposes. The amount of memory available depends on the product. The data stored in the local memory is protected by ECC. Areas of the local memory can be write-protected by configuring up to eight address ranges using SFRs in the DAM. Each of these areas can be dimensioned in 32-byte increments and has its own independent list of master tag IDs that allow write access.

Feature list

An overview of the features implemented in the DAM functional block:

  • 64 KB of SRAM depending on the product

    • Organized as 64-bit words
    • Support for byte, half-word, and word access as well as double-word and burst access

  • Protection of DAM SRAM contents

    • Eight programmable address regions can be protected
    • Based on the unique master tag ID, each address range features a programmable list of permitted bus masters for read or write access

Functional description

The DAM SRAM can be used for code execution or data storage, but it lacks hardware safety mechanisms for ASIL B, C, or D applications. The address range of the memory is defined in the system memory map. The memory can be accessed through both cached (segment 9H) and non-cached (segment BH) memory addresses. The SRAM can also be configured as ROM emulation by setting the ROM bit in the MEMCON register. In this mode, all write accesses from the SRI are aborted with an SRI error without the memory content being changed.

The memory performs an integrity check for error detection and correction. This means that when the integrity check is activated, the memory must be initialized before reading to prevent errors caused by data corruption. By initializing with memory integrity logic disabled, the DAM SRAM can support initialization with word (32-bit) or smaller writes as well as 64-bit writes. If the memory integrity check is enabled, a read access that fails the integrity check is aborted with an SRI error condition. This behavior can be changed by setting the MEMCON.ERRDIS bit to 1B. If the bit is set, no SRI error will occur.

The DAM SRAM is internally organized as a 64-bit memory without the possibility of sub-word accesses. This means that any write access to data with less than 64 bits requires an internal Read-Modify-Write (iRMW) operation to write the data correctly and update the ECC data. This is done transparently to the rest of the system unless an uncorrected ECC error is detected during the read phase of the iRMW. This ECC error is reported to the SMU in the same way as an ECC data error that occurs during a normal read operation. In addition, the DAM MEMCON.RMWERR flag is set. The write operation is avoided to prevent writing incorrect ECC data to the memory, where the data could potentially contain an uncorrected error despite a matching ECC.

The DAM enables the definition of eight protected areas of the SRAM memory. The protection only applies to accesses to the SRAM contained in the DAM, not to registers. The protection scheme relies on unique master tag IDs to identify the accessing master and utilizes a six-bit tag to individually identify up to 64 masters.

The DAM implements the standard register protection scheme for peripheral registers using the ACCEN0 and ACCEN1 registers. This allows the DAM control registers to be protected from write access by untrusted masters. Masters are identified by the SRI tag of the access, and if the corresponding bit in the access enable registers is not set, write accesses are interrupted with an error acknowledgment. The protection scheme does not apply to ACCEN0 and ACCEN1 themselves. ACCEN0 and ACCEN1 are protected by Safe Endinit, while all other registers are protected by Endinit. The Endinit and Safe Endinit system status is defined by various watchdog units in the system control unit (SCU).