The PSI5 module communicates with the external world via one I/O line for each channel. The PSI5RXx lines serve as the receive data input signals. If the optional unidirectional mode is utilized, the PSI5TXx signals are transmitted on separate GPIO ports. The receive and transmit paths are always routed to two distinct ports.

Feature list

  • According to PSI5 protocol specification v2.1 and extended powertrain substandard

  • Flexibility in configuration and monitoring for software

    • Supports both Asynchronous and Synchronous data transmission modes (controlled by microcontroller in synchronous mode)
    • Support of enhanced serial messages according to SENT SAE J2716 JAN 2010
    • Three 64-bit downstream data registers for data input, data preparation and data output
    • Sticky interrupt flags, error interrupt optional (default disabled)
    • One sum interrupt for general events
    • One sum interrupt on selectable errors
    • Optional output inversion for use of external open drain transistor
    • Optional input inversion for use of external open transistor for level shifting

  • Receive PSI5 frames based on the protocol standard

    • Data rates of 125 kbit/s and 189 kbit/s are supported
    • Independent and parallel PSI5 channels implemented
    • Supports 6 sensor slots per channel
    • Decoding Manchester protocol
    • Error recognition in Manchester code
    • CRC check of received sensor data implemented but CRC code transparent
    • 24-bit time stamp (resolution: 1 μs)

  • Transmit PSI5 frames based on the protocol standard

    • Support of ECU to Sensor communication
    • Configurable data word length 8, 10, 16, 20, 24 bits according to standard (PSI5 V1.3)
    • Support of non-standard V1.3 frame length: 11 to 33 bits
    • Generation of 3 or 6 CRC bits for downstream data
    • Start sequence and CRC generator for downstream data

  • Message Storage and FIFO access

    • Storage of up to 32 frames per channel with time stamp
    • FIFO access and management
    • Buffer overrun detection
    • Buffer memory status overview registers

  • Sending sync pulses

    • Downstream data transmission by variation of pulse length (PSI5 V2.1)
    • Downstream data transmission by leaving out sync pulses (PSI5 V1.3)
    • Staggering sync pulses of all channels to avoid too many channels sending sync pulses in parallel

Functional description

The PSI5 IP-module performs communication according to the PSI5 specification v2.1 and also supports the extended powertrain sub-standard. PSI5 provides high-speed and high-reliability data transfer.

Figure 1. PSI5 block diagram


The PSI5 kernel consists of 2 independent and parallel PSI5 channels, each supporting 6 sensor slots. The IP also consists of a Manchester Decoding block that decodes the received PSI5 data frames. The Buffer Memory holds up to 32 frames per channel along with the time stamp. The Sync + Data pulse generation block generates sync pulses to trigger a data frame for data acquisition from a sensor or for ECU to sensor communication. The Time Stamp Generation block offers three time bases to select from for Time Stamping.

PSI5 acts as a slave on the FPI bus. The Clock Control block is driven by the system clock frequency fSPB. The Clock Control block produces a total of 5 clock signals. The Peripheral Sensor Interface is used for automotive sensor applications. PSI5 is an open standard based on existing sensor interfaces for peripheral airbag sensors, already proven in millions of airbag systems.

The PSI5 interface provides a current loop based serial communication link typically used to connect airbag sensors or other peripheral devices. While the physical layer is done externally, this module manages protocol handling and data representation to the application. The current to voltage and voltage to sync pulse translation is done externally as shown in the figure below.

Figure 2. PSI5 module connected to external PHY


Receive data on a PSI5 channel can be set up according to the underlying application. In particular the number of bits is configurable. The message storage consists of a 32-bit buffer register for each channel and an additional 32-bit register containing the 24-bit time stamp and additional status bits. These 64 bits per frame are additionally stored in a buffer of 32 lines per channel. In ECU to sensor communication mode, the module can provide regular sync pulses and select between internal and external timer or trigger resources. It also supports setting up the sensor and retrieving sensor status information. The register set of the PSI5 module can be accessed directly by the CPU for configuration, data read out and status query.