The Signal Processing Unit (SPU) is a semi-autonomous accelerator designed to perform Fast Fourier Transforms (FFTs) on data obtained from one or multiple dedicated ADC interfaces. The SPU utilizes a three-stage, streaming architecture to facilitate data pre-processing, FFT computation, and data post-processing operations. For data storage, the SPU leverages the Radar Memory to store datasets, along with internal buffer memories that store the data currently undergoing processing in the pipeline.

Feature list

The radar SPU has the following top level features:

  • Up to 2 concurrent SPU instances active
  • The maximum achievable performance can approach processing 1 sample per clock for large data cubes
  • A 256-bit bus connection to radar memory with 2 clocks required for each read or write access
  • The radar sequencer manages the automatic execution of a linked list, where execution units are reconfigured between computation steps
  • Internal configuration memory for linked lists

  • Two selectable input data flows (ADC interface or main RAM)

    • The ADC interface supports real or complex data
  • Input/output precision selectable: 16 or 32 bits
  • Input DMA with hardware transpose unit and data padding

  • Multiple execution units

    • Complex windowing with hardware support for phase demodulation
    • FFT from 8 to 2048 points
    • 2 x 1D-CFAR, thresholding units implementing 4 CA and 3 GOS algorithms
    • 1 x BIN rejection unit
    • Non coherent integration over two radar SPU
    • Antenna signal integration for elevation
    • Basic thresholding (local maximum detection)
  • RAM size optimization by using configurable FFT strategy (in place, out of place, partially shifted)
  • Output DMA with output FIFOs so that each data flow has its own FIFO and configurable DMA parameters
  • A min/max/average unit
  • A histogram unit up to 4096 elements
  • Support for up to 8 data lanes @ 400 Mbit/s
  • Low speed 60 Mb/s single ended IF
  • The ability to lockstep two SPU units

Functional description

The Signal Processing Unit (SPU) is an accelerator for radar signal processing functions. It is capable of processing radar data autonomously, performing several operations on 3D data in a single configuration without intervention. Data is streamed through the SPU using two pairs of buffer memories. The pre-processor functional sub-block includes a Fast Fourier Transform (FFT) engine as well as MATH0 and MATH1 units that perform pre-processing operations on the data stream, such as interference detection and windowing. The post processor functional sub-block includes the MATH2 unit is capable of performing a number of parallel operations. The ODM outputs data to memory.

Figure 1. SPU block diagram


The SPU runs as a semi-autonomous accelerator performing Fast Fourier Transforms (FFTs) on data from one or more dedicated ADC interfaces. It uses a three stage streaming architecture to provide data pre-processing, FFT, and data post-processing operations. Furthermore, it uses the Radar Memory to store datasets and has internal buffer memories which are used to store the data currently progressing through the processing pipeline.

Processing Flow

The SPU is intended to perform three operations simultaneously:

  • Processing of Input Data into FFT datasets, combining one or more datasets into data blocks
  • Performing an FFT on each of the datasets
  • Postprocessing the datasets and writing the results to Radar Memory

To do this the SPU uses four buffer memories. This imposes a hard limit on the amount of data that can be handled in a single operation. The buffer RAMs are organized in two pairs. The first pair stores input data for the FFT accelerator and the second pair stores the output data from the FFT accelerator. Therefore, the FFT accelerator can work on one set of data while the Output Data Processor is working on the results from the previous set of data and the Input Data Processor is preparing the next set of data.

Each input data block contains enough samples from each attached antenna to perform one FFT for each antenna. This amount of data can be referred to as a ramp and the processing step is referred to as the “inner loop”. The SPU processes a programmable number of these data blocks for each trigger. This can be referred to as a measurement cycle and the overall processing operation is referred to as the “outer loop”. Each completed outer loop sequence generates one complete set of results (a data cube) in the Radar Memory. All arithmetic operations in the SPU are fixed point unless explicitly stated otherwise.