The HSPDM is intended to generate up to two 1-bit bit-streams. Each bit-stream represents the 16-bit data stored inside the dedicated 8 KB SRAM. This bit-stream is a pulse-density modulated (PDM) bit-stream which can be averaged outside the microcontroller using a low pass filter (LPF) to generate the analog voltage.

Feature list

This section lists the features of the HSPDM module:

  • Two independent synchronous PDM bit-streams using the Delta-sigma modulator or bit-streams shifted serially using the shift register up to 160 Mbps
  • Trigger signal to EVADC to signal the start of conversion
  • Programmable offset in EVADC trigger signal
  • MUTE signal output from the microcontroller which can be used to turn on or turn off the external transmitter
  • Support burst mode for fast upload into the SRAM through an addition slave interface (SIF)

Functional description

The Figure 1 shows the architecture of the HSPDM and its interface to other IPs. It also highlights the signal flow from SRAM to bit-stream blocks at the output pads. In a system, HSPDM is conceived to generate an analog signal in conjunction with a LPF implemented external to the microcontroller. The signal-to-noise ratio (SNR) of the generated analog voltage is a function of the cut-off frequency, order and the implementation of the LPF and the frequency of operation of the Bit-Stream block.

Figure 1. High speed pulse density modulation block level diagram


HSPDM generates up to two bit-streams with bit-stream block 0 (BSB0) and bit-stream block 1 (BSB1). The correct mode of operation must be set by the user using CON.SM. The user must not change the mode of operation during the run time. Before changing the mode of operation, the user must stop the bit-streaming by setting the CON.RUNC bit, followed by setting the correct mode of operation using the CON.SM bit and then restarting the bit-streaming by setting the CON.RUNS bit. Mode changes during the run time will result in an undefined behavior of the bit-stream.

Each bit-stream block supports up to three modes of operation (see figure below):

  • Shift register generated bit-stream
  • Delta-sigma modulator generated bit-stream with the CIC filter and the Compactor enabled
  • Delta-sigma modulator generated bit-stream with the CIC filter and the Compactor disabled
Figure 2. HSPDM modes of operation