The Peripheral Sensor Interface is an interface for automotive sensor applications. PSI5 is an open standard based on existing sensor interfaces for peripheral airbag sensors, already proven in millions of airbag systems. PSI5 defines a current loop based serial communication link typically used to connect airbag sensors or other peripheral devices.

While the physical layer is done externally, this module manages communication with this PHY and the presentation of the data to the application. Note that there is no on chip PHY, that is the current to voltage and voltage to sync pulse translation is done externally.

Receive data on a PSI5-S channel can be set up according to the underlying application. In particular the number of bits forming one value is configured.

The message storage consists of a set of 3 32-bit registers for all channels: one PSI5-S Message Receive Data Register containing the received sensor data, one time stamp register containing the 24-bit value and one additional register containing status bits.

For synchronous communication mode, the module can consume sync pulses from the external GTM or generate periodic sync pulses by itself. It supports as well ECU to sensor communication by offering a 32-bit register, where messages can be set up by the CPU. All kinds of sync pulses are translated into a referring, programmable Byte to be sent via ASC.

The register set of the PSI5-S module can be accessed directly by the CPU for configuration, data read out and status query.

Feature list​

General features

  • ASC based communication with compatible PSI5-S PHY

  • Baud rate Generator (up to 12,5) MBaud (@ 200 MHz ASC Sub Module Clock)

  • Clock out generator to supply external PHY

  • Conformance with PSI5 protocol specification

  • Data rates of 125 kbit/s and 189 kbit/s supported (by external PHY already)

  • 8 PSI5-S channels sharing one common ASC (inc. channel 0 frame 1 special use)

  • Supports 6 sensor slots per channel

  • Asynchronous and synchronous PSI5 data transmission modes

  • 8 Interrupt or DMA triggers

Features of message recovery block

  • ASC format 10 Bit: 1 Start Bit, 8 Data bits, 1 Stop Bit (Up Stream)

  • Each PSI5 Frame is transported in a Packet Frame consisting of 3 to 6 UART Frames transmitted back to back, that is with exactly one stop bit - no additional delay

  • Packet Frames are separated by a programmable idle time (1 … 16 idle bits)

  • Assembly and decoding of Packet frames (envelope)

  • Routing of PSI5 Frames to their referring channel receive buffer in system memory by hardware DMA support

  • Checking CRC of Packet Frames (XCRC)

  • Frames with XCRC NOK will be routed to channel 0 frame 1

  • The external PHY sends all Frames of an Asynchronous Channel with FID = 1, all frames of this channel have the same length and structure as defined for FID 1. so it is sufficient to configure frame 1 for asynchronous channels

  • Configurable data length 8 … 28 bit + 3 bit PSI5 CRC or 1 bit PSI5 Parity

  • CRC check of received PSI5 sensor data, CRC code still transparent

  • No hardware Support of extended serial data messaging according to SENT SAE J2716 JAN 2010. Messaging bits are transported fully transparent for software decoding

  • 24-Bit time stamp on sync pulse request via ASC (resolution: 1 µs)

  • Two independent time bases for Time Stamp: clocked by GTM (1 out of n GTM signals is selectable) or internal periodic trigger generator

  • PHY answers to CPU commands with standard frames of fixed predefined length in channel 0 frame 0

  • Error bits in Packet Frame are presented fully transparent and an interrupt is issued

  • One Interrupt for error free Packet Frame, relevant errors are selectable

  • One Interrupt for Packet Frame reception disregarding any error

Features of message generation block

  • Support of ECU to Sensor communication

  • One 32-bit send data register per channel for downstream data input

  • Data is shifted out LSB first, MSB is filled with ‘0’ or ‘1’ with each shift (depending on bit coding method: Tooth Gap or Pulse Width)

  • ASC format 11 Bit: 1 Start Bit, 8 Data bits, 1 Parity, 1 Stop Bit (Down Stream)

  • Downstream commands of fixed format (3 MSB = Channel ID, 5 LSB = Command)

  • All commands are randomly programmable and so not interpreted by PSI5-S

  • Downstream data transmission by 2 different ASC commands (short/no and long pulse)

  • 8 common lines of FIFO for all channels, writable by

  • PSI5 Message Generation

  • Sync Pulse Generation (pre programmed Bytes for ‘0’ and ‘1’)

  • CPU Commands

  • Direct CPU Write Registers allow for insertion of commands into the FIFO for configuration and debugging

  • 8 GTM inputs for Sync Pulse Triggering

  • Software configurable staggering of Sync Pulse generation

  • Generation of 3 or 6 bit CRC for downstream data

  • Start sequence generator for downstream data (can be switched off)

  • Bit stuffing generator for downstream data (can be switched off)

  • CRC generator for downstream data (can be switched off)

  • Internal Loop Back mode for check of CRC generator and software development

Functional description​

The PSI5-S IP-module performs communication according to the PSI5 specification. It communicates with the external world via one ASC interface for all channels. This ASC is built into the PSI5-S module. If the optional bidirectional mode is used, the commands to the external Physical Layer Interface (PHY) are transmitted via this ASC.

Figure 1

shows a global view of the PSI5-S interface.

Figure 1. PSI5-S interface block diagram