Feature list

  • Conformance with the PSI5 protocol specification v2.1

  • Flexible configuration and monitoring using software

    • ASC based communication with compatible PSI5-S PHY
    • Baud rate Generator (up to 12,5) MBaud (@ 200 MHz ASC Sub Module Clock)
    • Clock out generator to supply external PHY
    • Data rates of 125kbit/s and 189kbit/s supported (by external PHY already)
    • 8 PSI5-S channels sharing one common ASC (inc. channel 0 frame 1 special use)
    • Asynchronous and synchronous PSI5 data transmission modes
    • Supports 6 sensor slots per channel
    • 8 Interrupt or DMA triggers

  • Receive data processing using Message Recovery Block

    • ASC format 10 Bit: 1 Start Bit, 8 Data bits, 1 Stop Bit (Up Stream)
    • Each PSI5 frame is transported in a Packet Frame consisting of 3 to 6 UART frames transmitted back-to-back, with exactly one stop bit and no additional delay
    • Packet Frames are separated by a programmable idle time (1 … 16 idle bits)
    • Assembly and decoding of Packet frames (envelope)
    • Routing of PSI5 Frames to their referring channel receive buffer in system memory by hardware DMA support
    • Checking CRC of Packet Frames (XCRC)
    • Frames with XCRC NOK will be routed to channel 0 frame 1
    • The external PHY sends all Frames of an Asynchronous Channel with FID = 1, all frames of this channel have the same length and structure as defined for FID 1. Therefore it is sufficient to configure frame 1 for asynchronous channels
    • Configurable data length 8 … 28 bit + 3 bit PSI5 CRC or 1 bit PSI5 Parity
    • CRC check of received PSI5 sensor data, CRC code still transparent
    • No HW Support of extended serial data messaging according to SENT SAE J2716 JAN 2010. Messaging bits are transported fully transparent for SW decoding
    • 24-Bit time stamp on sync pulse request through ASC (resolution: 1μs)
    • Two independent time bases for Time Stamp: clocked by GTM (1 out of n GTM signals is selectable) or internal periodic trigger generator
    • PHY answers to CPU commands with standard frames of fixed predefined length in channel 0 frame 0
    • Error bits in Packet Frame are presented fully transparent and an interrupt is issued
    • One Interrupt for error free Packet Frame, relevant errors are selectable
    • One Interrupt for Packet Frame reception disregarding any error

  • Transmit message data preparation using Message Generation Block

    • Support of ECU to Sensor communication
    • One 32-bit send data register per channel for downstream data input
    • Data is shifted out LSB first, MSB is filled with ‘0’ or ‘1’ with each shift (depending on bit coding method: Tooth Gap or Pulse Width)
    • ASC format 11 Bit: 1 Start Bit, 8 Data bits, 1 Parity, 1 Stop Bit (Down Stream)
    • Downstream commands of fixed format (3 MSB = Channel ID, 5 LSB = Command)
    • All commands are randomly programmable and therefore not interpreted by PSI5-S
    • Downstream data transmission by 2 different ASC commands (short/no and long pulse)
    • 8 common lines of FIFO for all channels, writable by
    • PSI5 Message Generation
    • Sync Pulse Generation (pre-programmed Bytes for ‘0’ and ‘1’)
    • CPU Commands
    • Direct CPU Write Registers allow for insertion of commands into the FIFO for configuration and debugging
    • 8 GTM inputs for Sync Pulse Triggering
    • Software configurable staggering of Sync Pulse generation
    • Generation of 3 or 6 bit CRC for downstream data
    • Start sequence generator for downstream data (can be switched off)
    • Bit stuffing generator for downstream data (can be switched off)
    • CRC generator for downstream data (can be switched off)
    • Internal Loop Back mode for check of CRC generator and Software development

Functional description

The PSI5-S module performs communication according to the PSI5 specification, communicating with the external world using one ASC interface for all channels. This ASC is built into the PSI5-S. If the optional bi-directional mode is used, the commands to the external Physical Layer Interface (PHY) are transmitted through this ASC.

Figure 1. PSI5-S block diagram


The Peripheral Sensor Interface is designed for automotive sensor applications. PSI5 is an open standard based on existing sensor interfaces for peripheral airbag sensors, already proven in millions of airbag systems. The block diagram shows a global view of the PSI5-S interfaces.

PSI5 defines a current loop based serial communication link typically used to connect airbag sensors or other peripheral devices. PSI5 provides high-speed and high-reliability data transfer. The PSI5-S acts as a slave on the SPB bus. The PSI5-S kernel is composed of the clock control block that is driven by the system clock frequency fSPB.

PSI5-S consists of three main blocks that are shared between 8 channels:

  • Message generation block that is used for preparing the transmit data
  • Message recovery block that processes the received messages
  • Common ASC module

While the physical layer is done externally, this module manages communication with the PHY and the presentation of the data to the application. Since there is no on-chip PHY, the current to voltage and voltage to sync pulse translation is done externally. Receive data on a PSI5-S channel can be set up according to the underlying application. In particular, the number of bits is configurable.

The message storage consists of a set of three 32-bit registers for all channels: one Receive Data Register containing the received sensor data, one time stamp register containing the 24-bit value and one additional register containing status bits.

For synchronous communication mode, the module can consume sync pulses from the external GTM or generate periodic sync pulses by itself. It supports as well ECU to sensor communication by offering a 32-bit register, where messages can be set up by the CPU. All kinds of sync pulses are translated into a referring, programmable byte to be sent through ASC. The register set of the PSI5-S module can be accessed directly by the CPU for configuration, data read out and status query.