The central processing unit implements version 1.8 of the TriCore™ architecture. A device specific number of instances can be used to run the application software. The CPU operation is supported by local SRAMs, a local NVM connection and configuration registers. The TC1.8 CPU block diagram is shown in the figure below:

Figure 1. CPU block diagram

TC1.8 CPU connections​

The TC1.8 CPU contains interfaces to the following memories, interconnect, and bus interfaces:

  • Data scratchpad SRAM (DSPR)

  • Program scratchpad SRAM (PSPR)

  • Data cache (DCache)

  • Program cache (PCache)

  • Distributed LMU memory (DLMU)

  • Local NVM bank (x2 some instances) through the NVM interface (CFI)

  • SRI slave interface for other resources (S-SRI0)

  • SRI slave interface for Local NVM (S-SRI1)

  • SRI master interface (M-SRI)

  • FPI master interface (M-FPI0)

    • FPI0 is always connected to the SPB

  • FPI master interface (M-FPI1)

    • FPI1 can connect to other FPI buses depending on the device and the core instance

The protected paths are:

  • S-SRI0 accesses to PSPR, DSPR, DLMU, SFR, CSFR, or STM

  • S-SRI1 (if present) accesses to CFI, or FSFR

  • PMI or PCACHE accesses to CFI

  • DMI or DCACHE accesses to CFI

  • DMI accesses to local DLMU

TC1.8 CPU units​

The TC1.8 CPU comprises of the following units:

  • TriCore™ based processing unit (CORE)

    • Program memory interface (PMI)

    • Data memory interface (DMI)

  • Special function registers (SFR)

  • Core special function registers (CSFR)

  • NVM special function registers (FSFR)

  • System timer (STM)