The TriCore™ 1.8 central processing unit (TC1.8 CPU) is a superscalar implementation of the version 1.8 of the TriCore™ architecture. TriCore™ is a 32-bit microcontroller-DSP architecture optimized for real-time embedded systems.

The TriCore™ instruction set architecture (ISA) combines the real-time capability of a microcontroller, the computational power of a Digital Signal Processor (DSP), and the high performance and features of a Reduced instruction set computer (RISC) load-store architecture, in a compact re-programmable core.

The ISA supports a uniform, 32-bit address space and memory-mapped Input/Output (IO). The architecture supports both 16-bit (reduced code space and low memory requirement) and 32-bit instruction formats. Real-time responsiveness is supported by low interrupt latency and fast-context-switching. The high performance architecture minimizes interrupt latency by avoiding long multi-cycle instructions and by providing a flexible hardware-supported interrupt scheme.

Compared to version 1.6, version 1.8 of the TriCore™ architecture includes virtualization support and a double precision IEEE-754-2019 Floating-point unit.

Please note that TriCore™ architectural information is defined in the TriCore™ 1.8 architecture manual. Topics covered by that manual include:

  • Architecture overview

  • Programming model

  • CPU registers

  • Tasks and functions

  • Interrupt handling

  • Traps

  • Memory protection system

  • Temporal protection system

  • Floating-point operations

  • Debug

  • Instruction set

  • Virtualization

Note: The optional MMU extension is not implemented in this product family.