The real-time core implementations have the following features:

  • 32-bit load store little-endian architecture

  • 16-bit and 32-bit instructions for reduced code size

  • Single and double-precision floating-point unit (IEEE-754-2019)

  • Virtualization

    • Dual virtual machine support per core with three hardware resource partitions replicating most state

    • Support for one hypervisor, one real-time virtual machine, and up to 6 other virtual machines

  • Temporal protection system allowing time-bounded real-time operation

  • 4 Gbyte address range (2

    32

    )

  • Multiple data types

    • Boolean, integer with saturation, bit array, signed fraction, character, double-word integers, quad-word integers, signed integers and unsigned integers

  • Multiple data formats

    • Bit, byte (8-bit), half-word (16-bit), word (32-bit), double-word (64-bit) and quad-word (128-bit)

  • Byte and bit addressing

  • Multiply and accumulate (MAC) instructions

    • Single 32 x 32 and dual 16 × 16, 16 × 32 architecture

  • Integer arithmetic with saturation

  • Packed data

  • Addressing modes

    • Absolute, circular, bit reverse, long + short, base + offset with pre-update and post-update

  • Instruction types

    • Arithmetic, address arithmetic, comparison, address comparison, logical, MAC, shift, coprocessor, bit logical, branch, bit-field, load and store, packed data and system

  • General Purpose Register Set (GPRS):

    • Sixteen 32-bit data registers

    • Sixteen 32-bit address registers

    • Three 32-bit status and program counter registers (PSW, PC, PCXI)

  • Debug support

  • Flexible memory protection system providing multiple protection sets with multiple protection ranges per set

  • Dedicated system timer with extensions for virtualization