• Compatible with I2C-bus specification version 2.1

  • Master mode supported

  • Multi-master mode supported

  • Slave mode supported

  • Different speed ranges available for data transfer

    :

    • Standard mode up to 100 kbit/s (20 kbit/s - 100 kbit/s)

    • Fast mode up to 400 kbit/s (100 kbit/s - 400 kbit/s)

    • High-speed mode up to 3.4 Mbit/s (500 kbit/s - 3.4 Mbit/s)

  • 7-bit and 10-bit I2C-bus addressing supported

  • Automatic execution of low-level tasks such as:

    • (De)Serialization of the bus data

    • Generation or detection of start and stop signal

    • Generation or detection of acknowledge signal

    • Bus state detection

    • Bus access arbitration in multi-master mode

    • Recognition of device address in slave mode

    • Configurable detection of general call address

    • Configurable repeated start in master mode

  • Flexible clock and timing control:

    • Prescaler for I2C kernel clock (from 0 to 255)

    • Bit rate generation through fractional divider

    • I2C-bus signal timing adjustment

  • FIFO for buffering data from or to CPU with following features:

    • 8 FIFO stages based on 32-bit width

    • Configurable data alignment (byte, half word, word)

    • Configurable sizes for burst, transmit and receive package

    • FIFO usable as flow controller (seamless DMA flow)

  • Advanced interrupt handling:

    • 4 data transfer interrupt requests (burst, last burst, single, last single) resulting in one single data transfer interrupt

    • Protocol interrupt with 7 sources (address match, general call, master code, arbitration lost, not-acknowledge received, transmission end, receive mode)

    • Error interrupt with 4 sources (overflow or underflow of FIFO for transmit or receive)

  • Pretended Networking:

    • High-speed mode, fast mode and standard mode work with the system clock frequency

      f

      I2C

      . that can reach a minimum of 5 MHz