Feature list

• A range of cyclic redundancy code (CRC) polynomials are implemented

  • CRC kernel 0: IEEE 802.3 CRC32 ethernet polynomial: 0x04C11DB7 -

    $x^{32}+x^{26}+x^{23}+x^{22}+x^{16}+x^{12}+x^{11}+x^{10}+x^8+x^7+x^5+x^4+x^2+x+1$

  • CRC kernel 1: Autosar safety polynomial CRC32P4: 0xF4ACFB13 -

    $x^{32}+x^{31}+x^{30}+x^{29}+x^{28}+x^{26}+x^{23}+x^{21}+x^{19}+x^{18}+x^{15}+x^{14}+x^{13}+x^{12}+x^{11}+x^9+x^8+x^4+x+1$

  • CRC kernel 2: CCITT CRC16 polynomial: 0x1021 -

    $x^{16}+x^{12}+x^5+1$

  • CRC kernel 3: SAE J1850 CRC8 polynomial: 0x1D -

    $x^8+x^4+x^3+x^2+1$

  Note: The polynomial hexadecimal representation covers the coefficients (degree - 1) down to 0.

• Parallel CRC computation

• Parallel channels of CRC context

  • Up to 8 parallel channels of CRC context are supported

  • The channels can be configured to use any one of the implemented algorithms

  • Different channels can use the same or different CRC algorithms concurrently

• Register Interface for CRC computation

  • Input register

  • CRC register

  • Configuration registers that enable control of the CRC operation and perform automatic checksum validation at the end of a message

  • Extended register interface to control the reliability of FCE execution in safety applications

  • Supports endianness conversion

• Independent module reset by software

  . The reset affects all CRC channels

• Error notification scheme through dedicated interrupt node for:

  • Transient error detection

    • Error interrupt generation (maskable) with local status register (cleared by software)

  • Checksum failure

    • Error interrupt generation (maskable) with local status register (cleared by software)

• Provides one interrupt line to the interrupt system