The FCE is a standard peripheral slave module which is controlled over a set of memory mapped registers. The FCE is fully synchronous with the peripheral bus clock and runs with a 1:1 clock ratio.

Figure 1. FCE block diagram

An FCE kernel is the instantiation of the CRC algorithm as a parallel matrix. Each FCE kernel implements a different CRC algorithm.

The FCE module contains 8 channels (Channel 0 - Channel 7). Each channel is provided with its own set of registers which allows the software to configure the channel, choose the algorithm kernel used, write the inputs, and read the results and status from the CRC computation.

Each channel has an interrupt associated with it. A status register is associated with each channel that enables the software to identify which interrupt source is active.

To aid fast interrupt handling in software, a channels status register is provided, which ORs together the status from each channel. The software can read this one register to get information regarding the pending status from each channel.

Each FCE channel presents the same hardware and software architecture for computing the CRC. The following chapters only focus on the description of the generic CRC computational flow, since each channel can be independently configured to use any CRC kernel.