Watchdog functions can be used by the application software to monitor the sequence and timing of software tasks and to trigger a software independent hardware reaction if errors are detected. Following figure shows the structure of the WTU.

Figure 1. Internal structure of the WTU

WTU consists of Universal Bus Slave (UBS) on the SPB FPI interface and a total of 8 independent Watchdog Timer (WDT) modules:

  • One watchdog timer per lock-stepped CPU - WDTCPU0-5 (6 total)

  • One watchdog timer for CSRM security CPU - WDTSEC (1 total)

  • One system watchdog timer - WDTSYS (1 total)

Module ID register is a part of UBS.

In addition to the SPB bus interface, each WDT receives SMU state machine signals used for Unlock Restriction (UR) feature which is explained in the following sections. Each of WDT functions provides dedicated register interface, password and timer logic, and a separate alarm signal to the SMU. There is also a 9th alarm output which represents logical "OR" combined alarm output of WDTCPU0-5 and WDTSYS.

More details on internal mechanisms inside each of the WDT is provided in the following sections.

Note: Regarding links to the registers which appear in the further text in this chapter: Every WDT contains same set of registers, so wherever in text there is a link to a register, and if link text does not include WDT prefix (for example link text is just "STAT"), the link would point to the WDTSYS register description, but it represents all registers with that name in all WDTs. If the link contains WDT prefix (for example WDTSEC_STAT) then the link will point to the register description of the respective WDT, and represents only that one register.