• Logic-BIST (built-in self-test) provides a full, automatic test of the digital components within the device

  • To support Logic-BIST, the chip design is clustered into hierarchical scan domains

  • Two LBIST test scenarios are supported:

    1. Key-on LBIST: Targeting only stuck-at faults of on chip functional safety logic within each hierarchical domain

    2. Key-off LBIST: Targeting stuck-at (permanent) faults of all logic within each hierarchical domain

  • Key-on LBIST features:

    • Can be executed automatically during the boot sequence of the device (using default firmware configuration) or started manually based on user software trigger

    • Key-On LBIST only involves safety-relevant flip-flops (~8-10% of total flop count) within any hierarchical domain. Other flip-flops are not toggled

    • Target stuck-at coverage: 90%

    • Target execution time: t

      LBIST

    • Because of the reduced toggle rate, multiple hierarchical scan domains of the chip design can be tested in parallel

  • Key-off LBIST features:

    • Can be configured and started for a single or multiple hierarchical domains by user application software.

    • Key-off LBIST involves all flip-flops within a hierarchical domain, therefore in case of a multiple domain configuration the key-off LBIST will test the selected domains sequentially

    • Target stuck-at coverage for full digital hierarchical domain: 90%

    • Target execution time for stuck-at test: 50 ms per hierarchical scan domain

  • Number of patterns (that is the number of shift and capture sequences) can be configured. For stored Multi Input Shift Register (MISR) signatures a specific key-on and key-off configuration is provided

  • After any LBIST execution, the system will execute a LBIST reset and reboot automatically

  • Execution status and MISR results are provided for each hierarchical domain after reboot of the device, to be compared against golden signatures by application software

  • LBIST power reduction features:

    • Configurable clock frequency for LBIST controller (affecting scan-chain shift and capture speed)

    • Split-shift:

      • Allows to distribute each scan shift cycle to 2 or 4 clock pulses to reduce the current jump for each shift clock pulse

    • Key-On LBIST to cover the functional safety logic (for example the lockstep compare logic in CPU) exclusively involves safety-relevant flip-flops (8-10%) within any hierarchical domain