Logic-BIST is an automatic structural self-testing mechanism, which is based on the structural scan test approach. It serves two main purposes:

  • Safety measures (“key-on”): 90% stuck-at test coverage on all safety monitoring logic (lock-step comparator, ECC, SMU, …) within 5-6 ms execution time at system start-up

  • In-system test (“key-off”): 90% stuck-at test coverage on all digital logic in 50 ms execution time per hierarchical scan domain at system shut-down

Due to complexity the device is divided into several hierarchical scan domains. Domain structure (number, complexity and LBIST runtime per domain) varies from device to device. Start of LBIST in any hierarchical domain brings the entire device automatically to scan mode during which no functional operation is possible. During LBIST execution the IOs reflect a static reset behavior.

The execution of Logic built-in self test in the microcontroller application mode is based on the design for test structures implemented for production testing and therefore reusing scan chains, control, and status mechanisms already available in microcontroller. The scan test operation is enabled through dedicated pseudo-random pattern generator (PRPG) modules, which generate patterns to be applied to the corresponding hierarchical domains. The PRPG generates pseudo-random patterns using a linear feedback shift register (LFSR). These patterns are loaded (this mean serially shifted) into the design scan-chains.

Figure 1. Hierarchical LBIST architecture

It shall be noted, that LBIST is a scan based structural test method which also covers the redundancy logic of the SRAMs within each hierarchical scan domain. Therefore the SRAM contents is not reliable after LBIST execution except for the Stand-by controller (SCR) SRAMs.

In the following sections the general LBIST operation scheme, possible configuration options and application scenarios are explained. In this conjunction also the LBIST integration into a hierarchical scan architecture is shown.

Figure 2. TRI block diagram

LBIST operation is controlled through a central LBIST supervisor logic, which resides in the test register interface (TRI) block. From this central supervisor all LBIST operations are controlled through a single state machine (LBIST FSM). From application side the LBIST operation is accessed by writing and reading specific LBISTCTRL registers through the SPB interface (SPB-IF). In this way a specific LBIST configuration (LBIST config) is handed over to the LBIST supervisor.

Once LBIST operation is started, the LBIST supervisor block configures the hierarchical LBIST controllers (Hierarchical LBIST Ctrl) through an iJTAG interface (iJTAG-IF). These hierarchical LBIST controllers are part of the hierarchical TRI interface (HDI), which is implemented within each domain. The LBIST translation interface and the in-system-test block within TRI will be used to establish a data communication between LBIST supervisor and the hierarchical LBIST controllers.

After initialization of the hierarchical LBIST controllers the LBIST supervisor will start each hierarchical LBIST operation individually through a lbist_run_req signal. It will then await the successful termination of the LBIST operation in each domain, which is indicated through individual lbist_done signals. As soon LBIST operation in all domains is finished, the LBIST supervisor block captures the domain individual MISR signature results (scan_misr) and triggers a LBIST reset to the whole system.

After LBIST operation is finished the LBIST FSM has to be set into a safe reset state through a specific RESET bit within the LBISTCTRL registers.

Specific alarm signals are defined to indicate any unwanted LBIST activity within the TRI to SMU. These alarms are processed through the test control unit (TCU) and can be triggered manually for testing purpose through the ERRINJ bit within the LBISTCTRL registers.