The main purpose of the QSPI module is to provide synchronous serial communication with external devices using clock, data-in, data-out and slave select signals. The focus of the module is fast and flexible communication. This can be either point-to-point or master-to-many slaves communication.

Parallel requests from on-chip bus masters to a module will be executed sequentially through the on-chip bus system. A read-modify-write feature provides an atomic read and write sequence where no other master can access the module in between operations. Module hardware semaphores are not supported.

Figure 1. QSPI block diagram

Note: In CLOCK chapter this fPER is referenced to as fQSPI for overview purposes

The figure above shows a high level overview of the QSPI module. The two clock domains of register interface and shift engine are shown, the connection to ports and interrupts. The latter has independent request lines for TX-interrupt (TX_INT), RX-interrupt (RX_INT), Error-interrupt (ERR_INT), Phase transition-interrupt (PT_INT) and User-interrupt (U_INT). These interrupts are connected to the following inputs of the IR: SRC_QSPIwTX, SRC_QSPIwRX, SRC_QSPIwERR, SRC_QSPIwPT, SRC_QSPIwU.