• Master and Slave mode operation

    • Full-duplex operation

    • Half-duplex operation

    • Automatic slave select control

    • Four-wire and three-wire types of connection

  • Flexible data format

    • Programmable number of data bits: 2 to 32 data bits (plus parity: 3 to 33 bits)

    • Programmable shift direction: least significant bit (LSB) or most significant bit (MSB) shift first

    • Programmable clock polarity: Idle low or idle high state for the shift clock

    • Programmable clock phase: data shift with leading or trailing edge of the shift clock

  • Baud rate

    generation

    • Baud rates generated from high precision phase locked loop (PLL) clock, asynchronous to the system PLL

  • Interrupt generation

    • On a transmitter first-in first-out memory (FIFO) event

    • On a receiver FIFO event

    • On an error condition (receive, baud rate, transmit error, parity error)

    • On a phase transition (At the start of frame for example, or the end of frame)

  • Supports control and data handling by the direct memory access (DMA) controller

  • Flexible QSPI pin configuration

  • Hardware supported parity mode

    • Odd, even, or no parity

  • Seven slave select inputs

    SLSIA...G

    in Slave mode

  • Sixteen programmable slave select outputs SLSO[15:0] in Master mode

    • Automatic SLSO generation with programmable timing

    • Programmable active level and enable control

    • External de-multiplexing of the slave select outputs support

    • Multiple slave select activation (up to 4 slave select outputs)

  • Transmission triggering from external timer

  • Several module reset options

    • State machine reset per software (only the state machine)

    • Module reset per software (both FIFOs, all registers, and the state machine)

    • Automatic stop option of the state machine in slave mode after baud rate error

  • Loop-Back mode

  • Interoperability with SSC (Synchronous Serial Channel) and USIC (Universal Serial Interface Channel) modules of Infineon microcontroller families, and with popular (Q)SPI interfaces of multiple suppliers

  • Communication stop on RxFIFO full

    • Shift register full and RxFIFO full can pause the communication

    • Interrupt generation

Note: Baud rate generation: The maximum baud rate achievable in a particular connection is limited by the timings of both the master and the slave chips, as defined in the corresponding data sheets. Important considerations are the type of Input/Output (I/O) pads used, for example Low Voltage Differential Signalling (LVDS) or Complementary Metal Oxide Semiconductor (CMOS) pads, the I/O power supply voltage, the configured output driver strength, and the allowed electromagnetic radiation and temperature. Due to temperature and voltage change there is variation in loop delay. To compensate that run-time adjustment of sampling point by application software might be required for baud rate higher than 20 Mbit/s