The DMA moves data from source locations to destination locations without the intervention of the CPU or other on chip devices.

A data move is controlled by the transaction control set of an active DMA channel and is executed by a move engine. The transaction control sets are loaded into the DMARAM either directly through software writes through the configuration interface, or indirectly through linked list operations.

A DMA channel is activated by a DMA request, which can be a software request, a hardware request or a daisy chain request. DMA channels can be configured to raise an interrupt on transaction completion or other events. DMA channels are each assigned to a unique resource partition and inherit the access enable rules and master tag identifiers of that resource partition.

Figure 1. SDMA block diagram

The DMA is configured by software over the FPI_SIF interface and implements access protection to provide functional freedom from interference between different applications using the DMA.

Each DMA channel stores the context of an independent DMA operation in a transaction control set (TCS). Each application can configure and use one or more DMA channels. The DMA channels can be triggered by software requests, through hardware requests coming from the interrupt router (IR), or through other internal triggers. All DMA channels with pending DMA requests are then arbitrated so they can begin processing on one of the available move engines (MEs). DMA moves generated by the MEs result in read and write transactions being sent out through the DMA master agents FPI_MIFx and SRI_MIFx onto the system interconnect.

Each DMA channel can be configured to generate interrupts to the IR for completion and other events on the CHc interface. The DMA resource partitions (RPs) can also generate error interrupts to the IR on the ERRr interface. Errors which cannot be attributed to a single resource partition are reported to the IR through the GERR interface.

The DMA also implements interfaces to various infrastructure components for clocks, resets, sleep and shutdown requests. It implements debug and trace functionality through the interfaces with the DEBUG and TRACE functional blocks. The DMA debug and trace functions for CS resource partitions can be disabled by the CSRM through the CSAV interface.

The DMA also generates alarms for safety relevant events to the SMU.