• Safe movement of data

    • The DMA implements a lockstep mechanism using a redundant checker core for safety

    • The DMA implements ECC protection on the DMARAM

  • Ability to detect patterns in DMA move data

    • Pattern detection can be configured on 8-bit, 16-bit, and 32-bit data moves

  • Virtualization and resource partitions to provide freedom from interference

    • The DMA implements virtualization using the concept of resource partitions (RPs). Each DMA instance implements up to 16 RPs

    • An application in one RP running a set of defined DMA move functions has functional freedom from interference from another application running another set of defined DMA move functions in a different RP

    • Each RP has independent access protection controls which enable individual Master TAG identifiers, virtual machine IDs, and protection register sets (PRS) to have read and write access to the RP and assigned DMA channels

    • Each RP may be assigned to a cyber-secure or non-cyber-secure group and only interrupt requests from the same group may trigger DMA hardware requests

    • Each RP can be configured with a master agent function tag identifier, a virtual machine number (VM), a protection register set (PRS), user or supervisor mode, and secure master identification to be driven onto the system interconnect during a DMA move

  • Multiple independent DMA channels which can be individually programmed and scheduled

    • Each DMA channel may be assigned to a resource partition

    • Each DMA channel's transaction control set is stored in the DMARAM

    • The DMA channel source and destination address pointers support 32-bit wide address counters

    • Programmable data width of DMA moves

  • Multiple move engines to support parallel servicing of DMA requests

    • Any move engine can service a DMA request from any DMA channel

    • Arbitration rules to pick the highest priority DMA channels with pending DMA requests for service by the move engines

    • SRI-source to SRI-destination data block moves up to 16 Mbyte DMA moves per DMA transaction

    • FPI-source to FPI-destination data block moves up to 8 Mbyte DMA moves per DMA transaction

  • Multiple ways to request DMA move operations or chains of DMA move operations

    • DMA software requests

    • DMA hardware requests triggered by hardware interrupts

    • DMA daisy-chain requests to automatically trigger successive channels

    • Linked list and conditional linked list operations - the current DMA transaction can load the next DMA channel transaction control set (TCS) into the DMARAM by overwriting the existing DMA channel TCS. The next DMA transaction can be auto-started

  • Generation of interrupts and alarms

    • Channel completion, pattern match and circular buffer wrap interrupts

    • Resource partition, and global error interrupts

    • Safety alarms generated on all safety events such as lockstep mismatches and EDC errors

  • DMA timestamp

    • The DMA channel can be configured to write out a timestamp when the DMA transaction is completed. This timestamp can be used by application software to implement temporal monitoring of data transfers

  • DMA CRC computation

    • The DMA channel can be configured to compute a CRC on the addresses or data transferred during a DMA transaction using the IEEE 802.3 CRC32 algorithm