Blocks of the NVM sub-system​

The following figure shows the NVM sub-system and the interfaces to CPU and SRI.

Figure 1. NVM block diagram

Block descriptions​

Table 1. Blocks within the NVM sub-system

Sub-system block

Sub-function

Description

DMU

_

Command Interface Block to System:

  • Command Decoding of Flash Operation Requests from CPU or other SRI Bus masters

  • Check of write, read, write_once, and OTP protection

  • Check of security settings of memory regions

  • Flash operations to protected memory regions will be prevented

Read port and access control for: DFLASH Banks, UCB and BootROM

FSI_x

_

NVM internal CPU for execution of Flash Operation commands such as program, erase, or verify.

It has its own storage for firmware for Flash operations

ANALOG_x

_

Central hardmacro block containing chargepumps mainly used for program or erase operation

PFLASH[x]

_

PFLASH bank.

A bank containing memory cells for code or data storage of the CPUs, and also containing peripheral circuitry for read, write, or erase operations, 278-bit data output (256-bit data and 22-bit ECC checkbits).

Each Bank has a separate address or read path and one bank can be programmed or erased while the other banks are being read (read-while-write support)

PFLASHcs

_

PFLASH bank (as above).

Can be set to be exclusively readable, programmable, or erasable by the security CPU

PFRWB[x]

_

PFLASH Read Write Buffers.

Digital Interface to the hardmacro PFLASH banks containing address muxes, read buffers, ECC correction, and also control registers for the PFLASH bank

DFLASH[0]

_

Bank containing memory cells for the EEPROM, UCB, and CFS sub-functions.

Shared bitline and other read, program or erase peripheral circuitry for operation

EEPROM

For the storage of data which needs to be frequently updated during its lifetime

Config Sector (CFS)

Internal parameters and settings of the NVM and the system. Not accessible by the application software

User Configuration Blocks (UCB)

Infineon and user settings.

Part of it can be changed by customer production equipment or application software

DFLASH[1]

_

Separate bank for the EEPROM, UCB, and CFS sub-functions, which can be set to be exclusively readable, programmable, or erasable by the security CPU

EEPROM

For the storage of data which needs to be frequently updated during its lifetime

Config Sector (CFS)

NVM and system internal parameters and settings. Not accessible by the application or security software

User Configuration Blocks (UCB)

Infineon and user

settings.

Part of it can be changed by customer production equipment, application and security software

DFRWB[x]

_

DFLASH Read Write Buffers.

Digital Interface to the hardmacro DFLASH Banks containing address muxes, read buffers, ECC correction and also control registers for the DFLASH Bank

BROM

_

ROM containing the startup software (SSW)