• Storage of CPU code and data in several Program Flash (PFLASH) banks with fast read access

    • Independent read access to the banks

    • Read-while-Write capability between the banks

  • Storage of EEPROM data in dedicated Data Flash (DFLASH) banks

    • High write or erase cycling endurance

    • DFLASH write or erase while PFLASH read possible

  • Security code and data can be stored in separate banks with access protection to the security CPU

  • User Configuration Block (UCB) for microcontroller and application specific configuration storage

  • Write and erase operations include a verify operation to check the correct cell distribution of programmed and erased bits after the operation

  • Two different write operations:

    • Write page with minimum Error Correction Code (ECC) width

    • Write burst for high throughput: more data with one operation

  • Erase operation with adjustable range from minimum logical sector size of 16 KB PFLASH and 2 KB DFLASH, up to 512 KB PFLASH and 256 KB DFLASH

  • Write (burst) and erase operations may be aborted to allow the start of an other operation

  • Replace Logical Sector (RLS) repair function usable by application software in the field to replace a failing logical sector by a free redundant sector

  • Separate erase counter for each PFLASH bank: each erase operation in the PFLASH bank is counted and up to 500 entries are possible

  • Data integrity check operations

  • BootROM for microcontroller start-up software (SSW)