• Compliant with the PCI Express™ specification, revision 5.0 Version 1.0

  • Gen3 data rate, x1 lane up to 8 GT/s (giga-transfers per second)

  • Dual mode: either root complex or endpoint

  • Programmable Base Address Register (BAR) addressing: 32 bit or 64 bit

  • Programmable BAR sizing

  • 256 byte maximum payload size (MAX_PAYLOAD_SIZE)

  • Requester and completer function support for PCIe transactions

  • Interrupt generation and reception

    • INTx support

    • MSI support, up to 32 interrupts

    • MSI-X support, up to 64 interrupts

    • Additional support for non-standard interrupt reception in endpoint mode

  • Power management

    • D0, D3

      hot

      and D3

      cold

      support

    • L0, L0s, L1, L1 sub-states, L2, and L3 support

    • Reference clock power management with CLKREQ#

    • Active-State Power Management (ASPM) support

    • PCIe beacon and wake-up (WAKE#)

  • Embedded Direct Memory Access (DMA) support

    • 4 read and 4 write DMA channels

    • Linked list support

    • Remote configurable DMA channels (EP only)

  • Address translation unit

    • 8 translation regions for inbound transactions

    • 8 translation regions for outbound transactions

    • Transaction type conversion

  • Baseline and Advanced Error reporting (AER) support

  • One physical function implemented in endpoint mode

  • Optional end-to-end cyclic redundancy (ECRC) support

  • Accesses to the System-on-Chip (SoC) memory and registers from wire

  • Spread Spectrum Clocking (SSC) support

  • Optimized Buffer Flush/Fill (OBFF) support

  • Precision Time Measurement (PTM) support

  • Latency Tolerance Reporting (LTR) support

  • Readiness notification support

  • Advanced on-chip debug support (OCDS) trigger bus (OTGB) trace support

  • Safety measures for registers, memory, and data path against random hardware faults