PCI Express is a high performance, general purpose I/O interconnect for a wide range of applications. The interface is compatible with the PCI Express™ Base Specification, Revision 3.1a. The target of this manual is not to document the PCIe protocol. This manual describes mainly how to use the PCIe interface and only basic concept of the PCIe protocol.

The PCIe interface can be configured as a root complex or an endpoint after the power-on. Afterwards, the work mode cannot be changed without resetting the PCIe interface. The speed of the PCIe interface can be Gen1, Gen2 and Gen3. An embedded DMA is designed to offload the CPU by using DMA transfers. In addition, an address translation unit provides flexible mapping between the PCIe wire address and the SoC internal address.

The PCIe interface consists of two sub-blocks, namely the PCIe controller and the HSPHY (PCIe PHY), as shown in the following figure. An SRI master interface and an SRI slave interface are used for data transfer while two SPB slave interfaces are only for the configuration purpose. The interface connects to interrupt router (IR), safety and security alarm management unit (SMU) and TRACE for the common infrastructure functionalities.

Figure 1. PCIe block diagram