The LMU SRAM can be used for code execution, data storage or overlay memory. The address range of the memory for each LMU instance is defined in the system memory map. The memory supports being aliased to more than one address range, for example, cached and non-cached segments. A block diagram of the LMU is shown below.

Access to the SRAM is protected by 16 Access Protection Units (APUs), each of which can be configured to limit access by masters to a configurable memory range. By default (after reset), read access is allowed by any master to the whole memory and write access is restricted to certain masters, details of which can be found in the reset value of

RGNx_ACCEN_WRA

. The safety configuration and monitoring registers are protected by

PROTSE

.

The memory implements memory integrity checking for error detection and correction.

This means that the memory must be initialized before reading with the integrity checking enabled to avoid generating spurious data corruption errors. Initializing with the memory integrity logic disabled allows the LMU SRAM to support initialization using word (32-bit) or smaller writes. Initialization using

-bit writes is always possible.

If memory integrity checking is enabled, a read access which fails the integrity check will cause an error condition to be flagged to the initiating bus master. This behavior can be changed by setting the

MEMCON

.ERRDIS bit to

1

. If ERRDIS is set, the access will terminate without an integrity error being reported to the SRI. The ERRDIS bit-field of the

MEMCON

register is protected by the

MEMCON

.ERRDISWE bit. If the data written to the register has the

MEMCON

.ERRDISWE bit set to

0

, no change will be made to ERRDIS regardless of the data written to the field.

An alarm will be triggered whenever there is an ECC error, regardless of the value of

MEMCON

.ERRDIS.

The SRAM can be written as a -bit memory without using internal Read-Modify-Write (iRMW) operations. Any write access of less than bits of data results in an iRMW operation to correctly write the data and update the ECC data. This happens transparently to the rest of the system unless an uncorrected ECC error is detected during the read phase of the iRMW. Any such ECC error will be flagged with an alarm in the same way as a data ECC error occurring during a normal read. In addition, the MEMCON .RMWERR flag will be set. The write operation will not take place as this would write potentially incorrect data to the memory.

Figure 1. LMU block diagram