SCU provides common CPU and system functions that include trap handling, global overlay control, SOTA swap control, ERU triggering and chip information. The main components of the SCU are illustrated in the following figure.

Figure 1. SCU block diagram


Trap/NMI handling for both non-secure and secure CPUs is done inside TR block. ERU block provides cross triggering functionality, connecting several ports and peripherals as sources to interrupt controller, SMU, ADC, timers and other peripherals as destinations. Beside TR and ERU functions, SCU also includes several control registers for common CPU and system functionality: memory overlay, SOTA swap control and basic chip information.