This following figure provides a simplified system overview in the form of a block diagram.

Figure 1. xSPI block diagram

The xSPI kernel is connected to the SRI slave via the SRI to AHB bridge and SRI master via SRI to AXI bridge. Access to host control registers and memory mapped register space via XIP takes place through SRI slave interface. Data transfers from/to external memory to/from internal memory space takes place through an internal Direct Memory Access(DMA) engine via the SRI master interface. Any type of non DMA mode data transfers takes place through the SRI slave using the internal tx and rx FIFO memory.

All the safety related interrupts are grouped under two alarms XSPIDATAADD (XSPI data address error alarm) and XSPIFSM(XSPI FSM alarm) that interfaces to SMU (Safety and security alarm Management Unit). Similarly, the non safety related interrupts are grouped under two interrupts XSPIFIFO and XSPIERROR that interface to IR (Interrupt Router).

The HSPHY functional block contains the DLL (Delay Locked Loop) along with Port 16 IO (Input Output) pad related SFRs that can be accessed via an SPB interface. The xSPI receives two times the f

xSPI

clock called f

XSPI*2

from the HSPHY. The SSI_clk is the internal peripheral kernel clock that is used to generate the Sclk_out. The BAUDR register helps in scaling the SSI_clk if needed, to obtain the desired output clock Sclk_out. The Sclk_in is used to sample the incoming data during data reads.

The xSPI can be used either on :

  • Port 16 through the HSPHY and HSFAST pads (pads specialized for xSPI performance) at maximum performance using f

    xspi*2

  • Or over GPIO pads through the PORTS in a reduced speed mode in quad SDR mode only, using f

    XSPISL

    clock

Note: One of the signal (TXD3/RXD3) belonging to port 20 Quad mode implementation is routed to port 15. Since there is only one instance of xSPI in any device, the xSPI cannot be used in parallel, on both port 16 and over other ports with GPIO pads