• Physical SoC interface for externally provided clocks (crystal oscillator (

    XTAL OSC

    ) or HSSL system clock (

    SYSCLK

    ))

  • Internally generated back-up clock provided by an embedded voltage regulator (

    EVR

    ) oscillator for independent operation in the absence of a crystal clock

  • Internally generated linear ramp clock to support power-up and power-down, reset, and emergency operation with low supply voltage drops and low current peaks

  • Up-scaling of externally supplied clocks up to a maximum frequency of

    f

    PLL0 as specified in the datasheet, phase locked loops (System

    PLL

    )

  • Up-scaling of externally supplied clocks up to a maximum frequency of

    f

    PLL1,

    f

    PLL2 and

    f

    PLL3 as specified in the datasheet, phase locked loops (Peripheral

    PLL

    )

  • System clock domain with frequency modulation to reduce electromagnetic interference (EMI)

  • Peripheral clock domain with low jitter and low noise to comply with jitter and the signal-to-noise ratio requirements of selected communication protocols and analog to digital converters (

    ADC

    )

  • Peripheral clock domain with frequency modulation for optional use to reduce EMI

  • Low skew distribution of all system clocks to enable global synchronous operation within the microcontroller unit (

    MCU

    )

  • Independent generation and distribution of all system and peripheral clocks

  • Software programming interface for clock configuration and status observation

  • Clock monitoring to support ASIL D safety protection and security

  • Provision of selected internal system and peripheral clocks to physical outputs of the MCU

  • Reset support functions (clock gating and frequency adaptation)