Functional overview

The SDMMC controller supports SD-card, eMMC and SDIO interfaces. It contains a DMA engine for data transfer, a registers unit, and a FIFO controller.

Figure 1. SDMMC block diagram

The figure above provides a simplified overview of SDMMC in the form of a block diagram.

The SDMMC kernel is connected to the SPB slave through the FPI to AHB bridge and SRI master via AHB to SRI bridge. Access to host control registers takes place through slave interface. Data transfers from or to external NAND memory to or from internal system memory space takes place through an internal Direct Memory Access(DMA) engine through the master interface. The slave and master clock domain runs at a frequency of f

SPB

The card clock domain runs at the peripheral frequency of f

SDMMC

. The Host controller accesses the external memory device over the GPIO pads belonging to the PORTS functional block. SDMMC has a single port RAM for packet buffering interfacing the FIFO controller.