The block diagram of the HSSL module is shown in the following figure:

Figure 1. HSSL block diagram

Note: The bus interface used by the HSSL module is defined in the device specific chapter.

The HSSL has one alarm, called 'HSSL SRI Read Data EDC Error' interfacing to the SMU (EDC stands for Error Detection and Correction). For the alarm description please refer to the alarm mapping tables in the SMU functional block and the safety manual. A set of 17 interrupts are mapped to IR(Interrupt Router), four types of channel specific interrupts per channel and one module interrupt. In order to support the debugging activities, the HSSL provides a set of internal signals to the on-chip debug system OCDS (On Chip Debug System) through OTGB (OnChip Trigger Generation Bus) trigger buses.

The HSSL sub-module provides point-to-point communication for both single data values and large data blocks, called streams. The functionality of each of these channels is further sub divided as 'transmitter and receiver' and 'Initiator and target' controllers by the HSSL channel controller. The communicating devices can be complex micro controllers, or a microcontroller and a device with only basic execution capabilities. There are four channels to transfer single values to/from target. They support direct writing of 8/16/32 bit data from the initiator into a target’s local address map (e.g., registers and memory), as well as reading a value from a target, performed by a modules internal SPB/SRI bus master on the target side. For transferring large data blocks there is a channel containing FIFOs. The HSSL module implements transport layer tasks and hands over the data to another module which provides data link layer and physical layer services, data serialization and transmission. All transfers are protected by safety features like CRC and timeout. The SRI and SPB master interface on the target HSSL helps in accessing the peripherals on the corresponding bus. The SPB slave interface helps in accessing the special function registers of HSSL.

The SRI master interface is capable of performing both single and burst reads and writes on the SRI bus. The SPB slave interface is used by an SPB master (DMA, CPU, HSSL SPB Master) for writing the HSSL SFRs, so configuring the module and performing single read and write operations.

High Speed Communication Tunnel (HSCT)​

The lower layer companion module and logic control the lower communication layers positioned between two devices, the data, and the physical layer. They consist of the High Speed Communication Tunnel (HSCT) and pads. For more information on the lower communication layers, see the HSCT chapter. The SPB slave interface helps in accessing the special function registers of HSCT.

The chip-to-chip interface employs a digital interface for inter chip communication between a master or a slave HSCT instance. The interface is capable of running in a master or in a slave HSCT mode. During configuration phase the role of the Interface (master or slave) has to be defined. It is not intended to change the system role after initialization and start-up. The HSCT controller consists of framer, deframer and the corresponding FSMs(finite state machines) along with the SFRs controlled via SPB slave interface.

The interface consists of a full-duplex RX and TX high-speed data interface based on double ended differential signals (in total 4 lines) and a master clock interface (SYSCLK_OUT). The master IC owns the crystal and provides the clock to the slave. The interface reset is derived from the System reset and provided by chip internal reset signaling.