Each port line has a number of control and data bits, enabling very flexible usage of the line. Each port pad can be configured for input or output operation.

Figure 1. PORTS block diagram

For the alarm description please refer to the alarm mapping tables in the SMU functional block and the Safety Manual.

The available features depend on the type of pad. For example, input-only pads (e.g. SENT pads) do not offer output control. In this text we describe the capabilities of a general CMOS pad. The section on LVDS Port Operation adds information for switchable LVDS or CMOS pads.

In input mode, which is the default mode after reset, the output driver is switched off (high-impedance). The actual voltage level present at the port pin is translated into a logical 0 or 1 through a Schmitt-Trigger device and can be read with the read-only register

IN

. Input signals are connected directly to the various inputs of the peripheral units. The function of the input line from the pin to the input register

IN

and to the peripheral is independent of whether the port pin operates as input or output. This means that when the port is in output mode, the level of the pin can be read by software through

IN

or a peripheral can use the pin level as an input.

In output mode, the output driver is activated and drives the value supplied through the multiplexer to the port pin. Switching between input and output mode is accomplished through the

PADCFGp_DRVCFG

register, which enables or disables the output driver. If a peripheral unit uses a GPIO port line as a bi-directional IO line, register

PADCFGp_DRVCFG

has to be written in order to configure input and output settings according to system's needs. The

PADCFGp_DRVCFG

register further controls the driver type of the output driver, and determines whether an internal weak pull-up, pull-down, or without input pull device is alternatively connected to the pin when used as an input.

The output multiplexer in front of the output driver selects the signal source for the GPIO line when used as output. If the pin is used as general-purpose output, the multiplexer is switched by software (

PADCFGp_DRVCFG

register) to the Output Data Register

OUT

.

The status of

OUT

can be changed through separate

OMSR

or

OMCR

registers.

The set or clear operations for the bits in

OUT

can be made by setting the corresponding

PADCFGp_GPIO

.SET and

PADCFGp_GPIO

.CLR registers. Alternatively, the set, clear, or toggle function can be achieved through

OMR

, where all pins within the same port can be set, cleared, or toggled within one write operation. The manipulation of the control bits in these registers can directly influence the state of the port pin. If the on-chip peripheral units use the pin for output signals, the alternate output lines ALT1 to ALT15 can be switched through the multiplexer to the output driver.

The data written into the output register

OUT

by software can be used as input data to an on-chip peripheral. This enables for example, peripheral tests using software without external circuitry (ALTIN path).

When selected as general-purpose output line, the logic state of each port pin can be changed individually by programming the pin-related bits in the

  • Port n Output Modification Set Register:

    OMSR

    .PSx (where x_0 through to 15)

  • Port n GPIO Control Register for Pin p:

    PADCFGp_GPIO

    .SET

  • Port n Output Modification Clear Register:

    OMCR

    .PCLx (where x=0 through to 15)

  • Port n GPIO Control Register for Pin p:

    PADCFGp_GPIO

    .CLR

  • Port n Output Modification Register:

    OMR

The bits in

OMSR

and

OMCR

make it possible to set and clear the bits in the

OUT

register.

The bits in

OMR

allows the bits in

OUT

to be set, cleared, toggled or remain unchanged.

When the GPIO is selected as general-purpose output line, its actual logic level at the pin can be examined through reading

IN

and compared against the applied output level, either applied through software through the output register

OUT

, or through an alternate output function of a peripheral unit. This can be used to detect some electrical failures at the pin caused through external circuitry. In addition, software-supported arbitration schemes can be implemented in this way using the open-drain configuration and an external wired-And circuitry. Collisions on the external communication lines can be detected when a high level (1) is output, but a low level (0) is seen when reading the pin value through the input register

IN

.

Most of the digital GPIO lines have an emergency stop logic. This logic makes it possible to individually disconnect outputs and put them onto a well defined logic state in an emergency case. In an emergency case, the pin is switched to input function with internal pull-up device connected or tri-state (depending on global configuration). The Emergency Stop Register

PADCFGp_SAFSEC

determines whether an output is enabled or disabled in an emergency case.

LVDS port operation​

The LVDS pads offer LVDS RX or TX functionality for a pair of pins. Additionally, they contain, if not specified differently, a bi-directional CMOS pad for each of the pins. The CMOS functionality is controlled by the set of standard registers. The LVDS functionality is controlled by additional

LPCRx

.LRXTERM registers.