• XC800 core

    • Based on the standard 8051 8-bit core

    • Two clocks per CPU cycle architecture, for memory access without wait state

    • Two data pointers

    • Maximum 100 MHz frequency

  • On-chip memory

    • 4-Kbyte boot ROM for start-up and debug firmware

    • 256-byte internal memory; plus 64-byte Monitor memory

    • 32-Kbyte XRAM for program code and data

    • XRAM accessible by the TriCore™ domain CPUs through the SPB bus and XRAM arbiter

  • Real-time clock (RTCSCR) to support periodic wake-up in standby mode

    • Support for crystal oscillator inputs - 32 kHz crystal from XTAL3/4 or external from SCR_P1.2 (P33.10)

    • Access to 64-bit Real-time Clock (RTC) and Die-Temperature Sensor (DTS) located in PMS address space

  • Four general purpose I/O ports with up to 32 pins

    • Control of the shared pins in SCR Ports P0, P1, P2, and P3 (overlaid with Ports P32, P33, P34 and P35 of the TriCore™ domain)

  • Two 16-bit timers T0 and T1 for general purpose usage (tightly coupled with the XC800 core)

  • Two 16-bit timers with capture and compare unit (T2CCU0 and T2CCU1) for digital signal generation

  • Watchdog timer (WDTSCR) with programmable window feature for refresh operation and warning prior to overflow

  • Full duplex serial interface (UART)

  • Synchronous serial channel (SSC)

  • Inter-integrated circuit interface (I2CSCR)

  • Wake-up CAN module (WCAN) to support Partial Networking (CAN ID filtering)

  • ADC compare functionality (ADCOMP) with 16 channels and 11-bit resolution

  • Local Interconnect Network (LIN) application support through extended UART features

  • Interrupt supported from SCR to the main SoC interrupt system and vice-verse

  • On-chip debug support through a single pin DAP interface (SPD)

  • Power saving features

    • Idle mode of the SCR core

    • Clock gating control for each peripheral

    • Switch between STANDBY0 and STANDBY1 system modes without wake-up of the TriCore™ domain

Note: TriCore™ domain P35 (SCR Ports P2.5 - P2.7 and P3.5 - P3.7) are only available in the packages with extensionr STD