• Interrupt system with support for up to 2048 service requests

  • Support for up to 256 service request priority levels per Interrupt Control Unit (ICU) and Interrupt Service Provider (ISP)

  • Support for up to 15 ICUs

  • A dedicated ICU for each implemented ISP. The ISPs are the functional blocks CPUs, DMAs, PPU, and the GTM

  • Low latency arbitration

    • Four fSPB clock cycles from interrupt trigger to service request signaling to ISP

    • Interrupt latency may increase for an ICU that operates in hardware virtualization mode

  • Each interrupt with a dedicated Service Request Node (SRN)

    • Each SRN with a programmable 8-bit Service Request Priority Number (SRPN)

    • Each SRN can be mapped to one of the implemented ISP

    • Each SRN can be mapped to exactly one virtual machine

    • SRNs are cleared by hardware on an interrupt acknowledge by the configured ISP if no EDC error is detected

  • Interrupt system with integrity support

    • The IR is implemented with a lockstep mechanism

    • End-to-end EDC protection of the interface between IR and the ISPs

  • Software Interrupts

    • One group of 8 General Purpose Service Requests (GPSR) per CPU and for the PPU

  • Ability to signal software interrupts simultaneously to multiple ISPs through service request broadcast registers (SRB)

  • Ability to transfer additional 16-bit information through software interrupt control register (

    GPSRG_SWC

    .DATA) to ISPs, protected by a hardware handshake

  • External interrupts with filter and trigger modes

    • External interrupt logic and related control registers are described in the System Control Unit (SCU) chapter, External Request Unit (ERU)

  • The IR provides wake-up support for the CPUs and the PPU that can cause the respective function block that is currently in idle or sleep to enter run mode