• According to PSI5 protocol specification

    v2.1

  • Flexible configuration and monitoring using software

    • Asynchronous/synchronous serial communication (ASC interface) with compatible PSI5-S physical-layer (PHY)

    • Baud rate generator up to 12,5 MBaud at 200 MHz ASC sub-module clock

    • Clock out generator to supply external PHY

    • Data rates of 125 kbit/s and 189 kbit/s supported

    • 8 PSI5-S channels sharing one common ASC interface (channel 0 frame 1 special use)

    • Asynchronous and Synchronous PSI5 data transmission modes

    • Supports 6 sensor slots per channel

    • 8 interrupts or direct memory access (DMA) triggers

  • Receive data processing using Message Recovery block:

    • 10-bit ASC format: 1 Start bit, 8 Data bits, 1 Stop bit (upstream)

    • Each PSI5 frame is transported in a packet frame consisting of 3 to 6 UART frames transmitted back to back with exactly one Stop bit. There is no additional delay

    • Packet frames are separated by a programmable idle time (with 1 to 16 idle bits)

    • Assembly and decoding of packet frames (envelope)

    • Routing of PSI5 frames to their referring channel receive buffer in system memory by hardware DMA support

    • Checking CRC of packet frames (XCRC)

    • Frames with XCRC error will be routed to channel 0 frame 1

    • The external PHY sends all frames of an asynchronous channel with frame ID (FID) = 1. All frames of this channel have the same length and structure as defined for FID 1. Therefore it is sufficient to configure frame 1 for asynchronous channels

    • Configurable data length from 8 to 28 bits and 3-bit PSI5 CRC or 1-bit PSI5 parity

    • CRC check of received PSI5 sensor data, CRC code still transparent

    • No hardware support of extended serial data messaging according to SENT SAE J2716 JAN 2010. Messaging bits are transported fully transparent for software decoding

    • 24-bit timestamp on sync pulse request through ASC (resolution: 1 µs)

    • Two independent time bases for timestamp: clocked by GTM or eGTM (1 out of n GTM or eGTM signals is selectable) or internal periodic trigger generator

    • PHY answers to CPU commands with standard frames of fixed predefined length in channel 0 frame 0

    • Error bits in packet frame are presented fully transparent and an interrupt is issued

    • One interrupt for error free packet frame. Relevant errors are selectable

    • One interrupt for packet frame reception disregarding any error

  • Transmit message data preparation using Message Generation block

    • Support of ECU to sensor communication

    • One 32-bit send data register per channel for downstream data input

    • Data is shifted out LSB first. MSB is filled with ‘0’ or ‘1’ with each shift, depending on the bit coding method: Tooth Gap or Pulse Width

    • 11-bit ASC format: 1 Start bit, 8 Data bits, 1 Parity, 1 Stop bit (downstream)

    • Downstream commands of fixed format (3 MSB = Channel ID. 5 LSB = Command)

    • All commands are randomly programmable and are therefore not interpreted by PSI5-S

    • Downstream data transmission by 2 different ASC commands (short/no, and long pulse)

    • 8 common lines of FIFO for all channels, writable by:

      • PSI5 message generation

      • Sync pulse generation. Pre-programmed bytes for 0 and 1

      • CPU commands:

        • CPU direct write registers (CDW) allow for insertion of commands into the FIFO for configuration and debugging

    • 8 GTM or eGTM inputs for sync pulse triggering

    • Software configurable staggering of sync pulse generation

    • Generation of 3 or 6-bit CRC for downstream data

    • Start sequence generator for downstream data. This can also be switched off

    • Bit stuffing generator for downstream data. This can also be switched off

    • CRC generator for downstream data. This can also be switched off

    • Internal Loop-Back mode for a check of the CRC generator and for software development