Feature list

General features

• Transmit ASC, LIN, and SPI frames to external devices and handle all protocol relevant topics

• Receive ASC, LIN, and SPI frames from external devices and handle all protocol relevant topics

• Data storage of

  16-bytes TxFIFO (Transmit first in first out) and 16-bytes RxFIFO (Receive first in first out)

• Pack and unpack capabilities of the TxFIFO and RxFIFO

• Interrupt generation:

  • On a configurable TxFIFO level

  • On a configurable RxFIFO level

  • On an error condition (frame, parity, overrun error)

  • On various internal events (end of ASC or SPI frame, or LIN events)

• Interrupt signals capable of triggering either a CPU or a DMA

• Flexible functional configuration for software:

  • Programmable oversampling of 4 to 16 times per bit

  • Programmable sampling point position

  • Programmable digital glitch filter and median filter for incoming bit stream

  • Shift direction LSB first for LIN mode and programmable LSB or MSB first for SPI and ASC mode

• Internal loop-back mode

Standard ASC features

• Full-duplex asynchronous operating mode:

  • 7-bit, 8-bit, or 9-bit (or up to 16-bit) data frames, LSB first

  • Parity-bit generation and checking

  • One or two stop bits

  • Maximum baud rate

    $\frac{{\mathrm{<p>f</p>}}_{\mathrm{<p>A</p>}}}{\mathrm{<p>16</p>}}$

    (6.25 MBaud at 100 MHz

    f

    A

    module clock)

  • Minimum baud rate

    $\frac{{\mathrm{<p>f</p>}}_{\mathrm{<p>A</p>}}}{\mathrm{<p>268</p>}\mathrm{<p>435</p>}\mathrm{<p>456</p>}}$

    (0.37 Baud at 100 MHz

    f

    A

    module clock)

• Frame transmit on hardware or software trigger

• Circular buffer

Extended ASC features

• Programmable oversampling of 4 to 16 times per bit:

  • Module capability of up to 4 times higher baud rates (

    $\frac{{\mathrm{<p>f</p>}}_{\mathrm{<p>A</p>}}}{\mathrm{<p>4</p>}}$

    ) than the standard ASC

  • System considerations such as pad type, incoming signal quality, and accumulated PLL jitter can lead to constraints regarding the usable oversampling ratios (for example

    $\frac{{\mathrm{<p>f</p>}}_{\mathrm{<p>A</p>}}}{\mathrm{<p>8</p>}}<p>=</p>\frac{\mathrm{<p>200</p>}<p></p>\mathrm{<p>MHz</p>}}{\mathrm{<p>8</p>}}<p>=</p>\mathrm{<p>25</p>}<p></p>\mathrm{<p>MBaud</p>}$

    )

• Optional RTS/CTS handshaking

LIN features

• Support of:

  • LIN version 1.3, 2.0, 2.1, and 2.2

  • J2602

• Break detection

• Break injection

• Sync field generation

• Auto baud detection based on Sync Field measurement

• Collision detection optionally (LIN2.1 mandatory)

• LIN Watchdogs:

  • Header time-out

  • Frame or Response time-out

• Stuck at zero or one monitoring

• Bus idle time monitoring

• Energy saving features (Wake-Up, Sleep)

• Minimum CPU load in master mode:

  • Single interrupt indicating the end of the frame

• Minimum CPU load in slave mode:

  • Single interrupt at the end of the header reception

  • Single interrupt at the end of the response or end of frame

• Standard operation with one interrupt per transmitted or received byte supported

SPI features

• SPI master modes (slave mode not supported):

  • Four-wire or three-wire (with or without slave select output signal)

• Up to 16-bit data width

• Full-duplex and half-duplex:

  • Maximum baud rate

    $\frac{{\mathrm{<p>f</p>}}_{\mathrm{<p>A</p>}}}{\mathrm{<p>4</p>}}<p></p>$

    (= 25 MBaud at 100 MHz

    f

    A

    module clock)

  • Minimum baud rate

    $\frac{{\mathrm{<p>f</p>}}_{\mathrm{<p>A</p>}}}{\mathrm{<p>268</p>}\mathrm{<p>435</p>}\mathrm{<p>456</p>}}<p></p>$

    (= 0.37 Baud at 100 MHz

    f

    A

    module clock)

• Programmable leading and trailing delays