Supported system modes​

  • RESET State: The device supports the following hierarchical reset states - Low Voltage Detector reset, Cold Power-On reset, Power Domain cold reset , Logical BIST reset, warm Power-On reset, System reset and Application reset

  • RUN0 Mode: The device is in operation after the de-assertion of all resets and Boot Firmware is executed. CPU0 and CPUcs are active in this phase. All switchable power domains in VDD core domain are active

  • RUN1 Mode: The device is in operation and user start-up software is executed. The switchable power domains which are not required are powered off

  • IDLE Modes: The IDLE Mode is available for every processing unit such as CPUs where the respective cores are put into idle state

  • SLEEP Modes: All CPUs are in Idle mode and only a few selected peripherals are active to realize wake-up functions. The SRI and SPB frequency can be reduced to reduce power consumption

  • STANDBYx Modes: Only PMS0 and/or PMS1 standby domains are active. All other modules and VDD Core domain is switched off

Supported reset types​

  • Low Voltage Detector triggered resets: These resets are triggered by PMS in case of power fails of the standby supply domains or indicated after an initial supply ramp-up

  • Power Domain Cold reset: This reset is triggered by PMS in the case of a VDD core voltage supply fail beyond which the power domain infrastructure and switch components need to be initialized

  • Cold Power-On reset: This reset is triggered by PMS in the case of a power fail of critical IO and core supply rails below the operating minimum voltage limits . All modules are in reset state except parts of PMS module

  • LBIST reset: This reset represents the device state when LBIST is active or being performed. After LBIST is completed or aborted, internal cold PORST is triggered. All modules are in reset state except PMS module

  • Warm Power-on reset: This reset is triggered when the external power-on reset pin (PORST) is asserted low. This reset is triggered predominantly by external regulators in case the microcontroller does not service external watchdogs within a defined time period. All modules are in reset state except PMS, SCR if configured, Standby RAMs, and SMM and RRAM

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    . RAMs of processing units maintain data content during and after reset

  • System reset: This reset is triggered by software, safety and security alarms, and watchdogs through the SMU unit, ESRx reset pins, system timers, test and debug modules. All modules are reset except PMS, SCR, SMM, RRAM

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    , Standby RAMs, and parts of SMU and debug system, based on configuration. RAMs of processing units maintain data content during and after reset

  • Application reset: This reset is triggered by software, safety and security alarms, and watchdogs through the SMU unit, ESRx reset pins, system timers and test and debug modules. All modules are reset except PMS, SCR, SMM, Standby RAMs, Clock, Flash

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    ,RRAM

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    , parts of SMU, SCU and the debug system based on configuration. RAMs of processing units maintain data content during and after reset. This reset ensures a fast overall microcontroller reset with minimal reset time

  • Module Group Resets: A predefined group of modules provide partitioning between multiple applications. These resets are triggered for such groups of modules which are bundled together to be reset together. The module reset behavior is the same as that after individual module resets

  • Module reset: The respective module is reset. Module reset is not available for CPU0, CPUcs, Flash, RRAM

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    , PMS, IR, SCU, SMM, and CCU. This reset is also used to specifically re-initialize the respective modules

External interfaces and features​

  • Bi-directional PORST pin: During cold resets, the PORST pin is asserted low internally therefore driving a reset output. The PORST pin is consequently de-asserted with additional voltage hysteresis once the supply is back in the operating region

  • The external request pins (ESR0, ESR1 and ESR2) support reset input trigger requests

  • The external request pins (ESR0 and ESR2) support reset output propagation with configurable delay to external driver and memory devices. This is to support open-drain star connected reset architectures and cascaded sequential reset architectures

  • The external request pins (ESR0, ESR1 and ESR2) support trap requests, NMI inputs, and wake-up requests, depending on configuration and system modes

  • Shut-down reset sequencing of modules after a reset request over a time period to ensure regulator friendly load transients

Start-up​

  • Coordination together with PMS of reset release and boot

  • The startup configuration (HWCFG Pins) is latched into status register in PMS

Load jump management​

  • Adaption of core voltage set points voltage levels for load jump handling

  • Shutdown sequencing for negative load jumps in case of reset events

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Not available on all devices of the

family