• Optimized for high-speed and high-performance

    • Support of multiple master agents and back-to-back transaction execution

    • Transaction pipelining support to support up to 1 data transmission per cycle

    • 32-bit address and 32-bit data width

    • 8, 16, and 32-bit data transfers

    • 64, 128, and 256-bit block transfers with wrap around addressing

  • Slave-controlled wait state and retry insertion

  • Timeout detection and handling

  • Support of atomic TriCore™ operations for example LDMST, ST.T, SWAP.W, CMPSWP, and SWPMSK

  • Flexible arbitration schemes

    • Priority based, two round-robin groups and starvation prevention mechanism

  • QoS master agent interconnect usage control mechanism

  • QoS application interconnect usage observation mechanism

  • Round-robin group control mechanism (round share mechanism)

  • Starvation prevention mechanism that can take care that even low priority requests will be granted after a configurable number of arbitration cycles, permanently enabled

  • Default slave mechanism that responds to a transactions to a not implemented addresses

  • Debug support where transaction information are captured in case of a FPI timeout or FPI error

  • Address phase includes master identifier, supervisor mode and security mode information

  • All slave agents implemented with master agent identifier based access protection

  • Transactions protected through end to end error detection code (EDC)