• Single (8-bit, 16-bit, 32-bit and 64-bit) and block read and write transactions (blocks up to 8 x 64-bit beats)

  • Atomic read write transaction sequence supported

  • Pipelined transactions from SRI masters to SRI slaves

    • Improved read write parallelism compared to previous generations

  • Arbiter for each SRI slave, with individual configuration

    • Two round-robin groups, high and low priority

    • Control of opportunity for the high priority group

  • EDC (Error Detection Code) on all address, data and control information transferred between SRI masters and SRI slaves

    • EDC on all data and control information transferred from an SRI master to an SRI slave for a write

    • EDC on all data and control information transferred from an SRI slave to an SRI master for a read

  • Device specific capability to monitor and record bandwidth utilization of resources for Quality of Service (QoS) purposes