Feature list

Power Management System

• Integrated on-chip voltage regulators enabling a 5 V ± 10% or 3.3 V ± 10% single source power supply concept. External supply on all rails also supported

• Core buck regulator (EVRC) to generate

  V

  DD

  core supply from

  V

  DDEXTDC

  input supply up to 7 V (depending upon product variant) to enable MOSFET supply from external pre-regulator. Synchronization support with external DCDC regulators

• Static voltage scaling support between 0.95 V – 1.025 V ± 10%, depending on product variant, in steps of 2.83 mV (using the embedded voltage regulator EVRC), depending on product variant and device type

• Primary under-voltage monitoring of supply rails including

  V

  DD

  ,

  V

  DDEXT

  ,

  V

  DDEXTHS

  ,(

  V

  DDEXTDC

  V

  SSDCHS

  ),

  V

  DDEXTDC

  ,

  V

  DDDCLS

  ,

  V

  DDEVRSB

  ,

  V

  DD3PMS

  ,

  V

  DDP3NVM

  ,

  V

  DDM

  ,

  V

  DDPHPHYx

  ,

  V

  DDPHRIFx

  ,

  V

  DDHSIF

  ,

  V

  DDPAD

  ,

  V

  DDCPUx

  ,

  V

  DDPPU

  ,

  V

  DDLMUx

  ,

  V

  DDPHYx

  , and

  V

  DDRIFx

  , depending on product variant (not all supply rails are available on each product variant), irrespective of whether externally supplied or internally generated, to put the microcontroller into cold reset state

• Secondary independent over and under-voltage monitoring on

  V

  DDEVRSB

  ,

  V

  DD3PMS

  ,

  V

  DDEXT

  ,

  V

  DDEXTHS

  ,

  V

  DDP3NVM

  ,

  V

  DDM

  ,

  V

  DDFLEX

  ,

  V

  DD

  ,

  V

  DDPMS0

  ,

  V

  DDPMS1

  ,

  V

  DDPMS2

  ,

  V

  DDSBRAM

  ,

  V

  DDPAD

  ,

  V

  DDPHPHYx

  ,

  V

  DDPHRIFx

  ,

  V

  DDHSIF

  ,

  V

  DDPHYx

  ,

  V

  DDRIFx

  ,

  V

  DDCPUx

  ,

  V

  DDPPU

  ,

  V

  DDLMUx

  , and

  V

  DDEXTDC

  supplies, depending on product variant (not all supply rails are available on each product variant). In case of violation of the thresholds, alarms are reported to the SMU (safety and security alarm management unit) and CSRM (cyber security real-time module)

• Support of multiple standby power domains PMS0, PMS1, and PMS2 supplied by separate standby supply pin (

  V

  DDEVRSB

  ) and internal standby core regulators to meet low quiescent standby current targets. Wake-up possible from RTC, WUT, pin events, and

  V

  DDEXT

  supply ramp events

• 256 kB standby RAM support split across CPU0 dLMU and CPU1 dLMU and 32 kB SCR XRAM supplied in standby mode

  , depending on product variant

• Real Time Clock and timer support with external 32 kHz crystal with temperature trimming

  , depending on product variant

• Enhanced standby controller subsystem running up to maximum frequency of 100 MHz and with 32 kB XRAM

  , depending on product variant

Power distribution

• Support of multiple core power domains for CPU, PPU, and LMU functional blocks (depending on product variant) to reduce overall power consumption for use cases where the modules are not required

• Separate ADC power domain supplied by

  V

  DDM

  /

  V

  SSM

  supply rails to ensure minimum noise interference from the digital core and pad domains. Separate

  V

  DDM

  /

  V

  AREF

  reference supply for ADC modules

• Mixed IO support

  • Flexport (

    V

    DDFLEX

    ) has separate dedicated supply pins and may be supplied with either 5 V or 3.3 V

  • ADC channels supported in dedicated analog and shared digital port (P00/P33) domains

• XTAL/Oscillator/PLL supply with separate supply and ground pins for minimal noise interference

• Separate port domain for standby controller and standby functions supplied by

  V

  DDEVRSB

  supply rail

• Separate port power domains for high speed communication interfaces

  • SGMIIx and PCIe modules supplied by dedicated

    V

    DDPHPHYx

    and

    V

    DDPHYx

    supply rails

  • NOR Flash interface or ethernet RGMII supplied by dedicated

    V

    DDHSIF

    supply rail

  • Ethernet RMII/MII supplied by dedicated

    V

    DDFLEX

    supply rail