AN224413  How to use I2S in TRAVEO™ T2G family

About this document

Scope and purpose

This application note explains how to configure and use I ² S in TRAVEO™ T2G family MCU. The application note also explains the necessary settings for I ² S such as port, clock, and interrupt. The document uses TLV320AIC26 (Audio Codec) as an example to explain the functions of I ² S.

Intended audience

This document is intended for anyone who uses Infineon TRAVEO™ T2G MCUs for configuring I ² S.

Associated part family

TRAVEO™ T2G family CYT3B series

TRAVEO™ T2G family CYT4B series

TRAVEO™ T2G family CYT6B series

TRAVEO™ T2G family CYT2C series

TRAVEO™ T2G family CYT3D series

TRAVEO™ T2G family CYT4D series

TRAVEO™ T2G family CYT4E series

Introduction

The Inter-IC Sound Bus (I ² S) is a serial bus interface standard used to connect digital audio devices together. The specification is from Philips Semiconductor (I ² S bus specification: February 1986, revised June 5, 1996). In addition to the standard I ² S format, the I ² S block also supports the Left Justified (LJ) format and the Time Division Multiplexed (TDM) format.

This application note describes how to use I ² S for TRAVEO™ T2G family CYT4B series MCUs. The application note uses TLV320AIC26 as an example to connect with I ² S interface to record and play with headphones.

To understand the functionality described and terminology used in this application note, see the “Audio Subsystem” chapter in the architecture reference manual .

I²S structure

Figure 1 , Figure 2 , and Figure 3 show the structure of I ² S and three use cases of external and internal clock.

The I ² S block configuration, control, and status registers, along with the FIFO data buffers are accessible through the AHB bus. AHB bus masters such as CPU and DMA can access the I ² S registers through the AHB interface. See the device datasheet for information on port pin assignments of the I ² S block signals and AC-DC electrical specifications.

Figure 1.

I ² S block diagram for internal clock

Figure 2.

I ² S block diagram for external clock

Figure 3.

I ² S block diagram for MCLK output

Figure 1 , Figure 2 , and Figure 3 show the block diagrams of the I ² S block of the TRAVEO™ T2G MCU, which consist of two sub-blocks-I ² S Transmitter (TX) and I ² S Receiver (RX). The digital audio interface format and master/slave mode configuration can be done independently for the TX and RX blocks. In the master mode, the word select (WS) and serial data clock (SCK) are generated by the I ² S block in TRAVEO™ T2G. In the slave mode, the WS and SCK signals are input signals to the I ² S block and generated by the external master device.

Internal clock and external clock

Figure 1 shows the basic use case for I ² S internal clock. In this case, the external device uses Audio_I2S_MCLK as clock and the I ² S block uses HF_CLK [5] as clock. The external device and the I ² S block are not synchronized because they use different clocks; therefore, it may cause the FIFO to underflow or overflow. Figure 2 shows external clock connections respectively. In this case, clock is the synchronization of the clock. Thus, there are no underflow or overflow due to the clock being out of sync.

The following are the settings required for internal clock:

• CTL.TX_ENABLE and RX_ENABLE = 1 (I ² S is enabled)

• CLOCK_CTL.CLOCK_SEL = 0 (I ² S clock is from internal clock: CLK_HF [5])

• CLOCK_CTL.CLOCK_DIV = 0, 1, 2… 63 (Division ratio: 1, 2, 3…64)

The following are the settings required for external clock:

• CTL.TX_ENABLE and RX_ENABLE = 1 (I ² S is enabled)

• CLOCK_CTL.CLOCK_SEL = 1 (I ² S clock is from external clock: AUDIO_CLK_I2S_IF)

• CLOCK_CTL.CLOCK_DIV = 0, 1, 2… 63 (Division ratio: 1, 2, 3…64)

To understand the functionality described and terminology used in this application note, see the “Audio Subsystem” chapter in the architecture reference manual .

MCLK output function

This section explains the third use case (see Figure 3 ), where the I ² S unit generates MCLK output signal for the external audio DAC.

In Figure 3 , AUDIOSS2_MCLK is used as the output for the external audio DAC. In this use case, the MCLK output pin is active before I ² S audio started (PLL start-up time of external IC).

MCLK output signal is generated only if the following conditions are met:

CTL.TX_ENABLE and CTL.RX_ENABLE = 1 (I ² S is enabled)

• CLOCK_CTL.CLOCK_SEL = 0 (I ² S clock is from internal clock: CLK_HF [5])

• CLOCK_CTL.MCLK_DIV = 0, 1, 2 or 3 (Division ratio: 1, 2, 4, or 8)

• CLOCK_CTL.MCLK_EN = 1 (MCLK output enabled)

Figure 4 shows the MCLK output function.

Figure 4.

MCLK output function

For more information on interface formations, see the “Audio Subsystem” chapter of the architecture reference manual .

Digital audio interface format

The I ² S block supports the following digital audio interface formats:

• Standard I ² S

• LJ

• TDM

For more information on interface formats, see the “Audio Subsystem” chapter of the architecture reference manual .

Operation overview

The external device TLV320AIC26 is used as an example to show the functions of the I ² S block of TRAVEO™ T2G. The features of TLV320AIC26 of interest include Stereo Audio DAC and Mono Audio ADC. For more information, see TLV320AIC26 datasheet .

The TLV320AIC26 device converts the analog signal (for example, signal from a microphone) to the digital form and transmits it to the TRAVEO™ T2G MCU. TRAVEO™ T2G transmits the digital signals again to TLV320AIC26 which will do digital to analog conversion, and the analog signal can be played by a speaker. Thus, you can hear your voice from the headset while speaking over a microphone.

Figure 5 shows this example where the external device Audio Codec TLV320AIC26 converts the analog data from MICIN to RX_FIFO through DOUT. Then, I ² S writes the data to TX_FIFO and transmits it to TLV320AIC26 through DIN. TLV320AIC26 uses a DAC to convert this digital data. Then, TLV320AIC26 outputs the analog data via HPR/HPL.

I ² S block uses a standard I ² S format. When TX is set in master mode, TX outputs WS, and SCK signals. When RX is set to slave mode, RX uses WS and SCK signals from TX. Sampling rate of I ² S data transfer is set as 48 kHz. The clock is an internal clock derived from CLK_HF[5]. Word length and channel length of data transfer are 16 bits.

Figure 5.

Example of use case

Control of the TLV320AIC26 and its functions is accomplished by writing to its registers. A simple command protocol is used to address the 16-bit registers. Registers control the operation of the AD converter and Audio Codec. The control functions are accessed via a SPI Interface (in this example, it uses SCB5_SPI).

SCB5_SPI is used only to configure (write to its registers) the external device Audio Codec. The external Audio Codec device and I2S device use their own internal clocks AUDIO_I2S_MCLK and CLK_HF[5], respectively. AUDIO_I2S_MCLK is generated from an external oscillator.

Figure 6 shows an example of an external crystal oscillator.

Figure 6.

Example for external crystal oscillator

For more information about TLV320AIC26 and ASE series crystal oscillator, see TLV320AIC26 datasheet and ASE Series datasheet .

The signals of I²S block

This section explains the direction of signals.

In Figure 7 , the TRAVEO™ T2G I ² S TX block acts as the master and the codec, and the TRAVEO™ T2G I ² S RX block act as slaves. Since the I ² S TX block is the master, AUDIOSS_TX_SCK, AUDIOSS_TX_WS, AUDIOSS_RX_SCK, and AUDIOSS_RX_WS use the same clock.

Figure 7.

Connections for codecs with common WS and SCK signals for RX and TX

Setting procedure

Figure 8 provides the necessary settings for HF clock setting, port setting, interrupt setting, I ² S setting, SPI setting, and audio codec setting and illustrates the procedure to write data for uses case. In this case, if an unintended interrupt occurs, the status is set to false. If a false status occurs, the software can perform appropriate error handling.

Figure 8.

Write DATA to TX_FIFO

HF_Clock setting

This section explains the clock settings that can be used.

TRAVEO™ T2G family has several high-frequency root clocks (CLK_HF). Each CLK_HF has a destination on the device. In this use case, the I ² S block uses CLK_HF [5] that is set to 24.576 MHz, for generating the 48 kHz sampling rate (details in Section 3.5 Configure for I ² S ).

The following are the settings and steps required for HF_Clock setting:

• HF_CLK5 for I ² S

  (HF_CLK5 = 24.576 MHz)

• HF_CLK2 for SCB5_SPI1.

  1. Enable each HF_CLK2

  2. Clock divider setting for SCB5_SPI

     • Assigns a programmable divider to a selected IP block

     • Sets the frequency and divider number (make sure that the frequency is defined)

     • Enables the selected divider

For more details on clocks, see the “Clock Subsystem” chapter of the architecture reference manual .

Port setting

Follow this procedure to configure SPI and I ² S port setting, using SCB5_SPI to address registers of TLV320AIC26:

• Configure SPI interface port

  • SCB5_SPI_MISO

  • SCB5_SPI_MOSI

  • SCB5_SPI_CLK

  • SCB5_SPI_SELECT1

• Configure I ² S TX interface port

  • AUDIOSS0_TX_SCK

  • AUDIOSS0_TX_WS

  • AUDIOSS0_TX_SDO

• Configure I ² S RX interface port

  • AUDIOSS0_RX_SCK

  • AUDIOSS0_RX_WS

  • AUDIOSS0_RX_SDI

To set driver mode, interrupt mask, and edge detect as port settings, see the “IO Subsystem” chapter of the architecture reference manual .

Interrupt setting

The following are the interrupts that need to be set:

• SCB5_SPI interrupt

• I ² S interrupt

See the interrupts chapter of the architecture reference manual for details on the vector number of the I ² S interrupt and the procedure to configure the interrupt priority, vector address, and enabling/disabling interrupts.

Configure for SPI

External device TLV320AIC26 communicates with MCU over SCB5_SPI interface and MCU acts as a SPI bus master.

All TLV320AIC26 control registers are programmed through a standard SCB5_SPI and the bitrate is set to 125000 Hz.

To set SCB5_SPI, see the “Serial Communications Interface” chapter of the architecture reference manual to set SCB5_SPI.

Configure for I²S

The I ² S block can support Standard I ² S format, LJ format, and TDM format. In this use case, the I ² S uses Standard I ² S format. Also, the number of data bytes transmitted and received over I ² S is 96 in each iteration.

Figure 9 shows how to configure I ² S.

Figure 9.

Example of configuration for I ² S

• CLOCK_CTL.CLOCK_DIV = 1

  This clock divider is used to generate the internal I ² S master clock (MCLK_SOC).

  I ² S device uses HF_CLK [5], which is 24.576 MHz and has a sampling rate set as 48 kHz.

  The formula is:

  $\frac{\mathrm{I}\mathrm{n}\mathrm{p}\mathrm{u}\mathrm{t}\mathrm{ }\mathrm{C}\mathrm{l}\mathrm{o}\mathrm{c}\mathrm{k}}{8\times CLOC{K}_{DIV}\times Bitsize}=Sampling\mathrm{ }Rate$

  Where,

  8 is the second stage divider and is a constant.

  By substituting values:

  $\frac{24.576\mathrm{M}\mathrm{H}\mathrm{z}}{8\times CLOC{K}_{DIV}\times 32}=48 kHz$

  Thus, the value of CLOCK _DIV as derived as 2.

  For more details, see the “Clock System” chapter of the architecture reference manual .

• TX_CTL.SCKO_POL = false

  TX_CTL.SCKO_POL indicates the TX master bit clock polarity for transmitter control.

  • ‘false’: When transmitter is in master mode, serial data is transmitted from the falling bit clock edge

  • ‘true’: When transmitter is in master mode, serial data is transmitted from the rising bit clock edge

• TX_CTL.SCKI_POL = false

  TX_CTL.SCKI_POL indicates the TX slave bit clock polarity for transmitter control.

  • ‘false’: When transmitter is in slave mode, serial data is transmitted off the falling bit clock edge (according to the I ² S Standard)

  • ‘true’: When transmitter is in slave mode, serial data is transmitted off the rising bit clock edge.

• RX_CTL.SCKO_POL = false

  RX_CTL.SCKO_POL indicates the RX SCKO polarity for Receiver Control.

  • ‘false’: When receiver is in master mode, serial data is captured by the rising bit clock edge (accordingly to the I ² S Standard).

  • ‘true’: When receiver is in master mode, serial data is captured by the falling bit clock edge.

• RX_CTL.SCKI_POL = false

  RX_CTL.SCKI_POL indicates the RX slave bit clock polarity for Receiver Control.

  • ‘false’: When receiver is in slave mode, serial data is sampled on the rising bit clock edge.

  • ‘true’: When receiver is in slave mode, serial data is sampled on the falling bit clock edge.

• TRIGGER_LEVEL = 96

  TRIGGER_LEVEL is a set value of trigger event condition.

• TX_FIFO_TRIGGER_LEVEL＝96

  When the trigger level is between 1 and 96, the number of data are stacked on TX FIFO, and an event trigger will be generated.

• RX_FIFO_CTL.TRIGGER_LEVEL＝96

  When the trigger level is equal to or greater than 96, the number of data are stacked on RX FIFO, and an event trigger will be generated.

For more information on interface formats, see the “Audio Subsystem” chapter of the architecture reference manual .

Audio codec setting

This section explains how to configure the audio codec.

Figure 10 shows an example for how to configure ADC and DAC in the audio codec.

Figure 10. Example of setting for ADC and DAC in the audio codec

For more information on Audio Codec settings, see the References .

PLL setting

The reference sampling rate (Fsref) is necessary for the PLL and it must be set between 39 kHz and 53 kHz. Fsref can be set by the REG-06H/Page2 control register. For more information on sampling rate, see the TLV320AIC26 datasheet . Use the following formula to calculate the values of P, K, J, and D, when PLL is enabled.

$\mathrm{ }\mathrm{F}\mathrm{s}\mathrm{r}\mathrm{e}\mathrm{f}=\mathrm{ }\frac{MCLK\times K}{2048\times P}$

Fsref= MCLK×K2048×P

Where,

P = 1, 2, 3 …,8

K = J.D

J = 1, 2, 3, …,64

D = 0, 1, 2, …,9999

P, J, and D are set by registers. J is the integer part of K before the decimal point. D is a four-digit fractional part of K after the decimal point, including lagging zeros. P, J, and D are necessary values for the PLL.

In Figure 10 , MCLK is 12 MHz. Fsref is set as 48 kHz and PLL is enabled. Therefore, the values are set as follows:

$\mathrm{F}\mathrm{s}\mathrm{r}\mathrm{e}\mathrm{f}=\mathrm{ }\frac{MCLK\times K}{2048\times P}=\mathrm{ }\frac{12000000\times J.D}{2048\times P}\mathrm{ }=\mathrm{ }48000 Hz$

Where,

P = 1

J = 8

D = 1920

K = 8.192

You can confirm the validity of the values of P, J, and D from the following:

When PLL is enabled and D ≠0, the following condition of P must be satisfied:

$10\mathrm{ }\mathrm{M}\mathrm{H}\mathrm{z}\le \frac{MCLK}{P}\le 20\mathrm{ }MHz$

After adding values to the formula, the condition should be:

$10\mathrm{ }\mathrm{M}\mathrm{H}\mathrm{z}\le \frac{12MHz}{1}\le 20\mathrm{ }MHz$

Thus, P = 1 satisfies the condition.

The following is the condition to set K (= J.D):

$\mathrm{ }80\mathrm{ }\mathrm{M}\mathrm{H}\mathrm{z}\le \frac{MCLK\times K}{P}\le 110\mathrm{ }MHz$

After adding values to the formula, the condition should be:

$80\mathrm{ }\mathrm{M}\mathrm{H}\mathrm{z}\le \frac{12MHz\times 8.192}{1}\le 110\mathrm{ }MHz$

Thus, J = 8 and D = 192 satisfy the condition.

Interrupt routine

Figure 8 shows the interrupt routine for I ² S.

Use the following register to check whether the interrupt has occurred:

• Register: INTR_MASKED.RX_TRIGGER

This is Interrupt masked register. A register value of 1 means Rx trigger interrupt has occurred.

• Register: INTR_MASKED.TX_TRIGGER

This is Interrupt masked register. A register value of 1 means Tx trigger interrupt has occurred.

In this use case, I ² S gets the data from RX_FIFO when INTR_MASKED.RX_TRIGGER equals to 1.

I ² S writes data to TX_FIFO when INTR_MASKED.TX_TRIGGER equals to 1 and status shows successful.

Status shows false when unexpected interrupt occurred.

Then, clear the interrupt flag and wait for the next interrupt to occur.

Glossary

Terms	Description
BCLK	Audio bit-clock
DIN	Audio data input
DOUT	Audio data output
HPL	Left channel audio output
HPR	Right channel audio output
LRCK	Audio DAC word-clock
MCLK	Master clock
MICBIAS	Microphone bias voltage
MICIN	Microphone input
MISO	SPI serial data output (Master in slave out)
MOSI	SPI serial data input (Master out slave in)
RX FIFO	FIFO for receiver
RX_SCK	I 2 S serial clock for receiver
RX_SDI	I 2 S serial data input for receiver
RX_WS	I 2 S word select for receiver
SCLK	SPI serial clock input
SS	SPI slave select input
TX FIFO	FIFO for transmitter
TX_SCK	I 2 S serial clock for transmitter
TX_SDO	I 2 S serial data output for transmitter
TX_WS	I 2 S word select for transmitter
VGND	Virtual ground for audio output

References

The following are the TRAVEO™ T2G Family Series datasheets and technical reference manuals:

1. Device datasheet

   • CYT3BB/4BB datasheet 32-bit Arm® Cortex®-M7 microcontroller TRAVEO™ T2G family
   • CYT4BF datasheet 32-bit Arm® Cortex®-M7 microcontroller TRAVEO™ T2G family

   • CYT6BJ datasheet 32-bit Arm® Cortex®-M7 microcontroller TRAVEO™ T2G family (Doc No. 002-33466)

   • CYT3DL datasheet 32-bit Arm® Cortex®-M7 microcontroller TRAVEO™ T2G family
   • CYT4DN datasheet 32-bit Arm® Cortex®-M7 microcontroller TRAVEO™ T2G family

   • CYT4EN datasheet 32-bit Arm® Cortex®-M7 microcontroller TRAVEO™ T2G family (Doc No. 002-30842)

   • CYT2CL datasheet 32-bit Arm® Cortex®-M4F microcontroller TRAVEO™ T2G family
2. Body controller high family

   • TRAVEO™ T2G automotive body controller high family architecture reference manual

   • TRAVEO™ T2G automotive body controller high registers reference manual for CYT3BB/4BB
   • TRAVEO™ T2G automotive body controller high registers reference manual for CYT4BF

   • TRAVEO™ T2G automotive body controller high registers reference manual for CYT6BJ (Doc No. 002-36068)

3. Cluster Entry family

   • TRAVEO™ T2G automotive cluster entry architecture reference manual

   • TRAVEO™ T2G automotive cluster entry registers reference manual for CYT2CL

4. Cluster 2D family

   • TRAVEO™ T2G automotive cluster 2D architecture reference manual

   • TRAVEO™ T2G automotive cluster 2D registers reference manual for CYT3DL

   • TRAVEO™ T2G automotive cluster 2D registers reference manual for CYT4DN

   • TRAVEO™ T2G automotive cluster 2D registers reference manual for CYT4EN (Doc No. 002-35181)

5. Sample software

   • Contact Technical Support

The following is the TLV320AIC26 datasheet:

1. TLV320AIC26: Low power stereo audio CODEC w/headphone/speaker amp and 12-Bit battery/temperature/auxiliary ADC

The following is the ASE Series datasheet:

1. ASE-12MHz-LC-T: Crystal Oscillator datasheet

Revision history

Document revision	Date	Description of changes
**	2019-06-04	New application note.
*A	2021-05-17	Updated to Infineon template.
*B	2023-11-10	Template update; no content update.
*C	2025-01-22	Updated and fixed related to CYT6BJ