XMC4100/XMC4200

XMC4000 Family

Microcontroller Series for Industrial Applications

ARM® Cortex®-M4

32-bit processor core

Datasheet

About this Document

This datasheet is addressed to embedded hardware and software developers. It provides the reader with detailed descriptions about the ordering designations, available features, electrical and physical characteristics of the XMC4[12]00 series devices.

The document describes the characteristics of a superset of the XMC4[12]00 series devices. For simplicity, the various device types are referred to by the collective term XMC4[12]00 throughout this manual.

XMC4000 Family User Documentation

The set of user documentation includes:

• Reference Manual

  • describes the functionality of the superset of devices.

• Datasheets

  • list the complete ordering designations, available features and electrical characteristics of derivative devices.

• Errata Sheets

  • list deviations from the specifications given in the related Reference Manual or Datasheets. Errata Sheets are provided for the superset of devices.

Attention:

Please consult all parts of the documentation set to attain consolidated knowledge about your device.

Application related guidance is provided by

Users Guides

and

Application Notes

.

Please refer to

http://www.infineon.com/xmc4000

to get access to the latest versions of those documents.

Summary of Features

The XMC4[12]00 devices are members of the XMC4000 Family of microcontrollers based on the ARM Cortex-M4 processor core. The XMC4000 is a family of high performance and energy efficient microcontrollers optimized for Industrial Connectivity, Industrial Control, Power Conversion, Sense & Control.

Figure 1. System Block Diagram

CPU Subsystem

• CPU Core

  • High Performance 32-bit ARM Cortex-M4 CPU

  • 16-bit and 32-bit Thumb2 instruction set

  • DSP/MAC instructions

  • System timer (SysTick) for Operating System support

• Floating Point Unit

• Memory Protection Unit

• Nested Vectored Interrupt Controller

• One General Purpose DMA with up-to 8 channels

• Event Request Unit (ERU) for programmable processing of external and internal service requests

• Flexible CRC Engine (FCE) for multiple bit error detection

On-Chip Memories

• 16 KB on-chip boot ROM

• up to 16 KB on-chip high-speed program memory

• up to 24 KB on-chip high speed data memory

• up to 256 KB on-chip Flash Memory with 1 KB instruction cache

Communication Peripherals

• Universal Serial Bus, USB 2.0 device, with integrated PHY

• Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with two nodes, 64 message objects (MO), data rate up to 1 MBit/s

• Four Universal Serial Interface Channels (USIC), providing four serial channels, usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces

• LED and Touch-Sense Controller (LEDTS) for Human-Machine interface

Analog Frontend Peripherals

• Two Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with input out-of-range comparators

• Digital-Analog Converter (DAC) with two channels of 12-bit resolution

Industrial Control Peripherals

• Two Capture/Compare Units 4 (CCU4) for use as general purpose timers

• One Capture/Compare Units 8 (CCU8) for motor control and power conversion

• Four High Resolution PWM (HRPWM) channels

• One Position Interface (POSIF) for servo motor positioning

• Window Watchdog Timer (WDT) for safety sensitive applications

• Die Temperature Sensor (DTS)

• Real Time Clock module with alarm support

• System Control Unit (SCU) for system configuration and control

Input/Output Lines

• Programmable port driver control module (PORTS)

• Individual bit addressability

• Tri-stated in input mode

• Push/pull or open drain output mode

• Boundary scan test support over JTAG interface

On-Chip Debug Support

• Full support for debug features: 8 breakpoints, CoreSight, trace

• Various interfaces: ARM-JTAG, SWD, single wire trace

Ordering Information

The ordering code for an Infineon microcontroller provides an exact reference to a specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies:

• <DDD> the derivatives function set

• <Z> the package variant

  • E: LFBGA

  • F: LQFP, TQFP

  • Q: VQFN

• <PPP> package pin count

• <T> the temperature range:

  • F: -40°C to 85°C

  • K: -40°C to 125°C

• <FFFF> the Flash memory size.

For ordering codes for the XMC4[12]00 please contact your sales representative or local distributor.

This document describes several derivatives of the XMC4100 and XMC4200 series, some descriptions may not apply to a specific product. Please see

Table 1

.

For simplicity the term

XMC4[12]00

is used for all derivatives throughout this document.

Device Types

These device types are available and can be ordered through Infineon’s direct and/or distribution channels.

Table 1. Synopsis of XMC4[12]00 Device Types

Derivative 1	Package	Flash Kbytes	SRAM Kbytes
XMC4200-F64x256	PG-yQFP-64	256	40
XMC4200-Q48x256	PG-VQFN-48	256	40
XMC4100-F64x128	PG-yQFP-64 2	128	20
XMC4100-Q48x128	PG-VQFN-48	128	20
XMC4104-F64x64	PG-yQFP-64 2	64	20
XMC4104-Q48x64	PG-VQFN-48	64	20
XMC4104-F64x128	PG-yQFP-64 2	128	20
XMC4104-Q48x128	PG-VQFN-48	128	20
XMC4108-F64x64	PG-yQFP-64 2	64	20
XMC4108-Q48x64	PG-VQFN-48	64	20

Package Variants

Different markings of the XMC4[12]00 use different package variants. Details of those packages are given in the Package Parameters section of the datasheet.

Table 2. XMC4[12]00 Package Variants

Package Variant	Marking	Package
XMC4[12]00-F64	EES-AA, ES-AA, ES-AB, AB	PG-LQFP-64-19
XMC4[12]00-Q48		PG-VQFN-48-53
XMC4[12]00-F64	BA	PG-TQFP-64-19
XMC4[12]00-Q48		PG-VQFN-48-71

Device Type Features

The following table lists the available features per device type.

Table 3. Features of XMC4[12]00 Device Types

Derivative 3	LEDTS Intf.	USB Intf.	USIC Chan.	MultiCAN Nodes, MO
XMC4200-F64x256	1	1	2 x 2	N0, N1 MO[0..63]
XMC4200-Q48x256	1	1	2 x 2	N0, N1 MO[0..63]
XMC4100-F64x128	1	1	2 x 2	N0, N1 MO[0..63]
XMC4100-Q48x128	1	1	2 x 2	N0, N1 MO[0..63]
XMC4104-F64x64	1	–	2 x 2	–
XMC4104-Q48x64	1	-	2 x 2	–
XMC4104-F64x128	1	–	2 x 2	–
XMC4104-Q48x128	1	–	2 x 2	–
XMC4108-F64x64	–	–	2 x 2	N0, MO[0..31]
XMC4108-Q48x64	–	–	2 x 2	N0, MO[0..31]

Table 4. Features of XMC4[12]00 Device Types

Derivative 4	ADC Chan.	DAC Chan.	CCU4 Slice	CCU8 Slice	POSIF Intf.	HRPWM Intf.
XMC4200-F64x256	10	2	2 x 4	1 x 4	1	1
XMC4200-Q48x256	9	2	2 x 4	1 x 4	1	1
XMC4100-F64x128	10	2	2 x 4	1 x 4	1	1
XMC4100-Q48x128	9	2	2 x 4	1 x 4	1	1
XMC4104-F64x64	10	2	2 x 4	1 x 4	1	1
XMC4104-Q48x64	9	2	2 x 4	1 x 4	1	1
XMC4104-F64x128	10	2	2 x 4	1 x 4	1	1
XMC4104-Q48x128	9	2	2 x 4	1 x 4	1	1
XMC4108-F64x64	10	2	2 x 4	1 x 4	1	–
XMC4108-Q48x64	9	2	2 x 4	1 x 4	1	–

Definition of Feature Variants

The XMC4[12]00 types are offered with several memory sizes and number of available VADC channels. Table 5 describes the location of the available Flash memory, Table 6 describes the location of the available SRAMs, Table 7 the available VADC channels.

Table 5. Flash Memory Ranges

Total Flash Size	Cached Range	Uncached Range
256 Kbytes	0800 0000 – 0803 FFFF	0C00 0000 – 0C03 FFFF
128 Kbytes	0800 0000 – 0801 FFFF	0C00 0000 – 0C01 FFFF
64 Kbytes	0800 0000 – 0800 FFFF	0C00 0000 – 0C00 FFFF

Table 6. SRAM Memory Ranges

Total SRAM Size	Program SRAM	System Data SRAM
40 Kbytes	1FFF C000 – 1FFF FFFF	2000 0000 – 2000 5FFF
20 Kbytes	1FFF E000 – 1FFF FFFF	2000 0000 – 2000 2FFF

Table 7. ADC Channels ⁵

Package	VADC G0	VADC G1
LQFP-64, TQFP-64	CH0, CH3..CH7	CH0, CH1, CH3, CH6
PG-VQFN-48	CH0, CH3..CH7	CH0, CH1, CH3

Identification Registers

The identification registers allow software to identify the marking.

Table 8. XMC4200 Identification Registers

Register Name	Value	Marking
SCU_IDCHIP	0004 2001	EES-AA, ES-AA
SCU_IDCHIP	0004 2002	ES-AB, AB
SCU_IDCHIP	0004 2003	BA
JTAG IDCODE	101D D083	EES-AA, ES-AA
JTAG IDCODE	201D D083	ES-AB, AB
JTAG IDCODE	301D D083	BA

Table 9. XMC4100 Identification Registers

Register Name	Value	Marking
SCU_IDCHIP	0004 2001	EES-AA, ES-AA
SCU_IDCHIP	0004 2002	ES-AB, AB
SCU_IDCHIP	0004 1003	BA
JTAG IDCODE	101D D083	EES-AA, ES-AA
JTAG IDCODE	201D D083	ES-AB, AB
JTAG IDCODE	301D D083	BA

General Device Information

This section summarizes the logic symbols and package pin configurations with a detailed list of the functional I/O mapping.

Logic Symbols

Figure 2. XMC4[12]00 Logic Symbol PG-LQFP-64 and PG-TQFP-64

Figure 3. XMC4[12]00 Logic Symbol PG-VQFN-48

Pin Configuration and Definition

The following figures summarize all pins, showing their locations on the different packages.

Figure 4. XMC4[12]00 PG-LQFP-64 and PG-TQFP-64 Pin Configuration (top view)

Figure 5. XMC4[12]00 PG-VQFN-48 Pin Configuration (top view)

Package Pin Summary

The following general scheme is used to describe each pin:

Table 10. Package Pin Mapping Description

Function	Package A	Package B	...	Pad Type	Notes
Name	N	Ax	...	A1+

The table is sorted by the “Function” column, starting with the regular Port pins (Px.y), followed by the dedicated pins (i.e.

$\overline{PORST}$) and supply pins.

The following columns, titled with the supported package variants, lists the package pin number to which the respective function is mapped in that package.

The “Pad Type” indicates the employed pad type (A1, A1+, special=special pad, In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about the pad properties are defined in the Electrical Parameters.

In the “Notes”, special information to the respective pin/function is given, i.e. deviations from the default configuration after reset. Per default the regular Port pins are configured as direct input with no internal pull device active.

Table 11. Package Pin Mapping

Function	LQFP-64 TQFP-64	VQFN-48	Pad Type	Notes
P0.0	2	2	A1+
P0.1	1	1	A1+
P0.2	64	48	A1+
P0.3	63	47	A1+
P0.4	62	46	A1+
P0.5	61	45	A1+
P0.6	60	44	A1+
P0.7	58	43	A1+	After a system reset, via HWSEL this pin selects the DB.TDI function.
P0.8	57	42	A1+	After a system reset, via HWSEL this pin selects the $\overline{DB\mathrm{.}TRST}$ function, with a weak pull-down active.
P0.9	4	–	A1+
P0.10	3	–	A1+
P0.11	59	–	A1+
P1.0	52	40	A1+
P1.1	51	39	A1+
P1.2	50	38	A1+
P1.3	49	37	A1+
P1.4	48	36	A1+
P1.5	47	35	A1+
P1.7	55	–	A1+
P1.8	54	–	A1+
P1.9	53	–	A1+
P1.15	46	–	A1+
P2.0	34	26	A1+
P2.1	33	25	A1+	After a system reset, via HWSEL this pin selects the DB.TDO function.
P2.2	32	24	A1+
P2.3	31	23	A1+
P2.4	30	22	A1+
P2.5	29	21	A1+
P2.6	36	–	A1+
P2.7	35	–	A1+
P2.8	28	–	A1+
P2.9	27	–	A1+
P2.14	26	–	A1+
P2.15	25	–	A1+
P3.0	5	–	A1+
P14.0	20	16	AN/DIG_IN
P14.3	19	15	AN/DIG_IN
P14.4	18	14	AN/DIG_IN
P14.5	17	13	AN/DIG_IN
P14.6	16	12	AN/DIG_IN
P14.7	15	11	AN/DIG_IN
P14.8	24	20	AN/DAC/DIG_IN
P14.9	23	19	AN/DAC/DIG_IN
P14.14	14	–	AN/DIG_IN
USB_DP	7	4	special
USB_DM	6	3	special
HIB_IO_0	10	7	A1 special	At the first power-up and with every reset of the hibernate domain this pin is configured as open-drain output and drives "0". As output the medium driver mode is active.
TCK	45	34	A1	Weak pull-down active.
TMS	44	33	A1+	Weak pull-up active. As output the strong-soft driver mode is active.
$\stackrel{<p>¯</p>}{\mathrm{<p>P</p>}\mathrm{<p>O</p>}\mathrm{<p>R</p>}\mathrm{<p>S</p>}\mathrm{<p>T</p>}}$	43	32	special	Strong pull-down controlled by EVR. Weak pull-up active while strong pull-down is not active.
XTAL1	39	29	clock_IN
XTAL2	40	30	clock_O
RTC_XTAL1	11	8	clock_IN
RTC_XTAL2	12	9	clock_O
VBAT	13	10	Power	When VDDP is supplied VBAT has to be supplied as well.
VDDA/VAREF	22	18	AN_Power/AN_Ref	Shared analog supply and reference voltage pin.
VSSA/VAGND	21	17	AN_Power/AN_Ref	Shared analog supply and reference ground pin.
VDDC	9	6	Power
VDDC	42	31	Power
VDDP	8	5	Power
VDDP	38	28	Power
VDDP	56	41	Power
VSS	37	27	Power
VSSO	41	–	Power
VSS	Exp. Pad	Exp. Pad	Power	Exposed Die Pad The exposed die pad is connected internally to VSS. For proper operation, it is mandatory to connect the exposed pad directly to the common ground on the board. For thermal aspects, please refer to the Datasheet. Board layout examples are given in an application note.

Port I/O Functions

The following general scheme is used to describe each PORT pin:

Table 12. Port I/O Function Description

Function	Outputs			Inputs
	ALT1	ALTn	HWO0	HWI0	Input	Input
P0.0		MODA.OUT	MODB.OUT	MODB.INA	MODC.INA
Pn.y	MODA.OUT				MODA.INA	MODC.INB

Figure 6. Simplified Port Structure

Pn.y is the port pin name, defining the control and data bits/registers associated with it. As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT defines the output value.

Up to four alternate output functions (ALT1/2/3/4) can be mapped to a single port pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective module, with the pin characteristics controlled by the port registers (within the limits of the connected pad).

The port pin input can be connected to multiple peripherals. Most peripherals have an input multiplexer to select between different possible input sources.

The input path is also active while the pin is configured as output. This allows to feedback an output to on-chip resources without wasting an additional external pin.

By Pn_HWSEL it is possible to select between different hardware “masters” (HWO0/HWI0). The selected peripheral can take control of the pin(s). Hardware control overrules settings in the respective port pin registers.

Port I/O Function Table

Table 13. Port I/O Functions

Function	Output					Input
	ALT1	ALT2	ALT3	ALT4	HWO0	HWI0	Input	Input	Input	Input	Input	Input	Input	Input
P0.0		CAN. N0_TXD	CCU80.OUT21	LEDTS0.COL2			U1C1. DX0D		ERU0.0B0	USB.VBUSDETECT A		HRPWM0.C1INB
P0.1		U1C1. DOUT0	CCU80.OUT11	LEDTS0.COL3					ERU0.0A0			HRPWM0.C2INB
P0.2		U1C1. SELO1	CCU80.OUT01	HRPWM0.HROUT01	U1C0. DOUT3	U1C0. HWIN3			ERU0.3B3
P0.3			CCU80.OUT20	HRPWM0.HROUT20	U1C0. DOUT2	U1C0. HWIN2				ERU1.3B0
P0.4			CCU80.OUT10	HRPWM0.HROUT21	U1C0. DOUT1	U1C0. HWIN1		U1C0.DX0A	ERU0.2B3
P0.5		U1C0. DOUT0	CCU80.OUT00	HRPWM0.HROUT00	U1C0. DOUT0	U1C0. HWIN0		U1C0.DX0B		ERU1.3A0
P0.6		U1C0. SELO0	CCU80.OUT30	HRPWM0.HROUT30				U1C0.DX2A	ERU0.3B2		CCU80.IN2B
P0.7	WWDT.SERVICE_OUT	U0C0. SELO0		HRPWM0.HROUT11		DB.TDI	U0C0. DX2B		ERU0.2B1		CCU80.IN0A	CCU80.IN1A	CCU80.IN2A	CCU80.IN3A
P0.8	SCU.EXTCLK	U0C0. SCLKOUT		HRPWM0.HROUT10		$\stackrel{<p>¯</p>}{\mathrm{<p>D</p>}\mathrm{<p>B</p>}\mathrm{<p>.</p>}\mathrm{<p>T</p>}\mathrm{<p>R</p>}\mathrm{<p>S</p>}\mathrm{<p>T</p>}}$	U0C0. DX1B		ERU0.2A1		CCU80.IN1B
P0.9	HRPWM0.HROUT31	U1C1. SELO0	CCU80.OUT12	LEDTS0.COL0			U1C1. DX2A		ERU0.1B0
P0.10		U1C1. SCLKOUT	CCU80.OUT02	LEDTS0.COL1			U1C1. DX1A		ERU0.1A0
P0.11		U1C0. SCLKOUT	CCU80.OUT31					U1C0.DX1A	ERU0.3A2
P1.0		U0C0. SELO0	CCU40.OUT3	ERU1.PDOUT3			U0C0. DX2A		ERU0.3B0		CCU40.IN3A	HRPWM0.C0INA
P1.1		U0C0. SCLKOUT	CCU40.OUT2	ERU1.PDOUT2			U0C0. DX1A	POSIF0.IN2A	ERU0.3A0		CCU40.IN2A	HRPWM0.C1INA
P1.2			CCU40.OUT1	ERU1.PDOUT1	U0C0. DOUT3	U0C0. HWIN3		POSIF0.IN1A		ERU1.2B0	CCU40.IN1A	HRPWM0.C2INA
P1.3		U0C0. MCLKOUT	CCU40.OUT0	ERU1.PDOUT0	U0C0. DOUT2	U0C0. HWIN2		POSIF0.IN0A		ERU1.2A0	CCU40.IN0A	HRPWM0.C0INB
P1.4	WWDT.SERVICE_OUT	CAN. N0_TXD	CCU80.OUT33		U0C0. DOUT1	U0C0. HWIN1	U0C0. DX0B	CAN.N1_RXDD	ERU0.2B0		CCU41.IN0C	HRPWM0.BL0A
P1.5	CAN.N1_TXD	U0C0. DOUT0	CCU80.OUT23		U0C0. DOUT0	U0C0. HWIN0	U0C0. DX0A	CAN.N0_RXDA	ERU0.2A0	ERU1.0A0	CCU41.IN1C
P1.7		U0C0. DOUT0		U1C1.SELO2						USB.VBUSDETECT B
P1.8		U0C0. SELO1		U1C1.SCLKOUT
P1.9	U0C0.SCLKOUT			U1C1.DOUT0
P1.15	SCU.EXTCLK			U1C0.DOUT0						ERU1.1A0
P2.0	CAN.N0_TXD			LEDTS0.COL1					ERU0.0B3		CCU40.IN1C
P2.1				LEDTS0.COL0	DB.TDO/TRACESWO					ERU1.0B0	CCU40.IN0C
P2.2	VADC.EMUX00		CCU41.OUT3	LEDTS0.LINE0	LEDTS0.EXTENDED0	LEDTS0.TSIN0A		U0C1.DX0A	ERU0.1B2		CCU41.IN3A
P2.3	VADC.EMUX01	U0C1. SELO0	CCU41.OUT2	LEDTS0.LINE1	LEDTS0.EXTENDED1	LEDTS0.TSIN1A		U0C1.DX2A	ERU0.1A2		CCU41.IN2A
P2.4	VADC.EMUX02	U0C1. SCLKOUT	CCU41.OUT1	LEDTS0.LINE2	LEDTS0.EXTENDED2	LEDTS0.TSIN2A		U0C1.DX1A	ERU0.0B2		CCU41.IN1A	HRPWM0.BL1A
P2.5		U0C1. DOUT0	CCU41.OUT0	LEDTS0.LINE3	LEDTS0.EXTENDED3	LEDTS0.TSIN3A		U0C1.DX0B	ERU0.0A2		CCU41.IN0A	HRPWM0.BL2A
P2.6			CCU80.OUT13	LEDTS0.COL3				CAN.N1_RXDA	ERU0.1B3		CCU40.IN3C
P2.7		CAN. N1_TXD	CCU80.OUT03	LEDTS0.COL2						ERU1.1B0	CCU40.IN2C
P2.8			CCU80.OUT32	LEDTS0.LINE4	LEDTS0.EXTENDED4	LEDTS0.TSIN4A	DAC.TRIGGER5				CCU40.IN0B	CCU40.IN1B	CCU40.IN2B	CCU40.IN3B
P2.9			CCU80.OUT22	LEDTS0.LINE5	LEDTS0.EXTENDED5	LEDTS0.TSIN5A	DAC.TRIGGER4				CCU41.IN0B	CCU41.IN1B	CCU41.IN2B	CCU41.IN3B
P2.14	VADC.EMUX11	U1C0. DOUT0	CCU80.OUT21					U1C0.DX0D
P2.15	VADC.EMUX12		CCU80.OUT11	LEDTS0.LINE6	LEDTS0.EXTENDED6	LEDTS0.TSIN6A		U1C0.DX0C
P3.0		U0C1. SCLKOUT					U0C1.DX1B				CCU80.IN2C
P14.0							VADC.G0CH0
P14.3							VADC.G0CH3	VADC.G1CH3			CAN.N0_RXDB
P14.4							VADC.G0CH4
P14.5							VADC.G0CH5				POSIF0.IN2B
P14.6							VADC.G0CH6				POSIF0.IN1B		G0ORC6
P14.7							VADC.G0CH7				POSIF0.IN0B
P14.8					DAC.OUT_0			VADC.G1CH0
P14.9					DAC.OUT_1			VADC.G1CH1
P14.14								VADC.G1CH6					G1ORC6
USB_DP
USB_DM
HIB_IO_0	HIBOUT	WWDT. SERVICE_OUT					WAKEUPA			USB.VBUSDETECT C
TCK						DB.TCK/SWCLK
TMS					DB.TMS/SWDIO
$\stackrel{<p>¯</p>}{\mathrm{<p>P</p>}\mathrm{<p>O</p>}\mathrm{<p>R</p>}\mathrm{<p>S</p>}\mathrm{<p>T</p>}}$
XTAL1							U0C0.DX0F	U0C1.DX0F	U1C0.DX0F	U1C1.DX0F
XTAL2
RTC_XTAL1									ERU0.1B1
RTC_XTAL2

Power Connection Scheme

Figure 7

shows a reference power connection scheme for the XMC4[12]00.

Figure 7. Power Connection Scheme

Every power supply pin needs to be connected. Different pins of the same supply need also to be externally connected. As example, all V_DDP pins must be connected externally to one V_DDP net. In this reference scheme one 100 nF capacitor is connected at each supply pin against V_SS . An additional 10 µF capacitor is connected to the V_DDP nets and an additional 4.7uF capacitor to the V_DDC nets.

The XMC4[12]00 has a common ground concept, all V_SS , V_SSA and V_SSO pins share the same ground potential. In packages with an exposed die pad it must be connected to the common ground as well.

There are no dedicated connections for the analog reference V_AREF and V_AGND . Instead, they share the same pins as the analog supply pins V_DDA and V_SSA . Some analog channels can optionally serve as “Alternate Reference”; further details on this operating mode are described in the Reference Manual.

When V_DDP is supplied, V_BAT must be supplied as well. If no other supply source (e.g. battery) is connected to V_BAT , the V_BAT pin can also be connected directly to V_DDP .

Electrical Parameters

General Parameters

Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the XMC4[12]00 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”:

• CC

  Such parameters indicate

  C

  ontroller

  C

  haracteristics, which are a distinctive feature of the XMC4[12]00 and must be regarded for system design.

• SR

  Such parameters indicate

  S

  ystem

  R

  equirements, which must be provided by the application system in which the XMC4[12]00 is designed in.

Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Table 14. Absolute Maximum Rating Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Storage temperature	TST SR	-65	–	150	°C	–
Junction temperature	TJ SR	-40	–	150	°C	–
Voltage at 3.3 V power supply pins with respect to VSS	VDDP SR	–	–	4.3	V	–
Voltage on any Class A and dedicated input pin with respect to VSS	VIN SR	-1.0	–	VDDP + 1.0 or max. 4.3	V	whichever is lower
Voltage on any analog input pin with respect to VAGND	VAIN VAREF SR	-1.0	–	VDDP + 1.0 or max. 4.3	V	whichever is lower
Input current on any pin during overload condition	IIN SR	-10	–	+10	mA
Absolute maximum sum of all input circuit currents for one port group during overload condition 6	Σ IIN SR	-25	–	+25	mA
Absolute maximum sum of all input circuit currents during overload condition	Σ IIN SR	-100	–	+100	mA

Figure 8

explains the input voltage ranges of V_IN and V_AIN and its dependency to the supply level of V_DDP . The input voltage must not exceed 4.3 V, and it must not be more than 1.0 V above V_DDP . For the range up to V_DDP

• 1.0 V also see the definition of the overload conditions in Pin Reliability in Overload .

Figure 8. Absolute Maximum Input Voltage Ranges

Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification.

Table 15

defines overload conditions that will not cause any negative reliability impact if all the following conditions are met:

• full operation life-time is not exceeded

• Operating Conditions

  are met for

  • pad supply levels ( V_DDP or V_DDA )

  • temperature

If a pin current is outside of the

Operating Conditions

but within the overload parameters, then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters.

Note:
An overload condition on one or more pins does not require a reset.

Note:
A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery.

Table 15. Overload Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Input current on any port pin during overload condition	IOV SR	-5	–	5	mA
Absolute sum of all input circuit currents for one port group during overload condition 7	IOVG SR	–	–	20	mA	Σ| IOVx |, for all IOVx < 0 mA
		–	–	20	mA	Σ| IOVx |, for all IOVx > 0 mA
Absolute sum of all input circuit currents during overload condition	IOVS SR	–	–	80	mA	Σ IOVG

Figure 9

shows the path of the input currents during overload via the ESD protection structures. The diodes against V_DDP and ground are a simplified representation of these ESD protection structures.

Figure 9. Input Overload Current via ESD structures

Table 16

and

Table 17

list input voltages that can be reached under overload conditions. Note that the absolute maximum input voltages as defined in the

Absolute Maximum Ratings

must not be exceeded during overload.

Table 16. PN-Junction Characteristics for positive Overload

Pad Type	IOV = 5 mA, TJ = -40°C	IOV = 5 mA, TJ = 150°C
A1/A1+	VIN = VDDP + 1.0 V	VIN = VDDP+ 0.75 V
AN/DIG_IN	VIN = VDDP + 1.0 V	VIN = VDDP + 0.75 V

Table 17. PN-Junction Characteristics for negative Overload

Pad Type	IOV = 5 mA, TJ = -40°C	IOV = 5 mA, TJ = 150°C
A1/A1+	VIN = VSS - 1.0 V	VIN = VSS - 0.75 V
AN/DIG_IN	VIN = VDDP - 1.0 V	VIN = VDDP - 0.75 V

Table 18. Port Groups for Overload and Short-Circuit Current Sum Parameters

Group	Pins
1	P0.[12:0], P3.0
2	P14.[8:0]
3	P2.[15:0]
4	P1.[15:0]

Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the

Input/Output Pins

.

Table 19. Pad Driver and Pad Classes Overview

Class	Power Supply	Type	Sub-Class	Speed Grade	Load	Termination
A	3.3 V	LVTTL I/O, LVTTL outputs	A1 (e.g. GPIO)	6 MHz	100 pF	No
			A1+ (e.g. serial I/Os)	25 MHz	50 pF	Series termination recommended

Figure 10. Output Slopes with different Pad Driver Modes

Figure 10

is a qualitative display of the resulting output slope performance with different output driver modes. The detailed input and output characteristics are listed in

Input/Output Pins

.

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the XMC4[12]00. All parameters specified in the following tables refer to these operating conditions, unless noted otherwise.

Table 20. Operating Conditions Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Ambient Temperature	TA SR	-40	–	85	°C	Temp. Range F
		-40	–	125	°C	Temp. Range K
Digital supply voltage	VDDP SR	3.13	3.3	3.63	V
Core Supply Voltage	VDDC CC	– 8	1.3	–	V	Generated internally
Digital ground voltage	VSS SR	0	–	–	V
ADC analog supply voltage	VDDA SR	3.0	3.3	3.6 9	V
Analog ground voltage for VDDA	VSSA SR	-0.1	0	0.1	V
Battery Supply Voltage for Hibernate Domain 10	VBAT SR	1.95 11	–	3.63	V	When VDDP is supplied VBAT has to be supplied as well.
System Frequency	fSYS SR	–	–	80	MHz
Short circuit current of digital outputs	ISC SR	-5	–	5	mA
Absolute sum of short circuit currents per pin group 12	Σ ISC_PG SR	–	–	20	mA
Absolute sum of short circuit currents of the device	Σ ISC_D SR	–	–	100	mA

DC Parameters

Input/Output Pins

The digital input stage of the shared analog/digital input pins is identical to the input stage of the standard digital input/output pins.

The pull-up characteristics (I_PUH) and the input high and low voltage levels (V_IH and V_IL) of the $\overline{PORST}$ pin are identical to the respective values of the standard digital input/output pins.

Table 21. Standard Pad Parameters

Parameter	Symbol	Values		Unit	Note/Test Condition
		Min.	Max.
Pin capacitance (digital inputs/outputs)	CIO CC	–	10	pF
Pull-down current	| IPDL | SR	150	–	μA	VIN ≥ 0.6 × VDDP
		–	10	μA	VIN ≤ 0.36 × VDDP
Pull-up current	| IPUH | SR	–	10	μA	14 VIN ≥ 0.6 × VDDP
		100	–	μA	13 VIN ≤ 0.36 × VDDP
Input Hysteresis for pads of all A classes 15	HYSA CC	0.1 × VDDP	–	V
$\stackrel{<p>¯</p>}{\mathrm{<p>P</p>}\mathrm{<p>O</p>}\mathrm{<p>R</p>}\mathrm{<p>S</p>}\mathrm{<p>T</p>}}$ spike filter always blocked pulse duration	tSF1 CC	–	10	ns
$\stackrel{<p>¯</p>}{\mathrm{<p>P</p>}\mathrm{<p>O</p>}\mathrm{<p>R</p>}\mathrm{<p>S</p>}\mathrm{<p>T</p>}}$ spike filter pass-through pulse duration	tSF2 CC	100	–	ns
$\stackrel{<p>¯</p>}{\mathrm{<p>P</p>}\mathrm{<p>O</p>}\mathrm{<p>R</p>}\mathrm{<p>S</p>}\mathrm{<p>T</p>}}$ pull-down current	| IPPD | CC	13	–	mA	Vi = 1.0 V

Figure 11. Pull Device Input Characteristics

Figure 11

visualizes the input characteristics with an active internal pull device:

• in the cases “A” the internal pull device is overridden by a strong external driver;

• in the cases “B” the internal pull device defines the input logical state against a weak external load.

Table 22. Standard Pads Class_A1

Parameter	Symbol	Values		Unit	Note/Test Condition
		Min.	Max.
Input leakage current	IOZA1 CC	-500	500	nA	0 V ≤ VIN ≤ VDDP
Input high voltage	VIHA1 SR	0.6 × VDDP	VDDP + 0.3	V	max. 3.6 V
Input low voltage	VILA1 SR	-0.3	0.36 × VDDP	V
Output high voltage, POD = weak	VOHA1 CC	VDDP - 0.4	–	V	IOH ≥ -400 μA
		2.4	–	V	IOH ≥ -500 μA
Output high voltage, POD 16 = medium		VDDP - 0.4	–	V	IOH ≥ -1.4 mA
		2.4	–	V	IOH ≥ -2 mA
Output low voltage	VOLA1 CC	–	0.4	V	IOL ≤ 500 μA; POD16 = weak
		–	0.4	V	IOL ≤ 2 mA; POD16 = medium
Fall time	tFA1 CC	–	150	ns	CL = 20 pF; POD16 = weak
		–	50	ns	CL = 50 pF; POD16 = medium
Rise time	tRA1 CC	–	150	ns	CL = 20 pF; POD16 = weak
		–	50	ns	CL = 50 pF; POD16 = medium

Table 23. Standard Pads Class_A1+

Parameter	Symbol	Values		Unit	Note/Test Condition
		Min.	Max.
Input leakage current	IOZA1+ CC	-1	1	µA	0 V ≤ VIN ≤ VDDP
Input high voltage	VIHA1+ SR	0.6 × VDDP	VDDP + 0.3	V	max. 3.6 V
Input low voltage	VILA1+ SR	-0.3	0.36 × VDDP	V
Output high voltage, POD = weak	VOHA1+ CC	VDDP - 0.4	–	V	IOH ≥ -400 μA
		2.4	–	V	IOH ≥ -500 μA
Output high voltage, POD 17 = medium		VDDP - 0.4	–	V	IOH ≥ -1.4 mA
		2.4	–	V	IOH ≥ -2 mA
Output high voltage, POD 17 = strong		VDDP - 0.4	–	V	IOH ≥ -1.4 mA
		2.4	–	V	IOH ≥ -2 mA
Output low voltage	VOLA1+ CC	–	0.4	V	IOL ≤ 500 μA; POD17 = weak
		–	0.4	V	IOL ≤ 2 mA; POD17 = medium
		–	0.4	V	IOL ≤ 2 mA; POD17 = strong
Fall time	tFA1+ CC	–	150	ns	CL = 20 pF; POD17 = weak
		–	50	ns	CL = 50 pF; POD17 = medium
		–	28	ns	CL = 50 pF; POD17 = strong; edge = slow
		–	16	ns	CL = 50 pF; POD17 = strong; edge = soft;
Rise time	tRA1+ CC	–	150	ns	CL = 20 pF; POD17 = weak
		–	50	ns	CL = 50 pF; POD17 = medium
		–	28	ns	CL = 50 pF; POD17 = strong; edge = slow
		–	16	ns	CL = 50 pF; POD17 = strong; edge = soft

Table 24. HIB_IO Class_A1 special Pads

Parameter	Symbol	Values		Unit	Note/Test Condition
		Min.	Max.
Input leakage current	IOZHIB CC	-500	500	nA	0 V ≤ VIN ≤ VBAT
Input high voltage	VIHHIB SR	0.6 × VBAT	VBAT + 0.3	V	max. 3.6 V
Input low voltage	VILHIB SR	-0.3	0.36 × VBAT	V
Input Hysteresis for HIB_IO pins	HYSHIB CC	0.1 × VBAT	–	V	VBAT ≥ 3.13 V
		0.06 × VBAT	–	V	VBAT < 3.13 V
Output high voltage, POD 18 = medium	VOHHIB CC	VBAT - 0.4	–	V	IOH ≥ -1.4 mA
Output low voltage	VOLHIB CC	–	0.4	V	IOL ≤ 2 mA
Fall time	tFHIB CC	–	50	ns	VBAT ≥ 3.13 V CL = 50 pF
		–	100	ns	VBAT < 3.13 V CL = 50 pF
Rise time	tRHIB CC	–	50	ns	VBAT ≥ 3.13 V CL = 50 pF
		–	100	ns	VBAT < 3.13 V CL = 50 pF

Analog to Digital Converters (ADCx)

Table 25. ADC Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Analog reference voltage	VAREF SR	–	–	–	V	VAREF = VDDA shared analog supply and reference input pin
Alternate reference voltage	VAREF SR	VAGND + 1	–	VDDA + 0.0520	V
Analog reference ground	VAGND SR	–	–	–	V	VAGND = VSSA shared analog supply and reference input pin
Alternate reference voltage range 19 21	VAREF - VAGND SR	1	–	VDDA + 0.1	V
Analog input voltage	VAIN SR	VAGND	–	VDDA	V
Input leakage at analog inputs 22	IOZ1 CC	-100	–	200	nA	0.03 × VDDA < VAIN < 0.97 × VDDA
		-500	–	100	nA	0 V ≤ VAIN ≤ 0.03 × VDDA
		-100	–	500	nA	0.97 × VDDA ≤ VAIN ≤ VDDA
Internal ADC clock	fADCI CC	2	–	30	MHz	VDDA = 3.3 V
Switched capacitance at the analog voltage inputs 23	CAINSW CC	–	4	6.5	pF
Total capacitance of an analog input	CAINTOT CC	–	12	20	pF
Switched capacitance at the alternate reference voltage input 19 24	CAREFSW CC	–	15	30	pF
Total capacitance of the alternate reference inputs 19	CAREFTOT CC	–	20	40	pF
Total Unadjusted Error	TUE CC	-6	–	6	LSB	12-bit resolution; VDDA = 3.3 V; VAREF = VDDA25
Differential Non-Linearity Error	EADNL CC	-4.5	–	4.5	LSB
Gain Error 26	EAGAIN CC	-6	–	6	LSB
Integral Non-Linearity 26	EAINL CC	-4.5	–	4.5	LSB
Offset Error 26	EAOFF CC	-6	–	6	LSB
RMS Noise 27	ENRMS CC	–	1	22829	LSB
Worst case ADC VDDA power supply current per active converter	IDDAA CC	–	1.5	2	mA	during conversion VDDP = 3.6 V, TJ = 150°C
Charge consumption on alternate reference per conversion 19	QCONV CC	–	30	–	pC	0 V ≤ VAREF ≤ VDDA30
ON resistance of the analog input path	RAIN CC	–	600	1200	Ohm
ON resistance for the ADC test (pull down for AIN7)	RAIN7T CC	180	550	900	Ohm

Figure 12.

VADC Reference Voltage Range

The power-up calibration of the ADC requires a maximum number of 4352 f_ADCI cycles.

Figure 13. ADCx Input Circuits

Figure 14.ADCx Analog Input Leakage Current

Conversion Time

Table 26. Conversion Time (Operating Conditions apply)

Parameter	Symbol	Values	Unit	Note
Conversion time	tC CC	2 × TADC + (2 + N + STC + PC +DM) × TADCI	µs	N = 8, 10, 12 for N-bit conversion TADC = 1/ fPERIPH TADCI = 1/ fADCI

• STC defines additional clock cycles to extend the sample time

• PC adds two cycles if post-calibration is enabled

• DM adds one cycle for an extended conversion time of the MSB

Conversion Time Examples

System assumptions (max. f_ADC ):

f_ADC = 80 MHz i.e. t_ADC = 12.5 ns, DIVA = 2, f_ADCI = 26.7 MHz i.e. t_ADCI = 37.5 ns

According to the given formulas the following minimum conversion times can be achieved (STC = 0, DM = 0):

12-bit post-calibrated conversion (PC = 2):

t_CN12C = (2 + 12 + 2) × t_ADCI + 2 × t_ADC = 16 × 37.5 ns + 2 × 12.5 ns = 625 ns

12-bit uncalibrated conversion:

t_CN12 = (2 + 12) × t_ADCI + 2 × t_ADC = 14 × 37.5 ns + 2 × 12.5 ns = 550 ns

10-bit uncalibrated conversion:

t_CN10 = (2 + 10) × t_ADCI + 2 × t_ADC = 12 × 37.5 ns + 2 × 12.5 ns = 475 ns

8-bit uncalibrated:

t_CN8 = (2 + 8) × t_ADCI + 2 × t_ADC = 10 × 37.5 ns + 2 × 12.5 ns = 400 ns

System assumptions (max. f_ADCI ):

f_ADC = 60 MHz i.e. t_ADC = 16.67 ns, DIVA = 1, f_ADCI = 30 MHz i.e. t_ADCI = 33.33 ns

12-bit post-calibrated conversion (PC = 2):

t_CN12C = (2 + 12 + 2) × t_ADCI + 2 × t_ADC = 16 × 33.33 ns + 2 × 16.67 ns = 566 ns

Digital to Analog Converters (DACx)

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 27. DAC Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
RMS supply current	IDD CC	–	2.5	4	mA	per active DAC channel, without load currents of DAC outputs
Resolution	RES CC	–	12	–	Bit
Update rate	fURATE_A CC	–		2	Msample/s	data rate, where DAC can follow 64 LSB code jumps to ± 1LSB accuracy
Update rate	fURATE_F CC	–		5	Msample/s	data rate, where DAC can follow 64 LSB code jumps to ± 4 LSB accuracy
Settling time	tSETTLE CC	–	1	2	μs	at full scale jump, output voltage reaches target value ± 20 LSB
Slew rate	SR CC	2	5	–	V/μs
Minimum output voltage	VOUT_MIN CC	–	0.3	–	V	code value unsigned: 000 ; signed: 800
Maximum output voltage	VOUT_MAX CC	–	2.5	–	V	code value unsigned: FFF ; signed: 7FF
Integral non-linearity 31	INL CC	-5.5	±2.5	5.5	LSB	RL ≥ 5 kOhm, CL ≤ 50 pF
Differential non-linearity	DNL CC	-2	±1	2	LSB	RL ≥ 5 kOhm, CL ≤ 50 pF
Offset error	EDOFF CC		±20		mV
Gain error	EDG_IN CC	-5	0	5	%
Startup time	tSTARTUP CC	–	15	30	µs	time from output enabling till code valid ±16 LSB
3dB Bandwidth of Output Buffer	fC1 CC	2.5	5	–	MHz	verified by design
Output sourcing current	IOUT_SOURCE CC	–	-30	–	mA
Output sinking current	IOUT_SINK CC	–	0.6	–	mA
Output resistance	ROUT CC	–	50	–	Ohm
Load resistance	RL SR	5	–	–	kOhm
Load capacitance	CL SR	–	–	50	pF
Signal-to-Noise Ratio	SNR CC	–	70	–	dB	examination bandwidth < 25 kHz
Total Harmonic Distortion	THD CC	–	70	–	dB	examination bandwidth < 25 kHz
Power Supply Rejection Ratio	PSRR CC	–	56	–	dB	to VDDA verified by design

Conversion Calculation

Unsigned:

DACxDATA = 4095 × (V_OUT - V_{OUT_MIN}) / (V_{OUT_MAX} - V_{OUT_MIN})

Signed:

DACxDATA = 4095 × (V_OUT - V_{OUT_MIN}) / (V_{OUT_MAX} - V_{OUT_MIN}) - 2048

Figure 15. DAC Conversion Examples

Out-of-Range Comparator (ORC)

The Out-of-Range Comparator (ORC) triggers on analog input voltages ( V_AIN ) above the analog reference

32

( V_AREF ) on selected input pins (GxORCy) and generates a service request trigger (GxORCOUTy).

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

The parameters in

Table 28

apply for the maximum reference voltage V_AREF

V_DDA + 50 mV.

Table 28. ORC Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
DC Switching Level	VODC CC	100	125	200	mV	Ax-marking devices VAIN ≥ VAREF + VODC
Hysteresis	VOHYS CC	50	–	VODC	mV
Detection Delay of a persistent Overvoltage	tODD CC	55	–	450	ns	Ax-marking devices VAIN ≥ VAREF + 200 mV
		45	–	105	ns	VAIN ≥ VAREF + 400 mV
Always detected Overvoltage Pulse	tOPDD CC	440	–	–	ns	Ax-marking devices VAIN ≥ VAREF + 200 mV
		90	–	–	ns	VAIN ≥ VAREF + 400 mV
Never detected Overvoltage Pulse	tOPDN CC	–	–	49	ns	Ax-marking devices VAIN ≥ VAREF + 200 mV
		–	–	30	ns	VAIN ≥ VAREF + 400 mV
Release Delay	tORD CC	65	–	105	ns	VAIN ≤ VAREF
Enable Delay	tOED CC	–	100	200	ns

Figure 16. GxORCOUTy Trigger Generation

Figure 17. ORC Detection Ranges

High Resolution PWM (HRPWM)

The following chapters describe the operating conditions, characteristics and timing requirements, for all the components inside the HRPWM module. Each description is given for just one sub unit, e.g., one CSG or one HRC.

All the timing information is related to the module clock, f_hrpwm .

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

HRC characteristics

Table 29

summarizes the characteristics of the HRC units.

Table 29. HRC characteristics (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
High resolution step size 33 34	tHRS CC	–	150	–	ps
Startup time (after reset release)	tstart CC	–	–	2	µs

CMP and 10-bit DAC characteristics

The

Table 30

summarizes the characteristics of the CSG unit.

The specified characteristics require that the setup of the HRPWM follows the initialization sequence as documented in the Reference Manual.

Table 30. CMP and 10-bit DAC characteristics (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
DAC Resolution	RES CC		10		bits
DAC differential nonlinearity	DNL CC	-1	–	1.5	LSB	Monotonic behavior See Figure 18
DAC integral nonlinearity	INL CC	-3	–	3	LSB	See Figure 18
CSG Output Jitter	DCSG CC	–	–	1	clk
Bias startup time	tstart CC	–	–	98	us
Bias supply current	IDDbias CC	–	–	400	μA
CSGy startup time	tCSGS CC	–	–	2	μs
Input operation current 35	IDDCIN CC	-10	–	33	μA	See Figure 19
High Speed Mode
DAC output voltage range	VDOUT CC	VSS	–	VDDP	V
DAC propagation delay - Full scale	tFShs CC	–	–	80	ns	See Figure 20
Input Selector propagation delay - Full scale	tDhs CC	–	–	100	ns	See Figure 20
Comparator bandwidth	tDhs CC	20	–	–	ns
DAC CLK frequency	fclk SR	–	–	30	MHz
Supply current	IDDhs CC	–	–	940	μA
Low Speed Mode
DAC output voltage range	VDOUT CC	0.1 × VDDP 36	–	VDDP	V
DAC propagation delay - Full Scale	tFSls CC	–	–	160	ns	See Figure 20
Input Selector propagation delay - Full Scale	tDls CC	–	–	200	ns	See Figure 20
Comparator bandwidth	tDls CC	20	–	–	ns
DAC CLK frequency	fclk SR	–	–	30	MHz
Supply current	IDDls CC	–	–	300	µA

Figure 18. CSG DAC INL and DNL example

Figure 19. Input operation current

Figure 20. DAC and Input Selector Propagation Delay

Clocks

HRPWM DAC Conversion Clock

The DAC conversion clock can be generated internally or it can be controlled via a HRPWM module pin.

Table 31. External DAC conversion trigger operating conditions

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Frequency	fetrg SR	–	–	30 38	MHz
ON time	tonetrg SR	2 Tccu	–	–	ns
OFF time	toffetrg SR	2 Tccu 37 38	–	–	ns

CSG External Clock

It is possible to select an external source, that can be used as a clock for the slope generation, HRPWMx.ECLKy. This clock is synchronized internally with the module clock and therefore the external clock needs to meet the criterion described on

Table 32

.

Table 32.

External clock operating conditions

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Frequency	feclk SR	–	–	fhrpwm /4	MHz
ON time	toneclk SR	2 Tccu	–	–	ns
OFF time	toffeclk SR	2 Tccu 39 40	–	–	ns	Only the rising edge is used

Low Power Analog Comparator (LPAC)

The Low Power Analog Comparator (LPAC) triggers a wake-up event from Hibernate state or an interrupt trigger during normal operation. It does so by comparing V_BAT or another external sensor voltage V_LPS with a pre-programmed threshold voltage.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 33. Low Power Analog Comparator Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
VBAT supply voltage range for LPAC operation	VBAT SR	2.1	–	3.6	V
Sensor voltage range	VLPCS CC	0	–	1.2	V
Threshold step size	Vth CC	–	18.75	–	mV
Threshold trigger accuracy	Δ Vth CC	–	–	±10	%	for Vth > 0.4 V
Conversion time	tLPCC CC	–	–	250	μs
Average current consumption over time	ILPCAC CC	–	–	15	μA	conversion interval 10 ms
Current consumption during conversion	ILPCC CC	–	150	–	μA	41

Die Temperature Sensor

The Die Temperature Sensor (DTS) measures the junction temperature T_J .

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 34. Die Temperature Sensor Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Temperature sensor range	TSR SR	-40	–	150	°C
Linearity Error (to the below defined formula)	Δ TLE CC	–	±1	–	°C	per Δ TJ ≤ 30°C
Offset Error	Δ TOE CC	–	±6	–	°C	ΔTOE = TJ - TDTS VDDP ≤ 3.3 V42
Measurement time	tM CC	–	–	100	µs
Start-up time after reset inactive	tTSST SR	–	–	10	µs

The following formula calculates the temperature measured by the DTS in [°C] from the RESULT bit field of the DTSSTAT register.

Temperature T_DTS = (RESULT - 605)/2.05 [°C]

This formula and the values defined in

Table 34

apply with the following calibration values:

• DTSCON.BGTRIM = 8

  H

• DTSCON.REFTRIM = 4

  H

USB Device Interface DC Characteristics

The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification. High-Speed Mode is not supported.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 35. USB Device Data Line (USB_DP, USB_DM) Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Input low voltage	VIL SR	–	–	0.8	V
Input high voltage (driven)	VIH SR	2.0	–	–	V
Input high voltage (floating) 43	VIHZ SR	2.7	–	3.6	V
Differential input sensitivity	VDIS CC	0.2	–	–	V
Differential common mode range	VCM CC	0.8	–	2.5	V
Output low voltage	VOL CC	0.0	–	0.3	V	1.5 kOhm pull-up to 3.6 V
Output high voltage	VOH CC	2.8	–	3.6	V	15 kOhm pull-down to 0 V
DP pull-up resistor (idle bus)	RPUI CC	900	–	1575	Ohm
DP pull-up resistor (upstream port receiving)	RPUA CC	1 425	–	3090	Ohm
Input impedance DP, DM	ZINP CC	300	–	–	kOhm	0 V ≤ VIN ≤ VDDP
Driver output resistance DP, DM	ZDRV CC	28	–	44	Ohm

Oscillator Pins

Note:
It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

The oscillator pins can be operated with an external crystal (see

Figure 21

) or in direct input mode (see

Figure 22

).

Figure 21. Oscillator in Crystal Mode

Figure 22. Oscillator in Direct Input Mode

Table 36. OSC_XTAL Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Input frequency	fOSC SR	4	–	40	MHz	Direct Input Mode selected
		4	–	25	MHz	External Crystal Mode selected
Oscillator start-up time 44	tOSCS CC	–	–	10	ms
Input voltage at XTAL1	VIX SR	-0.5	–	VDDP + 0.5	V
Input amplitude (peak-to-peak) at XTAL1 45 46	VPPX SR	0.4 × VDDP	–	VDDP + 1.0	V
Input high voltage at XTAL1	VIHBX SR	1.0	–	VDDP + 0.5	V
Input low voltage at XTAL1 47	VILBX SR	-0.5	–	0.4	V
Input leakage current at XTAL1	IILX1 CC	-100	–	100	nA	Oscillator power down 0 V ≤ VIX ≤ VDDP

Table 37. RTC_XTAL Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Input frequency	fOSC SR	–	32.768	–	kHz
Oscillator start-up time 48	tOSCS CC	–	–	5	s
Input voltage at RTC_XTAL1	VIX SR	-0.3	–	VBAT + 0.3	V
Input amplitude (peak-to-peak) at RTC_XTAL1 49 51	VPPX SR	0.4	–	–	V
Input high voltage at RTC_XTAL1	VIHBX SR	0.6 × VBAT	–	VBAT + 0.3	V
Input low voltage at RTC_XTAL1 52	VILBX SR	-0.3	–	0.36 × VBAT	V
Input Hysteresis for RTC_XTAL1 50 53	VHYSX CC	0.1 × VBAT		–	V	3.0 V ≤ VBAT < 3.6 V
		0.03 × VBAT		–	V	VBAT < 3.0 V
Input leakage current at RTC_XTAL1	IILX1 CC	-100	–	100	nA	Oscillator power down 0 V ≤ VIX ≤ VBAT

Power Supply Current

The total power supply current defined below consists of a leakage and a switching component.

Application relevant values are typically lower than those given in the following tables, and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations).

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

If not stated otherwise, the operating conditions for the parameters in the following table are:

V_DDP = 3.3 V, T_A = 25°C

Table 38. Power Supply Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Active supply current 54 Peripherals enabled Frequency: fCPU / fPERIPH / fCCU in MHz	IDDPA CC	–	80	–	mA	80/80/80
		–	75	–		80/40/40
		–	73	–		40/40/80
		–	59	–		24/24/24
		–	50	–		1/1/1
Active supply current Code execution from RAM Flash in Sleep mode Frequency: fCPU / fPERIPH / fCCU in MHz	IDDPA CC	–	24	–	mA	80/80/80
		–	19	–		80/40/40
Active supply current 55 Peripherals disabled Frequency: fCPU / fPERIPH in MHz	IDDPA CC	–	63	–	mA	80/80/80
		–	62	–		80/40/40
		–	60	–		40/40/80
		–	54	–		24/24/24
		–	50	–		1/1/1
Sleep supply current 56 Peripherals enabled Frequency: fCPU / fPERIPH / fCCU in MHz	IDDPS CC	–	76	–	mA	80/80/80
		–	73	–		80/40/40
		–	70	–		40/40/80
		–	56	–		24/24/24
		–	47	–		1/1/1
fCPU / fPERIPH / fCCU in kHz		–	46	–		100/100/100
Sleep supply current 57 Peripherals disabled Frequency: fCPU / fPERIPH / fCCU in MHz	IDDPS CC	–	59	–	mA	80/80/80
		–	58	–		80/40/40
		–	57	–		40/40/80
		–	51	–		24/24/24
		–	46	–		1/1/1
fCPU / fPERIPH / fCCU in kHz		–	46	–		100/100/100
Deep Sleep supply current 58 Flash in Sleep mode Frequency: fCPU / fPERIPH / fCCU in MHz	IDDPD CC	–	6.9	–	mA	24/24/24
		–	4.3	–		4/4/4
		–	3.8	–		1/1/1
fCPU / fPERIPH / fCCU in kHz		–	4.5	–		100/100/100 59
Hibernate supply current RTC on 60	IDDPH CC	–	10.8	–	µA	VBAT = 3.3 V
		–	8.0	–		VBAT = 2.4 V
		–	6.8	–		VBAT = 2.0 V
Hibernate supply current RTC off 61	IDDPH CC	–	10.3	–	µA	VBAT = 3.3 V
		–	7.5	–		VBAT = 2.4 V
		–	6.3	–		VBAT = 2.0 V
Worst case active supply current 62	IDDPA CC	–	–	140 63	mA	VDDP = 3.6 V, TJ = 150°C
VDDA power supply current	IDDA CC	–	–	– 64	mA
IDDP current at $\stackrel{<p>¯</p>}{\mathrm{<p>P</p>}\mathrm{<p>O</p>}\mathrm{<p>R</p>}\mathrm{<p>S</p>}\mathrm{<p>T</p>}}$ Low	IDDP_PORST CC	–	–	24	mA	VDDP = 3.6 V, TJ = 150°C
Power Dissipation	PDISS CC	–	–	1	W	VDDP = 3.6 V, TJ = 150°C
Wake-up time from Sleep to Active mode	tSSA CC	–	6	–	cycles
Wake-up time from Deep Sleep to Active mode		–	–	–	ms	Defined by the wake-up of the Flash module, see Section 3.2.11
Wake-up time from Hibernate mode		–	–	–	ms	Wake-up via power-on reset event, see Section 3.3.2

Peripheral Idle Currents

Test conditions:

• f_sys and derived clocks at 80 MHz

• V_DDP = 3.3 V, T_a = 25°C

• all peripherals are held in reset (see the PRSTAT registers in the Reset Control Unit of the SCU)

• the peripheral clocks are disabled (see CGATSTAT registers in the Clock Control Unit of the SCU

• no I/O activity

• the given values are a result of differential measurements with asserted and deasserted peripheral reset and enabled clock of the peripheral under test

The tested peripheral is left in the state after the peripheral reset is deasserted, no further initialisation or configuration is done. For example no timer is running in the CCUs, no communication active in the USICs, etc.

Table 39. Peripheral Idle Currents

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
PORTS USB FCE WDT POSIFx	IPER CC	–	≤ 0.3	–	mA
MultiCAN ERU LEDTSCU0 CCU4x 65 CCU8x 65		–	≤ 1.0	–
DAC (digital)		–	1.3	–
USICx		–	3.0	–
VADC (digital) 66		–	4.5	–
DMAx		–	6.0	–

Flash Memory Parameters

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 40. Flash Memory Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Erase Time per 256 Kbyte Sector	tERP CC	–	5	5.5	s
Erase Time per 64 Kbyte Sector	tERP CC	–	1.2	1.4	s
Erase Time per 16 Kbyte Logical Sector	tERP CC	–	0.3	0.4	s
Program time per page 67	tPRP CC	–	5.5	11	ms
Erase suspend delay	tFL_ErSusp CC	–	–	15	ms
Wait time after margin change	tFL_MarginDel CC	10	–	–	µs
Wake-up time	tWU CC	–	–	270	µs
Read access time	ta CC	20	–	–	ns	For operation with 1/ fCPU < ta wait states must be configured 68
Data Retention Time, Physical Sector	tRET CC	20	–	–	years	Max. 1000 erase/program cycles
Data Retention Time, Logical Sector 69 70	tRETL CC	20	–	–	years	Max. 100 erase/program cycles
Data Retention Time, User Configuration Block (UCB) 69 70	tRTU CC	20	–	–	years	Max. 4 erase/program cycles per UCB
Endurance on 64 Kbyte Physical Sector PS4	NEPS4 CC	10000	–	–	cycles	BA-marking devices only! Cycling distributed over life time 71

AC Parameters

Testing Waveforms

Figure 23. Rise/Fall Time Parameters

Figure 24. Testing Waveform, Output Delay

Figure 25. Testing Waveform, Output High Impedance

Power-Up and Supply Monitoring

$\overline{PORST}$ is always asserted when V_DDP and/or V_DDC violate the respective thresholds.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Figure 26. $\overline{PORST}$ Circuit

Table 41. Supply Monitoring Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Digital supply voltage reset threshold	VPOR CC	2.79 72	–	3.05 73	V	74
Core supply voltage reset threshold	VPV CC	–	–	1.17	V
VDDP voltage to ensure defined pad states	VDDPPA CC	–	1.0	–	V
$\stackrel{<p>¯</p>}{\mathrm{<p>P</p>}\mathrm{<p>O</p>}\mathrm{<p>R</p>}\mathrm{<p>S</p>}\mathrm{<p>T</p>}}$ rise time	tPR SR	–	–	2	μs
Startup time from power-on reset with code execution from Flash	tSSW CC	–	2.5	3.5	ms	Time to the first user code instruction
VDDC ramp up time	tVCR CC	–	550	–	μs	Ramp up after power-on or after a reset triggered by a violation of VPOR or VPV

Figure 27.

Power-Up Behavior

Power Sequencing

While starting up and shutting down as well as when switching power modes of the system it is important to limit the current load steps. A typical cause for such load steps is changing the CPU frequency f_CPU . Load steps exceeding the below defined values may cause a power on reset triggered by the supply monitor.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 42. Power Sequencing Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Positive Load Step Current	Δ IPLS SR	–	–	50	mA	Load increase on VDDP Δ t ≤ 10 ns
Negative Load Step Current	Δ INLS SR	–	–	150	mA	Load decrease on VDDP Δ t ≤ 10 ns
VDDC Voltage Over-/Undershoot from Load Step	Δ VLS CC	–	–	±100	mV	For maximum positive or negative load step
Positive Load Step Settling Time	tPLSS SR	50	–	–	μs
Negative Load Step Settling Time	tNLSS SR	100	–	–	μs
External Buffer Capacitor on VDDC	CEXT SR	3	4.7	6	μF	In addition C = 100 nF capacitor on each VDDC pin

Positive Load Step Examples

System assumptions:

f_CPU = f_SYS, target frequency f_CPU = 80 MHz, main PLL f_VCO = 480 MHz, stepping done by K2 divider, t_PLSS between individual steps:

24 MHz - 48 MHz - 80 MHz (K2 steps 20 - 10 - 6)

24 MHz - 60 MHz - 80 MHz (K2 steps 20 - 8 - 6)

Phase Locked Loop (PLL) Characteristics

Main and USB PLL

Table 43. PLL Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Accumulated Jitter	DP CC	–	–	±5	ns	accumulated over 300 cycles fSYS = 80 MHz
Duty Cycle 75	DDC CC	46	50	54	%	Low pulse to total period, assuming an ideal input clock source
PLL base frequency	fPLLBASE CC	30	–	140	MHz
VCO input frequency	fREF CC	4	–	16	MHz
VCO frequency range	fVCO CC	260	–	520	MHz
PLL lock-in time	tL CC	–	–	400	μs

Internal Clock Source Characteristics

Fast Internal Clock Source

Table 44. Fast Internal Clock Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Nominal frequency	fOFINC CC	–	36.5	–	MHz	not calibrated
		–	24	–	MHz	calibrated
Accuracy	Δ fOFI CC	-0.5	–	0.5	%	automatic calibration 76 77
		-15	–	15	%	factory calibration, VDDP = 3.3 V
		-25	–	25	%	no calibration, VDDP = 3.3 V
		-7	–	7	%	Variation over voltage range 78 3.13 V ≤ VDDP ≤ 3.63 V
Start-up time	tOFIS CC	–	50	–	μs

Slow Internal Clock Source

Table 45. Slow Internal Clock Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Nominal frequency	fOSI CC	–	32.768	–	kHz
Accuracy	ΔfOSI CC	-4	–	4	%	VBAT = const. 0°C ≤ TA ≤ 85°C
		-5	–	5	%	VBAT = const. TA < 0°C or TA > 85°C
		-5	–	5	%	2.4 V ≤ VBAT, TA = 25°C
		-10	–	10	%	1.95 V ≤ VBAT < 2.4 V, TA = 25°C
Start-up time	tOSIS CC	–	50	–	μs

JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000.

Note:

These parameters are not subject to production test, but verified by design and/or characterization.

Note:

Operating conditions apply.

Table 46. JTAG Interface Timing Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
TCK clock period	t1 SR	30	–	–	ns	For CL = 20 pF on TDO
TCK clock period	t1 SR	40	–	–	ns	For CL = 50 pF on TDO
TCK high time	t2 SR	10	–	–	ns
TCK low time	t3 SR	10	–	–	ns
TCK clock rise time	t4 SR	–	–	4	ns
TCK clock fall time	t5 SR	–	–	4	ns
TDI/TMS setup to TCK rising edge	t6 SR	6	–	–	ns
TDI/TMS hold after TCK rising edge	t7 SR	6	–	–	ns
TDO valid after TCK falling edge (propagation delay)	t8 CC	–	–	17	ns	CL = 50 pF
		3	–	–	ns	CL = 20 pF
TDO hold after TCK falling edge 79	t18 CC	2	–	–	ns
TDO high imped. to valid from TCK falling edge 79 80	t9 CC	–	–	14	ns	CL = 50 pF
TDO valid to high imped. from TCK falling edge 79	t10 CC	–	–	13.5	ns	CL = 50 pF

Figure 28. Test Clock Timing (TCK)

Figure 29. JTAG Timing

Serial Wire Debug Port (SW-DP) Timing

The following parameters are applicable for communication through the SW-DP interface.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Note:
Operating conditions apply.

Table 47. SWD Interface Timing Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
SWDCLK clock period	tSC SR	25	–	–	ns	CL = 30 pF
		40	–	–	ns	CL = 50 pF
SWDCLK high time	t1 SR	10	–	500000	ns
SWDCLK low time	t2 SR	10	–	500000	ns
SWDIO input setup to SWDCLK rising edge	t3 SR	6	–	–	ns
SWDIO input hold after SWDCLK rising edge	t4 SR	6	–	–	ns
SWDIO output valid time after SWDCLK rising edge	t5 CC	–	–	17	ns	CL = 50 pF
		–	–	13	ns	CL = 30 pF
SWDIO output hold time from SWDCLK rising edge	t6 CC	3	–	–	ns

Figure 30. SWD Timing

Peripheral Timing

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Note:
Operating conditions apply.

Synchronous Serial Interface (USIC SSC) Timing

The following parameters are applicable for a USIC channel operated in SSC mode.

Note:
Operating Conditions apply.

Table 48. USIC SSC Master Mode Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
SCLKOUT master clock period	tCLK CC	40	–	–	ns
Slave select output SELO active to first SCLKOUT transmit edge	t1 CC	tSYS - 6.5	–	–	ns
Slave select output SELO inactive after last SCLKOUT receive edge	t2 CC	tSYS - 8.581	–	–	ns
Data output DOUT[3:0] valid time	t3 CC	-6	–	8	ns
Receive data input DX0/DX[5:3] setup time to SCLKOUT receive edge	t4 SR	23	–	–	ns
Data input DX0/DX[5:3] hold time from SCLKOUT receive edge	t5 SR	1	–	–	ns

Table 49. USIC SSC Slave Mode Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
DX1 slave clock period	tCLK SR	66.6	–	–	ns
Select input DX2 setup to first clock input DX1 transmit edge	t10 SR	3	–	–	ns
Select input DX2 hold after last clock input DX1 receive edge 82	t11 SR	4	–	–	ns
Receive data input DX0/DX[5:3] setup time to shift clock receive edge 82	t12 SR	6	–	–	ns
Data input DX0/DX[5:3] hold time from clock input DX1 receive edge 82	t13 SR	4	–	–	ns
Data output DOUT[3:0] valid time	t14 CC	0	–	24	ns

Figure 31. USIC - SSC Master/Slave Mode Timing

Note:

This timing diagram shows a standard configuration, for which the slave select signal is low-active, and the serial clock signal is not shifted and not inverted.

Inter-IC (IIC) Interface Timing

The following parameters are applicable for a USIC channel operated in IIC mode.

Note:
Operating Conditions apply.

Table 50. USIC IIC Standard Mode Timing

⁸³

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Fall time of both SDA and SCL	t1 CC/SR	–	–	300	ns
Rise time of both SDA and SCL	t2 CC/SR	–	–	1000	ns
Data hold time	t3 CC/SR	0	–	–	µs
Data set-up time	t4 CC/SR	250	–	–	ns
LOW period of SCL clock	t5 CC/SR	4.7	–	–	µs
HIGH period of SCL clock	t6 CC/SR	4.0	–	–	µs
Hold time for (repeated) START condition	t7 CC/SR	4.0	–	–	µs
Set-up time for repeated START condition	t8 CC/SR	4.7	–	–	µs
Set-up time for STOP condition	t9 CC/SR	4.0	–	–	µs
Bus free time between a STOP and START condition	t10 CC/SR	4.7	–	–	µs
Capacitive load for each bus line	Cb SR	–	–	400	pF

Table 51. USIC IIC Fast Mode Timing⁸⁴

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Fall time of both SDA and SCL	t1 CC/SR	20 + 0.1* Cb	–	300	ns
Rise time of both SDA and SCL	t2 CC/SR	20 + 0.1* Cb 85	–	300	ns
Data hold time	t3 CC/SR	0	–	–	µs
Data set-up time	t4 CC/SR	100	–	–	ns
LOW period of SCL clock	t5 CC/SR	1.3	–	–	µs
HIGH period of SCL clock	t6 CC/SR	0.6	–	–	µs
Hold time for (repeated) START condition	t7 CC/SR	0.6	–	–	µs
Set-up time for repeated START condition	t8 CC/SR	0.6	–	–	µs
Set-up time for STOP condition	t9 CC/SR	0.6	–	–	µs
Bus free time between a STOP and START condition	t10 CC/SR	1.3	–	–	µs
Capacitive load for each bus line	Cb SR	–	–	400	pF

Figure 32. USIC IIC Stand and Fast Mode Timing

Inter-IC Sound (IIS) Interface Timing

The following parameters are applicable for a USIC channel operated in IIS mode.

Note:,
Operating Conditions apply.

Table 52. USIC IIS Master Transmitter Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Clock period	t1 CC	33.3	–	–	ns
Clock high time	t2 CC	0.35 x t1min	–	–	ns
Clock low time	t3 CC	0.35 x t1min	–	–	ns
Hold time	t4 CC	0	–	–	ns
Clock rise time	t5 CC	–	–	0.15 x t1min	ns

Figure 33. USIC IIS Master Transmitter Timing

Table 53. USIC IIS Slave Receiver Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Clock period	t6 SR	66.6	–	–	ns
Clock high time	t7 SR	0.35 x t6min	–	–	ns
Clock low time	t8 SR	0.35 x t6min	–	–	ns
Set-up time	t9 SR	0.2 x t6min	–	–	ns
Hold time	t10 SR	0	–	–	ns

Figure 34. USIC IIS Slave Receiver Timing

USB Interface Characteristics

The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification. High-Speed Mode is not supported.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 54. USB Timing Parameters (operating conditions apply)

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Rise time	tR CC	4	–	20	ns	CL = 50 pF
Fall time	tF CC	4	–	20	ns	CL = 50 pF
Rise/Fall time matching	tR / tF CC	90	–	111.11	%	CL = 50 pF
Crossover voltage	VCRS CC	1.3	–	2.0	V	CL = 50 pF

Figure 35. USB Signal Timing

Package and Reliability

The XMC4[12]00 is a member of the XMC4000 Family of microcontrollers. It is also compatible to a certain extent with members of similar families or subfamilies.

Each package is optimized for the device it houses. Therefore, there may be slight differences between packages of the same pin-count but for different device types. In particular, the size of the Exposed Die Pad may vary.

If different device types are considered or planned for an application, it must be ensured that the board layout fits all packages under consideration.

Package Parameters

Table 55

provides the thermal characteristics of the packages used in XMC4[12]00. The availability of different packages for different markings is listed in

Table 2

.

Table 55. Thermal Characteristics of the Packages

Parameter	Symbol	Limit Values		Unit	Package Types
		Min.	Max.
Exposed Die Pad Dimensions	Ex × Ey CC	–	5.7 × 5.7	mm	PG-TQFP-64-19 PG-TQFP-64-21
		–	5.2 × 5.2	mm	PG-VQFN-48-71
Thermal resistance Junction-Ambient	RΘJA CC	–	23.4	K/W	PG-TQFP-64-19 PG-TQFP-64-21 86
		–	34.8	K/W	PG-VQFN-48-71 86
Package thickness 1.0 ±0.05 mm	–	–	1.2 Max	mm	PG-TQFP-64-19 PG-TQFP-64-21

Note:
For electrical reasons, it is required to connect the exposed pad to the board ground V_SS, independent of EMC and thermal requirements.

Thermal Considerations

When operating the XMC4[12]00 in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage.

The maximum heat that can be dissipated depends on the package and its integration into the target board. The “Thermal resistance R_ΘJA ” quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 150°C.

The difference between junction temperature and ambient temperature is determined by

Δ T = ( P_INT + P_IOSTAT + P_IODYN ) × R_ΘJA

The internal power consumption is defined as

P_INT = V_DDP × I_DDP (switching current and leakage current).

The static external power consumption caused by the output drivers is defined as

P_IOSTAT = Σ((V_DDP - V_OH) × I_OH) + Σ(V_OL × I_OL)

The dynamic external power consumption caused by the output drivers ( P_IODYN ) depends on the capacitive load connected to the respective pins and their switching frequencies.

If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation:

• Reduce V_DDP , if possible in the system

• Reduce the system frequency

• Reduce the number of output pins

• Reduce the load on active output drivers

Package Outlines

The availability of different packages for different devices types is listed in

Table 1

, specific packages for different device markings are listed in

Table 2

.

Figure 36. PG-TQFP-64-19 (Plastic Green Thin Profile Quad Flat Package)

Figure 37. PG-TQFP-64-21 (Plastic Green Thin Profile Quad Flat Package)

Figure 38. PG-VQFN-48-71 (Plastic Green Very Thin Profile Flat Non Leaded Package)

All dimensions in mm.

You can find complete information about Infineon packages, packing and marking in our Infineon Internet Page “Packages”:

http://www.infineon.com/packages

Quality Declarations

The qualification of the XMC4[12]00 is executed according to the JEDEC standard JESD47H.

Note:

For automotive applications refer to the Infineon automotive microcontrollers.

Table 56. Quality Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Operation lifetime	tOP CC	20	–	–	a	TJ ≤ 109°C, device permanent on
ESD susceptibility according to Human Body Model (HBM)	VHBM SR	–	–	2000	V	EIA/JESD22-A114-B
ESD susceptibility according to Charged Device Model (CDM)	VCDM SR	–	–	500	V	Conforming to JESD22-C101-C
Moisture sensitivity level	MSL CC	–	–	3	–	JEDEC J-STD-020D
Soldering temperature	TSDR SR	–	–	260	°C	Profile according to JEDEC J-STD-020D

Revision history

Document revision	Date	Description of changes
V1.5	2023-04-01	Table 55 Deleted package details: PG-LQFP-64-19 and PG-VQFN-48-53. Added package details: PG-TQFP-64-21. Package Outlines Deleted Table 56 and 57. Figure 37 Added package diagram: PG-TQFP-64-21. Deleted package diagram: PG-LQFP-64-19.
V1.6	2024-11-28	Template update; no content update

1

x is a placeholder for the supported temperature range.

2

y is a placeholder for the QFP package variant, LQFP or TQFP depending on the stepping, see

Section 1.3

.

3

x is a placeholder for the supported temperature range.

4

x is a placeholder for the supported temperature range.

5

Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port I/O Function table.

6

The port groups are defined in

Table 18

.

7

The port groups are defined in

Table 18

.

8

See also the Supply Monitoring thresholds,

Section 3.3.2

.

9

Voltage overshoot to 4.0 V is permissible at Power-Up and

$\stackrel{<p>¯</p>}{\mathrm{<p>P</p>}\mathrm{<p>O</p>}\mathrm{<p>R</p>}\mathrm{<p>S</p>}\mathrm{<p>T</p>}}$

low, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h over lifetime.

10

Different limits apply for LPAC operation,

Section 3.2.6

.

11

To start the hibernate domain it is required that V_BAT ≥ 2.1 V, for a reliable start of the oscillation of RTC_XTAL in crystal mode it is required that V_BAT ≥ 3.0 V.

12

The port groups are defined in

Table 18

.

13

Current required to override the pull device with the opposite logic level (“force current”). With active pull device, at load currents between force and keep current the input state is undefined.

14

Load current at which the pull device still maintains the valid logic level (“keep current”). With active pull device, at load currents between force and keep current the input state is undefined.

15

Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not be guaranteed that it suppresses switching due to external system noise.

16

POD = Pin Out Driver

17

POD = Pin Out Driver

18

Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not be guaranteed that it suppresses switching due to external system noise.

19

Applies to AINx, when used as alternate reference input.

20

A running conversion may become imprecise in case the normal conditions are violated (voltage overshoot).

21

If the analog reference voltage is below V_DDA , then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE, DNL, INL, Gain, and Offset errors increase also by the factor 1/k.

22

The leakage current definition is a continuous function, as shown in figure ADCx Analog Inputs Leakage. The numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function (see

Figure 14

).

23

The sampling capacity of the conversion C-network is pre-charged to V_AREF /2 before the sampling moment. Because of the parasitic elements, the voltage measured at AINx can deviate from V_AREF /2.

24

This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead, smaller capacitances are successively switched to the reference voltage.

25

For 10-bit conversions, the errors are reduced to 1/4; for 8-bit conversions, the errors are reduced to 1/16. Never less than ±1 LSB.

26

The sum of DNL/INL/GAIN/OFF errors does not exceed the related total unadjusted error TUE.

27

This parameter is valid for soldered devices and requires careful analog board design.

28

Resulting worst case combined error is arithmetic combination of TUE and EN_RMS .

29

Value is defined for one sigma Gauss distribution.

30

The resulting current for a conversion can be calculated with I_AREF = Q_CONV / t_c.

The fastest 12-bit post-calibrated conversion of t_c = 566 ns results in a typical average current of I_AREF = 53 μA.

31

According to best straight line method.

32

Always the standard VADC reference, alternate references do not apply to the ORC.

33

The step size for clock frequencies equal to 180, 120 and 80 MHz is 150 ps.

34

The step size for clock frequencies different from 180, 120 and 80 MHz but within the range from 180 to 64 MHz can be between 118 to 180 ps (fixed over process and operating conditions)

35

Typical input resistance R_CIN = 100 kOhm.

36

The INL error increases for DAC output voltages below this limit.

37

50% duty cycle is not obligatory

38

Only valid if the signal was not previously synchronized/generated with the fccu clock (or a synchronous clock)

39

50% duty cycle is not obligatory

40

Only valid if the signal was not previously synchronized/generated with the fccu clock (or a synchronous clock)

41

Single channel conversion, measuring V_BAT = 3.3 V, 8 cycles settling time

42

At V_{DDP_max} = 3.63 V the typical offset error increases by an additional ΔT_OE = ±1°C.

43

Measured at A-connector with 1.5 kOhm ± 5% to 3.3 V ± 0.3 V connected to USB_DP or USB_DM and at B-connector with 15 kOhm ± 5% to ground connected to USB_DP and USB_DM.

44

t_OSCS is defined from the moment the oscillator is enabled with SCU_OSCHPCTRL.MODE until the oscillations reach an amplitude at XTAL1 of 0.4 * V_DDP .

45

The external oscillator circuitry must be optimized by the customer and checked for negative resistance and amplitude as recommended and specified by crystal suppliers.

46

If the shaper unit is enabled and not bypassed.

47

If the shaper unit is bypassed, dedicated DC-thresholds have to be met.

48

t_OSCS is defined from the moment the oscillator is enabled by the user with SCU_OSCULCTRL.MODE until the oscillations reach an amplitude at RTC_XTAL1 of 400 mV.

49

The external oscillator circuitry must be optimized by the customer and checked for negative resistance and amplitude as recommended and specified by crystal suppliers.

50

For a reliable start of the oscillation in crystal mode it is required that V_BAT ≥ 3.0 V. A running oscillation is maintained across the full V_BAT voltage range.

51

If the shaper unit is enabled and not bypassed.

52

If the shaper unit is bypassed, dedicated DC-thresholds have to be met.

53

Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not be guaranteed that it suppresses switching due to external system noise.

54

CPU executing code from Flash, all peripherals idle.

55

CPU executing code from Flash. USB and CCU clock off.

56

CPU in sleep, all peripherals idle, Flash in Active mode.

57

CPU in sleep, Flash in Active mode.

58

CPU in sleep, peripherals disabled, after wake-up code execution from RAM.

59

To wake-up the Flash from its Sleep mode, f_CPU ≥ 1 MHz is required.

60

OSC_ULP operating with external crystal on RTC_XTAL.

61

OSC_ULP off, Hibernate domain operating with OSC_SI clock.

62

Test Power Loop: f_SYS = 80 MHz, CPU executing benchmark code from Flash, all CCUs in 100 kHz timer mode, all ADC groups in continuous conversion mode, USICs as SPI in internal loop-back mode, CAN in 500 kHz internal loop-back mode, interrupt triggered DMA block transfers to parity protected RAMs and FCE, DTS measurements and FPU calculations.

The power consumption of each customer application will most probably be lower than this value, but must be evaluated separately.

63

I_DDP decreases typically by 3.5 mA when f_SYS decreases by 10 MHz, at constant T_J .

64

Sum of currents of all active converters (ADC and DAC).

65

Enabling the f_CCU clock for the POSIFx/CCU4x/CCU8x modules adds approximately I_PER = 1.8 mA, disregarding which and how many of those peripherals are enabled.

66

The current consumption of the analog components are given in the dedicated Datasheet sections of the respective peripheral.

67

In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes an additional time of 5.5 ms.

68

The following formula applies to the wait state configuration: FCON.WSPFLASH × (1/ f_CPU ) ≥ t_a

69

Storage and inactive time included.

70

Values given are valid for an average weighted junction temperature of T_J = 110°C.

71

Only valid with robust EEPROM emulation algorithm, equally cycling the logical sectors. For more details see the Reference Manual.

72

Minimum threshold for reset assertion.

73

Maximum threshold for reset deassertion.

74

The V_DDP monitoring has a typical hysteresis of V_PORHYS = 180 mV.

75

50% for even K2 divider values, 50±(10/K2) for odd K2 divider values.

76

Error in addition to the accuracy of the reference clock.

77

Automatic calibration compensates variations of the temperature and in the V_DDP supply voltage.

78

Deviations from the nominal V_DDP voltage induce an additional error to the uncalibrated and/or factory calibrated oscillator frequency.

79

The falling edge on TCK is used to generate the TDO timing.

80

The setup time for TDO is given implicitly by the TCK cycle time.

81

t_SYS = 1/ f_PB

82

These input timing are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0).

83

Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximately 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

84

Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximately 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

85

C_b refers to the total capacitance of one bus line in pF.

86

Device mounted on a 4-layer JEDEC board (JESD 51-7) with thermal vias; exposed pad soldered.