XMC4400

XMC4000 Family

Microcontroller Series for Industrial Applications

ARM® Cortex®-M4

32-bit processor core

Datasheet

About this Document

This datasheet is addressed to embedded hardware and software developers. It provides the reader with detailed descriptions about the ordering designations, available features, electrical and physical characteristics of the XMC4400 series devices.

The document describes the characteristics of a superset of the XMC4400 series devices. For simplicity, the various device types are referred to by the collective term XMC4400 throughout this manual.

XMC4000 Family User Documentation

The set of user documentation includes:

• Reference Manual

  • describes the functionality of the superset of devices.

• Datasheets

  • list the complete ordering designations, available features and electrical characteristics of derivative devices.

• Errata Sheets

  • list deviations from the specifications given in the related Reference Manual or Datasheets. Errata Sheets are provided for the superset of devices.

Attention:
Please consult all parts of the documentation set to attain consolidated knowledge about your device.

Application related guidance is provided by Users Guides and Application Notes .

Please refer to

http://www.infineon.com/xmc4000

to get access to the latest versions of those documents.

Summary of Features

The XMC4400 devices are members of the XMC4000 Family of microcontrollers based on the ARM Cortex-M4 processor core. The XMC4000 is a family of high performance and energy efficient microcontrollers optimized for Industrial Connectivity, Industrial Control, Power Conversion, Sense & Control.

Figure 1. XMC4400 System Block Diagram

CPU Subsystem

• CPU Core

  • High Performance 32-bit ARM Cortex-M4 CPU

  • 16-bit and 32-bit Thumb2 instruction set

  • DSP/MAC instructions

  • System timer (SysTick) for Operating System support

• Floating Point Unit

• Memory Protection Unit

• Nested Vectored Interrupt Controller

• One General Purpose DMA with up-to 8 channels

• Event Request Unit (ERU) for programmable processing of external and internal service requests

• Flexible CRC Engine (FCE) for multiple bit error detection

On-Chip Memories

• 16 KB on-chip boot ROM

• 16 KB on-chip high-speed program memory

• 32 KB on-chip high speed data memory

• 32 KB on-chip high-speed communication memory

• 512 KB on-chip Flash Memory with 4 KB instruction cache

Communication Peripherals

• Ethernet MAC module capable of 10/100 Mbit/s transfer rates

• Universal Serial Bus, USB 2.0 host, Full-Speed OTG, with integrated PHY

• Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with two nodes, 64 message objects (MO), data rate up to 1MBit/s

• Four Universal Serial Interface Channels (USIC), providing four serial channels, usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces

• LED and Touch-Sense Controller (LEDTS) for Human-Machine interface

Analog Frontend Peripherals

• Four Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with input out-of-range comparators

• Delta Sigma Demodulator with four channels, digital input stage for A/D signal conversion

• Digital-Analog Converter (DAC) with two channels of 12-bit resolution

Industrial Control Peripherals

• Two Capture/Compare Units 8 (CCU8) for motor control and power conversion

• Four Capture/Compare Units 4 (CCU4) for use as general purpose timers

• Four High Resolution PWM (HRPWM) channels

• Two Position Interfaces (POSIF) for servo motor positioning

• Window Watchdog Timer (WDT) for safety sensitive applications

• Die Temperature Sensor (DTS)

• Real Time Clock module with alarm support

• System Control Unit (SCU) for system configuration and control

Input/Output Lines

• Programmable port driver control module (PORTS)

• Individual bit addressability

• Tri-stated in input mode

• Push/pull or open drain output mode

• Boundary scan test support over JTAG interface

On-Chip Debug Support

• Full support for debug features: 8 breakpoints, CoreSight, trace

• Various interfaces: ARM-JTAG, SWD, single wire trace

Ordering Information

The ordering code for an Infineon microcontroller provides an exact reference to a specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies:

• <DDD> the derivatives function set

• <Z> the package variant

  • E: LFBGA

  • F: LQFP

  • Q: VQFN

• <PPP> package pin count

• <T> the temperature range:

  • F: -40°C to 85°C

  • K: -40°C to 125°C

• <FFFF> the Flash memory size.

For ordering codes for the XMC4400 please contact your sales representative or local distributor.

This document describes several derivatives of the XMC4400 series, some descriptions may not apply to a specific product. Please see

Table 1

.

For simplicity the term XMC4400 is used for all derivatives throughout this document.

Device Types

These device types are available and can be ordered through Infineon’s direct and/or distribution channels.

Table 1.Synopsis of XMC4400 Device Types

Derivative 1	Package	Flash Kbytes	SRAM Kbytes
XMC4400-F100x512	PG-LQFP-100	512	80
XMC4400-F64x512	PG-TQFP-64	512	80
XMC4400-F100x256	PG-LQFP-100	256	80
XMC4400-F64x256	PG-TQFP-64	256	80
XMC4402-F100x256	PG-LQFP-100	256	80
XMC4402-F64x256	PG-TQFP-64	256	80

Package Variants

Different markings of the XMC4400 use different package variants. Details of those packages are given in the

Package Parameters

section of the datasheet.

Table 2.XMC4400 Package Variants

Package Variant	Package
XMC4400-F100	PG-LQFP-100-25 PG-LQFP-100-29
XMC4400-F64	PG-TQFP-64-19 PG-TQFP-64-21

Device Type Features

The following table lists the available features per device type.

Table 3.Features of XMC4400 Device Types

Derivative 2	LEDTS Intf.	ETH Intf.	USB Intf.	USIC Chan.	MultiCAN Nodes, MO
XMC4400-F100x512	1	RMII	1	2 x 2	N0, N1 MO[0..63]
XMC4400-F64x512	1	RMII	1	2 x 2	N0, N1 MO[0..63]
XMC4400-F100x256	1	RMII	1	2 x 2	N0, N1 MO[0..63]
XMC4400-F64x256	1	RMII	1	2 x 2	N0, N1 MO[0..63]
XMC4402-F100x256	1	–	1	2 x 2	N0, N1 MO[0..63]
XMC4402-F64x256	1	–	1	2 x 2	N0, N1 MO[0..63]

Table 4.Features of XMC4400 Device Types

Derivative 3	ADC Chan.	DSD Chan.	DAC Chan.	CCU4 Slice	CCU8 Slice	POSIF Intf.	HRPWM Intf.
XMC4400-F100x512	24	4	2	4 x 4	2 x 4	2	1
XMC4400-F64x512	14	4	2	4 x 4	2 x 4	2	1
XMC4400-F100x256	24	4	2	4 x 4	2 x 4	2	1
XMC4400-F64x256	14	4	2	4 x 4	2 x 4	2	1
XMC4402-F100x256	24	4	2	4 x 4	2 x 4	2	1
XMC4402-F64x256	14	4	2	4 x 4	2 x 4	2	1

Definition of Feature Variants

The XMC4400 types are offered with several memory sizes and number of available VADC channels.

Table 5

describes the location of the available Flash memory,

Table 6

describes the location of the available SRAMs,

Table 7

the available VADC channels.

Table 5.Flash Memory Ranges

Total Flash Size	Cached Range	Uncached Range
256 Kbytes	0800 0000 – 0803 FFFF	0C00 0000 – 0C03 FFFF
512 Kbytes	0800 0000 – 0807 FFFF	0C00 0000 – 0C07 FFFF

Table 6.SRAM Memory Ranges

Total SRAM Size	Program SRAM	System Data SRAM	Communication Data SRAM
80 Kbytes	1FFF C000 – 1FFF FFFF	2000 0000 – 2000 7FFF	2000 8000 – 2000 FFFF

Table 7.ADC Channels ⁴

Package	VADC G0	VADC G1	VADC G2	VADC G3
PG-LQFP-100	CH0..CH7	CH0..CH7	CH0..CH3	CH0..CH3
PG-TQFP-64	CH0, CH3..CH7	CH0, CH1, CH3, CH6	CH0, CH1	CH2, CH3

Identification Registers

The identification registers allow software to identify the marking.

Table 8.XMC4400 Identification Registers

Register Name	Value	Marking
SCU_IDCHIP	0004 4001	EES-AA, ES-AA
SCU_IDCHIP	0004 4002	ES-AB, AB
SCU_IDCHIP	0004 4003	BA
JTAG IDCODE	101D C083	EES-AA, ES-AA
JTAG IDCODE	201D C083	ES-AB, AB
JTAG IDCODE	301D C083	BA

General Device Information

This section summarizes the logic symbols and package pin configurations with a detailed list of the functional I/O mapping.

Logic Symbols

Figure 2. XMC4400 Logic Symbol PG-LQFP-100

Figure 3. XMC4400 Logic Symbol PG-TQFP-64

Pin Configuration and Definition

The following figures summarize all pins, showing their locations on the different packages.

Figure 4. XMC4400 PG-LQFP-100 Pin Configuration (top view)

Figure 5. XMC4400 PG-TQFP-64 Pin Configuration (top view)

Package Pin Summary

The following general scheme is used to describe each pin.

Table 9.Package Pin Mapping Description

Function	Package A	Package B	...	Pad Type	Notes
Name	N	Ax	...	A2

The table is sorted by the “Function” column, starting with the regular Port pins (Px.y), followed by the dedicated pins (i.e. $\overline{PORST}$ ) and supply pins.

The following columns, titled with the supported package variants, lists the package pin number to which the respective function is mapped in that package.

The “Pad Type” indicates the employed pad type (A1, A1+, A2, special=special pad, In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about the pad properties are defined in the Electrical Parameters.

In the “Notes”, special information to the respective pin/function is given, i.e. deviations from the default configuration after reset. Per default the regular Port pins are configured as direct input with no internal pull device active.

Table 10.Package Pin Mapping

Function	LQFP-100	TQFP-64	Pad Type	Notes
P0.0	2	2	A1+
P0.1	1	1	A1+
P0.2	100	64	A2
P0.3	99	63	A2
P0.4	98	62	A2
P0.5	97	61	A2
P0.6	96	60	A2
P0.7	89	58	A2	After a system reset, via HWSEL this pin selects the DB.TDI function.
P0.8	88	57	A2	After a system reset, via HWSEL this pin selects the $\overline{DB\mathrm{.}TRST}$ function, with a weak pull-down active.
P0.9	4	4	A2
P0.10	3	3	A1+
P0.11	95	59	A1+
P0.12	94	–	A1+
P1.0	79	52	A1+
P1.1	78	51	A1+
P1.2	77	50	A2
P1.3	76	49	A2
P1.4	75	48	A1+
P1.5	74	47	A1+
P1.6	83	–	A2
P1.7	82	–	A2
P1.8	81	54	A2
P1.9	80	53	A2
P1.10	73	–	A1+
P1.11	72	–	A1+
P1.12	71	–	A2
P1.13	70	–	A2
P1.14	69	–	A2
P1.15	68	46	A2
P2.0	52	34	A2
P2.1	51	33	A2	After a system reset, via HWSEL this pin selects the DB.TDO function.
P2.2	50	32	A2
P2.3	49	31	A2
P2.4	48	30	A2
P2.5	47	29	A2
P2.6	54	36	A1+
P2.7	53	35	A1+
P2.8	46	28	A2
P2.9	45	27	A2
P2.10	44	–	A2
P2.14	41	–	A2
P2.15	40	–	A2
P3.0	7	–	A2
P3.1	6	–	A2
P3.2	5	–	A2
P3.3	93	–	A1+
P3.4	92	–	A1+
P3.5	91	–	A2
P3.6	90	–	A2
P4.0	85	–	A2
P4.1	84	–	A2
P5.0	58	–	A1+
P5.1	57	–	A1+
P5.2	56	–	A1+
P5.7	55	–	A1+
P14.0	31	20	AN/DIG_IN
P14.1	30	–	AN/DIG_IN
P14.2	29	–	AN/DIG_IN
P14.3	28	19	AN/DIG_IN
P14.4	27	18	AN/DIG_IN
P14.5	26	17	AN/DIG_IN
P14.6	25	16	AN/DIG_IN
P14.7	24	15	AN/DIG_IN
P14.8	37	24	AN/DAC/DIG_IN
P14.9	36	23	AN/DAC/DIG_IN
P14.12	23	–	AN/DIG_IN
P14.13	22	–	AN/DIG_IN
P14.14	21	14	AN/DIG_IN
P14.15	20	–	AN/DIG_IN
P15.2	19	–	AN/DIG_IN
P15.3	18	–	AN/DIG_IN
P15.8	39	–	AN/DIG_IN
P15.9	38	–	AN/DIG_IN
USB_DP	9	6	special
USB_DM	8	5	special
HIB_IO_0	14	10	A1 special	At the first power-up and with every reset of the hibernate domain this pin is configured as open-drain output and drives "0". As output the medium driver mode is active.
HIB_IO_1	13	–	A1 special	At the first power-up and with every reset of the hibernate domain this pin is configured as input with no pull device active. As output the medium driver mode is active.
TCK	67	45	A1	Weak pull-down active.
TMS	66	44	A1+	Weak pull-up active. As output the strong-soft driver mode is active.
$\overline{PORST}$	65	43	special	Strong pull-down controlled by EVR. Weak pull-up active while strong pull-down is not active.
XTAL1	61	39	clock_IN
XTAL2	62	40	clock_O
RTC_XTAL1	15	11	clock_IN
RTC_XTAL2	16	12	clock_O
VBAT	17	13	Power	When VDDP is supplied VBAT has to be supplied as well.
VBUS	10	7	special
VAREF	33	–	AN_Ref
VAGND	32	–	AN_Ref
VDDA	35	–	AN_Power
VDDA/VAREF	–	22	AN_Power/AN_Ref	Shared analog supply and reference voltage pin.
VSSA	34	–	AN_Power
VSSA/VAGND	–	21	AN_Power/AN_Ref	Shared analog supply and reference ground pin.
VDDC	12	9	Power
VDDC	42	25	Power
VDDC	64	42	Power
VDDC	86	55	Power
VDDP	11	8	Power
VDDP	43	26	Power
VDDP	60	38	Power
VDDP	87	56	Power
VSS	59	37	Power
VSSO	63	41	Power
VSS	Exp. Pad	Exp. Pad	Power	Exposed Die Pad The exposed die pad is connected internally to VSS. For proper operation, it is mandatory to connect the exposed pad directly to the common ground on the board. For thermal aspects, please refer to the Datasheet. Board layout examples are given in an application note.

Port I/O Functions

The following general scheme is used to describe each PORT pin:

Table 11.Port I/O Function Description

Function	Outputs			Inputs
	ALT1	ALTn	HWO0	HWI0	Input	Input
P0.0		MODA.OUT	MODB.OUT	MODB.INA	MODC.INA
Pn.y	MODA.OUT				MODA.INA	MODC.INB

Figure 6. Simplified Port Structure

Pn.y is the port pin name, defining the control and data bits/registers associated with it. As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT defines the output value.

Up to four alternate output functions (ALT1/2/3/4) can be mapped to a single port pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective module, with the pin characteristics controlled by the port registers (within the limits of the connected pad).

The port pin input can be connected to multiple peripherals. Most peripherals have an input multiplexer to select between different possible input sources.

The input path is also active while the pin is configured as output. This allows to feedback an output to on-chip resources without wasting an additional external pin.

By Pn_HWSEL it is possible to select between different hardware “masters” (HWO0/HWI0). The selected peripheral can take control of the pin(s). Hardware control overrules settings in the respective port pin registers.

Port I/O Function Table

Table 12.Port I/O Functions

Function	Output					Input
	ALT1	ALT2	ALT3	ALT4	HWO0	HWI0	Input	Input	Input	Input	Input	Input	Input	Input
P0.0		CAN.N0_TXD	CCU80.OUT21	LEDTS0.COL2			U1C1.DX0D	ETH0.CLK_RMIIB	ERU0.0B0			HRPWM0.C1INB		ETH0.CLKRXB
P0.1	USB.DRIVEVBUS	U1C1.DOUT0	CCU80.OUT11	LEDTS0.COL3				ETH0.CRS_DVB	ERU0.0A0			HRPWM0.C2INB		ETH0.RXDVB
P0.2		U1C1.SELO1	CCU80.OUT01	HRPWM0.HROUT01	U1C0.DOUT3	U1C0.HWIN3	ETH0.RXD0B		ERU0.3B3
P0.3			CCU80.OUT20	HRPWM0.HROUT20	U1C0.DOUT2	U1C0.HWIN2	ETH0.RXD1B			ERU1.3B0
P0.4	ETH0.TX_EN		CCU80.OUT10	HRPWM0.HROUT21	U1C0.DOUT1	U1C0.HWIN1		U1C0.DX0A	ERU0.2B3
P0.5	ETH0.TXD0	U1C0.DOUT0	CCU80.OUT00	HRPWM0.HROUT00	U1C0.DOUT0	U1C0.HWIN0		U1C0.DX0B		ERU1.3A0
P0.6	ETH0.TXD1	U1C0.SELO0	CCU80.OUT30	HRPWM0.HROUT30				U1C0.DX2A	ERU0.3B2		CCU80.IN2B
P0.7	WWDT.SERVICE_OUT	U0C0.SELO0		HRPWM0.HROUT11		DB.TDI	U0C0.DX2B	DSD.DIN1A	ERU0.2B1		CCU80.IN0A	CCU80.IN1A	CCU80.IN2A	CCU80.IN3A
P0.8	SCU.EXTCLK	U0C0.SCLKOUT		HRPWM0.HROUT10		$\overline{DB\mathrm{.}TRST}$	U0C0.DX1B	DSD.DIN0A	ERU0.2A1		CCU80.IN1B
P0.9	HRPWM0.HROUT31	U1C1.SELO0	CCU80.OUT12	LEDTS0.COL0	ETH0.MDO	ETH0.MDIA	U1C1.DX2A	USB.ID	ERU0.1B0
P0.10	ETH0.MDC	U1C1.SCLKOUT	CCU80.OUT02	LEDTS0.COL1			U1C1.DX1A		ERU0.1A0
P0.11		U1C0.SCLKOUT	CCU80.OUT31				ETH0.RXERB	U1C0.DX1A	ERU0.3A2
P0.12		U1C1.SELO0	CCU40.OUT3					U1C1.DX2B	ERU0.2B2
P1.0	DSD.CGPWMN	U0C0.SELO0	CCU40.OUT3	ERU1.PDOUT3			U0C0.DX2A		ERU0.3B0		CCU40.IN3A	HRPWM0.C0INA
P1.1	DSD.CGPWMP	U0C0.SCLKOUT	CCU40.OUT2	ERU1.PDOUT2			U0C0.DX1A	POSIF0.IN2A	ERU0.3A0		CCU40.IN2A	HRPWM0.C1INA
P1.2			CCU40.OUT1	ERU1.PDOUT1	U0C0.DOUT3	U0C0.HWIN3		POSIF0.IN1A		ERU1.2B0	CCU40.IN1A	HRPWM0.C2INA
P1.3		U0C0.MCLKOUT	CCU40.OUT0	ERU1.PDOUT0	U0C0.DOUT2	U0C0.HWIN2		POSIF0.IN0A		ERU1.2A0	CCU40.IN0A	HRPWM0.C0INB
P1.4	WWDT.SERVICE_OUT	CAN.N0_TXD	CCU80.OUT33	CCU81.OUT20	U0C0.DOUT1	U0C0.HWIN1	U0C0.DX0B	CAN.N1_RXDD	ERU0.2B0		CCU41.IN0C	HRPWM0.BL0A
P1.5	CAN.N1_TXD	U0C0.DOUT0	CCU80.OUT23	CCU81.OUT10	U0C0.DOUT0	U0C0.HWIN0	U0C0.DX0A	CAN.N0_RXDA	ERU0.2A0	ERU1.0A0	CCU41.IN1C	DSD.DIN2B
P1.6		U0C0.SCLKOUT					DSD.DIN2A
P1.7		U0C0.DOUT0	DSD.MCLK2	U1C1.SELO2				DSD.MCLK2A			DSD.MCLK0C
P1.8		U0C0.SELO1	DSD.MCLK1	U1C1.SCLKOUT				DSD.MCLK1A			DSD.MCLK0D	DSD.MCLK2D	DSD.MCLK3D
P1.9	U0C0.SCLKOUT		DSD.MCLK0	U1C1.DOUT0				DSD.MCLK0A			DSD.MCLK1C	DSD.MCLK2C	DSD.MCLK3C
P1.10	ETH0.MDC	U0C0.SCLKOUT	CCU81.OUT21								CCU41.IN2C
P1.11		U0C0.SELO0	CCU81.OUT11		ETH0.MDO	ETH0.MDIC					CCU41.IN3C
P1.12	ETH0.TX_EN	CAN.N1_TXD	CCU81.OUT01
P1.13	ETH0.TXD0	U0C1.SELO3	CCU81.OUT20				CAN.N1_RXDC
P1.14	ETH0.TXD1	U0C1.SELO2	CCU81.OUT10
P1.15	SCU.EXTCLK	DSD.MCLK2	CCU81.OUT00	U1C0.DOUT0	DB.ETM_TRACEDATA3			DSD.MCLK2B		ERU1.1A0
P2.0	CAN.N0_TXD	CCU81.OUT21	DSD.CGPWMN	LEDTS0.COL1	ETH0.MDO	ETH0.MDIB			ERU0.0B3		CCU40.IN1C
P2.1		CCU81.OUT11	DSD.CGPWMP	LEDTS0.COL0	DB.TDO/TRACESWO		ETH0.CLK_RMIIA			ERU1.0B0	CCU40.IN0C			ETH0.CLKRXA
P2.2	VADC.EMUX00	CCU81.OUT01	CCU41.OUT3	LEDTS0.LINE0	LEDTS0.EXTENDED0	LEDTS0.TSIN0A	ETH0.RXD0A	U0C1.DX0A	ERU0.1B2		CCU41.IN3A
P2.3	VADC.EMUX01	U0C1.SELO0	CCU41.OUT2	LEDTS0.LINE1	LEDTS0.EXTENDED1	LEDTS0.TSIN1A	ETH0.RXD1A	U0C1.DX2A	ERU0.1A2	POSIF1.IN2A	CCU41.IN2A
P2.4	VADC.EMUX02	U0C1.SCLKOUT	CCU41.OUT1	LEDTS0.LINE2	LEDTS0.EXTENDED2	LEDTS0.TSIN2A	ETH0.RXERA	U0C1.DX1A	ERU0.0B2	POSIF1.IN1A	CCU41.IN1A	HRPWM0.BL1A
P2.5	ETH0.TX_EN	U0C1.DOUT0	CCU41.OUT0	LEDTS0.LINE3	LEDTS0.EXTENDED3	LEDTS0.TSIN3A	ETH0.RXDVA	U0C1.DX0B	ERU0.0A2	POSIF1.IN0A	CCU41.IN0A	HRPWM0.BL2A		ETH0.CRS_DVA
P2.6			CCU80.OUT13	LEDTS0.COL3			DSD.DIN1B	CAN.N1_RXDA	ERU0.1B3		CCU40.IN3C
P2.7	ETH0.MDC	CAN.N1_TXD	CCU80.OUT03	LEDTS0.COL2			DSD.DIN0B			ERU1.1B0	CCU40.IN2C
P2.8	ETH0.TXD0		CCU80.OUT32	LEDTS0.LINE4	LEDTS0.EXTENDED4	LEDTS0.TSIN4A	DAC.TRIGGER5				CCU40.IN0B	CCU40.IN1B	CCU40.IN2B	CCU40.IN3B
P2.9	ETH0.TXD1		CCU80.OUT22	LEDTS0.LINE5	LEDTS0.EXTENDED5	LEDTS0.TSIN5A	DAC.TRIGGER4				CCU41.IN0B	CCU41.IN1B	CCU41.IN2B	CCU41.IN3B
P2.10	VADC.EMUX10
P2.14	VADC.EMUX11	U1C0.DOUT0	CCU80.OUT21		DB.ETM_TRACECLK			U1C0.DX0D			CCU43.IN0B	CCU43.IN1B	CCU43.IN2B	CCU43.IN3B
P2.15	VADC.EMUX12		CCU80.OUT11	LEDTS0.LINE6	LEDTS0.EXTENDED6	LEDTS0.TSIN6A	ETH0.COLA	U1C0.DX0C			CCU42.IN0B	CCU42.IN1B	CCU42.IN2B	CCU42.IN3B
P3.0		U0C1.SCLKOUT	CCU42.OUT0				U0C1.DX1B				CCU80.IN2C	CCU81.IN0C
P3.1		U0C1.SELO0					U0C1.DX2B		ERU0.0B1		CCU80.IN1C
P3.2	USB.DRIVEVBUS	CAN.N0_TXD		LEDTS0.COLA					ERU0.0A1		CCU80.IN0C
P3.3		U1C1.SELO1	CCU42.OUT3					DSD.DIN3B			CCU42.IN3A	CCU80.IN3B
P3.4		U1C1.SELO2	CCU42.OUT2	DSD.MCLK3				DSD.MCLK3B			CCU42.IN2A	CCU80.IN0B
P3.5		U1C1.SELO3	CCU42.OUT1	U0C1.DOUT0					ERU0.3B1		CCU42.IN1A
P3.6		U1C1.SELO4	CCU42.OUT0	U0C1.SCLKOUT	DB.ETM_TRACEDATA0				ERU0.3A1		CCU42.IN0A
P4.0			DSD.MCLK1		DB.ETM_TRACEDATA1		U1C1.DX1C	DSD.MCLK1B	U0C1.DX0E
P4.1		U1C1.MCLKOUT	DSD.MCLK0	U0C1.SELO0	DB.ETM_TRACEDATA2			DSD.MCLK0B			DSD.MCLK1D
P5.0		DSD.CGPWMN	CCU81.OUT33					ETH0.RXD0D	U0C0.DX0D		CCU81.IN0A	CCU81.IN1A	CCU81.IN2A	CCU81.IN3A
P5.1	U0C0.DOUT0	DSD.CGPWMP	CCU81.OUT32					ETH0.RXD1D			CCU81.IN0B
P5.2			CCU81.OUT23					ETH0.CRS_DVD			CCU81.IN1B			ETH0.RXDVD
P5.7			CCU81.OUT02	LEDTS0.COLA
P14.0							VADC.G0CH0
P14.1							VADC.G0CH1
P14.2							VADC.G0CH2	VADC.G1CH2
P14.3							VADC.G0CH3	VADC.G1CH3			CAN.N0_RXDB
P14.4							VADC.G0CH4		VADC.G2CH0
P14.5							VADC.G0CH5		VADC.G2CH1		POSIF0.IN2B
P14.6							VADC.G0CH6				POSIF0.IN1B		G0ORC6
P14.7							VADC.G0CH7				POSIF0.IN0B		G0ORC7
P14.8					DAC.OUT_0			VADC.G1CH0		VADC.G3CH2	ETH0.RXD0C
P14.9					DAC.OUT_1			VADC.G1CH1		VADC.G3CH3	ETH0.RXD1C
P14.12								VADC.G1CH4
P14.13								VADC.G1CH5
P14.14								VADC.G1CH6					G1ORC6
P14.15								VADC.G1CH7					G1ORC7
P15.2									VADC.G2CH2
P15.3									VADC.G2CH3
P15.8										VADC.G3CH0	ETH0.CLK_RMIIC			ETH0.CLKRXC
P15.9										VADC.G3CH1	ETH0.CRS_DVC			ETH0.RXDVC
USB_DP
USB_DM
HIB_IO_0	HIBOUT	WWDT.SERVICE_OUT					WAKEUPA
HIB_IO_1	HIBOUT	WWDT.SERVICE_OUT					WAKEUPB
TCK						DB.TCK/SWCLK
TMS					DB.TMS/SWDIO
$\overline{PORST}$
XTAL1							U0C0.DX0F	U0C1.DX0F	U1C0.DX0F	U1C1.DX0F
XTAL2
RTC_XTAL1									ERU0.1B1
RTC_XTAL2

Power Connection Scheme

Figure 7

shows a reference power connection scheme for the XMC4400.

Figure 7. Power Connection Scheme

Every power supply pin needs to be connected. Different pins of the same supply need also to be externally connected. As example, all V _DDP pins must be connected externally to one V _DDP net. In this reference scheme one 100 nF capacitor is connected at each supply pin against V _SS . An additional 10 µF capacitor is connected to the V _DDP nets and an additional 4.7 uF capacitor to the V _DDC nets.

The XMC4400 has a common ground concept, all V _SS , V _SSA and V _SSO pins share the same ground potential. In packages with an exposed die pad it must be connected to the common ground as well.

V _AGND is the low potential to the analog reference V _AREF . Depending on the application it can share the common ground or have a different potential. In devices with shared V _DDA / V _AREF and V _SSA / V _AGND pins the reference is tied to the supply. Some analog channels can optionally serve as “Alternate Reference”; further details on this operating mode are described in the Reference Manual.

When V _DDP is supplied, V _BAT must be supplied as well. If no other supply source (e.g. battery) is connected to V _BAT , the V _BAT pin can also be connected directly to V _DDP .

Electrical Parameters

General Parameters

Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the XMC4400 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”:

• CC

  Such parameters indicate C ontroller C haracteristics, which are a distinctive feature of the XMC4400 and must be regarded for system design.

• SR

  Such parameters indicate S ystem R equirements, which must be provided by the application system in which the XMC4400 is designed in.

Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Table 13.Absolute Maximum Rating Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Storage temperature	T ST SR	-65	–	150	°C	–
Junction temperature	T J SR	-40	–	150	°C	–
Voltage at 3.3 V power supply pins with respect to V SS	V DDP SR	–	–	4.3	V	–
Voltage on any Class A and dedicated input pin with respect to V SS	V IN SR	-1.0	–	V DDP + 1.0 or max. 4.3	V	whichever is lower
Voltage on any analog input pin with respect to V AGND	V AIN V AREF SR	-1.0	–	V DDP + 1.0 or max. 4.3	V	whichever is lower
Input current on any pin during overload condition	I IN SR	-10	–	+10	mA	–
Absolute maximum sum of all input circuit currents for one port group during overload condition 5	Σ I IN SR	-25	–	+25	mA	–
Absolute maximum sum of all input circuit currents during overload condition	Σ I IN SR	-100	–	+100	mA	–

Figure 8

explains the input voltage ranges of V _IN and V _AIN and its dependency to the supply level of V _DDP . The input voltage must not exceed 4.3 V, and it must not be more than 1.0 V above V _DDP . For the range up to V _DDP

• 1.0 V also see the definition of the overload conditions in

Pin Reliability in Overload

.

Figure 8. Absolute Maximum Input Voltage Ranges

Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification.

Table 14

defines overload conditions that will not cause any negative reliability impact if all the following conditions are met:

• full operation life-time is not exceeded

• Operating Conditions

  are met for

  • pad supply levels ( V _DDP or V _DDA )

  • temperature

If a pin current is outside of the

Operating Conditions

but within the overload parameters, then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters.

Note:
An overload condition on one or more pins does not require a reset.

Note:
A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery.

Table 14.Overload Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Input current on any port pin during overload condition	I OV SR	-5	–	5	mA
Absolute sum of all input circuit currents for one port group during overload condition 6	I OVG SR	–	–	20	mA	Σ| I OVx |, for all I OVx < 0 mA
		–	–	20	mA	Σ| I OVx |, for all I OVx > 0 mA
Absolute sum of all input circuit currents during overload condition	I OVS SR	–	–	80	mA	Σ I OVG

Figure 9

shows the path of the input currents during overload via the ESD protection structures. The diodes against V _DDP and ground are a simplified representation of these ESD protection structures.

Figure 9. Input Overload Current via ESD structures

Table 15

and

Table 16

list input voltages that can be reached under overload conditions. Note that the absolute maximum input voltages as defined in the

Absolute Maximum Ratings

must not be exceeded during overload.

Table 15.PN-Junction Characterisitics for positive Overload

Pad Type	I OV = 5 mA, TJ = -40 °C	I OV = 5 mA, TJ = 150 °C
A1 / A1+	V IN = V DDP + 1.0 V	V IN = V DDP + 0.75 V
A2	V IN = V DDP + 0.7 V	V IN = V DDP + 0.6 V
AN/DIG_IN	V IN = V DDP + 1.0 V	V IN = V DDP + 0.75 V

Table 16.PN-Junction Characterisitics for negative Overload

Pad Type	I OV = 5 mA, TJ = -40 °C	I OV = 5 mA, T J = 150 °C
A1 / A1+	V IN = V SS - 1.0 V	V IN = V SS - 0.75 V
A2	V IN = V SS - 0.7 V	V IN = V SS - 0.6 V
AN/DIG_IN	V IN = V DDP - 1.0 V	V IN = V DDP - 0.75 V

Table 17.Port Groups for Overload and Short-Circuit Current Sum Parameters

Group	Pins
1	P0.[12:0], P3.[6:0]
2	P14.[15:0], P15.[9:2]
3	P2.[15:0], P5.[7:0]
4	P1.[15:0], P4.[1:0]

Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the

Input/Output Pins

.

Table 18.Pad Driver and Pad Classes Overview

Class	Power Supply	Type	Sub-Class	Speed Grade	Load	Termination
A	3.3 V	LVTTL I/O, LVTTL outputs	A1 (e.g. GPIO)	6 MHz	100 pF	No
			A1+ (e.g. serial I/Os)	25 MHz	50 pF	Series termination recommended
			A2 (e.g. ext. Bus)	80 MHz	15 pF	Series termination recommended

Figure 10. Output Slopes with different Pad Driver Modes

Figure 10

is a qualitative display of the resulting output slope performance with different output driver modes. The detailed input and output characteristics are listed in

Input/Output Pins

.

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the XMC4400. All parameters specified in the following tables refer to these operating conditions, unless noted otherwise.

Table 19.Operating Conditions Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Ambient Temperature	T A SR	-40	–	85	°C	Temp. Range F
		-40	–	125	°C	Temp. Range K
Digital supply voltage	V DDP SR	3.13	3.3	3.63	V
Core Supply Voltage	V DDC CC	– 7	1.3	–	V	Generated internally
Digital ground voltage	V SS SR	0	–	–	V
ADC analog supply voltage	V DDA SR	3.0	3.3	3.6 8	V
Analog ground voltage for V DDA	V SSA SR	-0.1	0	0.1	V
Battery Supply Voltage for Hibernate Domain 9	V BAT SR	1.95 10	–	3.63	V	When V DDP is supplied V BAT has to be supplied too.
System Frequency	f SYS SR	–	–	120	MHz
Short circuit current of digital outputs	I SC SR	-5	–	5	mA
Absolute sum of short circuit currents per pin group 11	Σ I SC_PG SR	–	–	20	mA
Absolute sum of short circuit currents of the device	Σ I SC_D SR	–	–	100	mA

DC Parameters

Input/Output Pins

The digital input stage of the shared analog/digital input pins is identical to the input stage of the standard digital input/output pins.

The Pull-up on the $\overline{PORST}$ pin is identical to the Pull-up on the standard digital input/output pins.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 20.Standard Pad Parameters

Parameter	Symbol	Values		Unit	Note / Test Condition
		Min.	Max.
Pin capacitance (digital inputs/outputs)	C IO CC	–	10	pF
Pull-down current	| I PDL | CC	150	–	µA	V IN ≥ 0.6 × V DDP
		–	10	µA	13 V IN ≤ 0.36 × V DDP
Pull-Up current	| I PUH | SR	–	10	µA	12 V IN ≥ 0.6 × V DDP
		100	–	µA	12 V IN ≤ 0.36 × V DDP
Input Hysteresis for pads of all A classes 14	HYSA SR	0.1 × V DDP	–	V
$\overline{PORST}$ spike filter always blocked pulse duration	t SF1 CC	–	10	ns
$\overline{PORST}$ spike filter pass-through pulse duration	t SF2 CC	100	–	ns
$\overline{PORST}$ pull-down current	| I PPD | CC	13	–	mA	V IN = 1.0 V

Figure 11. Pull Device Input Characteristics

Figure 11

visualizes the input characteristics with an active internal pull device:

• in the cases “A” the internal pull device is overridden by a strong external driver;

• in the cases “B” the internal pull device defines the input logical state against a weak external load.

Table 21.Standard Pads Class_A1

Parameter	Symbol	Values		Unit	Note / Test Condition
		Min.	Max.
Input leakage current	I OZA1 CC	-500	500	nA	0 V ≤ V IN ≤ V DDP
Input high voltage	V IHA1 SR	0.6 × V DDP	V DDP + 0.3	V	max. 3.6 V
Input low voltage	V ILA1 SR	-0.3	0.36 × V DDP	V
Output high voltage, POD = weak	V OHA1 CC	V DDP - 0.4	–	V	I OH ≥ -400 μA
		2.4	–	V	I OH ≥ -500 μA
Output high voltage, POD 15 = medium		V DDP - 0.4	–	V	I OH ≥ -1.4 mA
		2.4	–	V	I OH ≥ -2 mA
Output low voltage	V OLA1 CC	–	0.4	V	I OL ≤ 500 μA; POD 15 = weak
		–	0.4	V	I OL ≤ 2 mA; POD 15 = medium
Fall time	t FA1 CC	–	150	ns	C L = 20 pF; POD 15 = weak
		–	50	ns	C L = 50 pF; POD 15 = medium
Rise time	t RA1 CC	–	150	ns	C L = 20 pF; POD 15 = weak
		–	50	ns	C L = 50 pF; POD 15 = medium

Table 22.Standard Pads Class_A1+

Parameter	Symbol	Values		Unit	Note / Test Condition
		Min.	Max.
Input leakage current	I OZA1+ CC	-1	1	µA	0 V ≤ V IN ≤ V DDP
Input high voltage	V IHA1+ SR	0.6 × V DDP	V DDP + 0.3	V	max. 3.6 V
Input low voltage	V ILA1+ SR	-0.3	0.36 × V DDP	V
Output high voltage, POD = weak	V OHA1+ CC	V DDP - 0.4	–	V	I OH ≥ -400 μA
		2.4	–	V	I OH ≥ -500 μA
Output high voltage, POD 16 = medium		V DDP - 0.4	–	V	I OH ≥ -1.4 mA
		2.4	–	V	I OH ≥ -2 mA
Output high voltage, POD 16 = strong		V DDP 0.4	–	V	I OH ≥ -1.4 mA
		2.4	–	V	I OH ≥ -2 mA
Output low voltage	V OLA1+ CC	–	0.4	V	I OL ≤ 500 μA; POD 16 = weak
		–	0.4	V	I OL ≤ 2 mA; POD 16 = medium
		–	0.4	V	I OL ≤ 2 mA; POD 16 = strong
Fall time	t FA1+ CC	–	150	ns	C L = 20 pF; POD 16 = weak
		–	50	ns	C L = 50 pF; POD 16 = medium
		–	28	ns	C L = 50 pF; POD 16 = strong; edge = slow
		–	16	ns	C L = 50 pF; POD 16 = strong; edge = soft;
Rise time	t RA1+ CC	–	150	ns	C L = 20 pF; POD 16 = weak
		–	50	ns	C L = 50 pF; POD 16 = medium
		–	28	ns	C L = 50 pF; POD 16 = strong; edge = slow
		–	16	ns	C L = 50 pF; POD 16 = strong; edge = soft

Table 23.Standard Pads Class_A2

Parameter	Symbol	Values		Unit	Note / Test Condition
		Min.	Max.
Input Leakage current	I OZA2 CC	-6	6	µA	0 V ≤ V IN < 0.5* V DDP - 1 V; 0.5* V DDP + 1 V < V IN ≤ V DDP
		-3	3	µA	0.5* V DDP - 1 V < V IN < 0.5* V DDP + 1 V
Input high voltage	V IHA2 SR	0.6 × V DDP	V DDP + 0.3	V	max. 3.6 V
Input low voltage	V ILA2 SR	-0.3	0.36 × V DDP	V
Output high voltage, POD = weak	V OHA2 CC	V DDP - 0.4	–	V	I OH ≥ -400 μA
		2.4	–	V	I OH ≥ -500 μA
Output high voltage, POD = medium		V DDP - 0.4	–	V	I OH ≥ -1.4 mA
		2.4	–	V	I OH ≥ -2 mA
Output high voltage, POD = strong		V DDP - 0.4	–	V	I OH ≥ -1.4 mA
		2.4	–	V	I OH ≥ -2 mA
Output low voltage, POD = weak	V OLA2 CC	–	0.4	V	I OL ≤ 500 μA
Output low voltage, POD = medium		–	0.4	V	I OL ≤ 2 mA
Output low voltage, POD = strong		–	0.4	V	I OL ≤ 2 mA
Fall time	t FA2 CC	–	150	ns	C L = 20 pF; POD = weak
		–	50	ns	C L = 50 pF; POD = medium
		–	3.7	ns	C L = 50 pF; POD = strong; edge = sharp
		–	7	ns	C L = 50 pF; POD = strong; edge = medium
		–	16	ns	C L = 50 pF; POD = strong; edge = soft
Rise time	t RA2 CC	–	150	ns	C L = 20 pF; POD = weak
		–	50	ns	C L = 50 pF; POD = medium
		–	3.7	ns	C L = 50 pF; POD = strong; edge = sharp
		–	7.0	ns	C L = 50 pF; POD = strong; edge = medium
		–	16	ns	C L = 50 pF; POD = strong; edge = soft

Table 24.HIB_IO Class_A1 special Pads

Parameter	Symbol	Values		Unit	Note / Test Condition
		Min.	Max.
Input leakage current	I OZHIB CC	-500	500	nA	0 V ≤ V IN ≤ V BAT
Input high voltage	V IHHIB SR	0.6 × V BAT	V BAT + 0.3	V	max. 3.6 V
Input low voltage	V ILHIB SR	-0.3	0.36 × V BAT	V
Input Hysteresis for HIB_IO pins	HYSHIB CC	0.1 × V BAT	–	V	V BAT ≥ 3.13 V
		0.06 × V BAT	–	V	V BAT < 3.13 V
Output high voltage, POD 17 = medium	V OHHIB CC	V BAT - 0.4	–	V	I OH ≥ -1.4 mA
Output low voltage	V OLHIB CC	–	0.4	V	I OL ≤ 2 mA
Fall time	t FHIB CC	–	50	ns	V BAT ≥ 3.13 V C L = 50 pF
		–	100	ns	V BAT < 3.13 V C L = 50 pF
Rise time	t RHIB CC	–	50	ns	V BAT ≥ 3.13 V C L = 50 pF
		–	100	ns	V BAT < 3.13 V C L = 50 pF

Analog to Digital Converters (ADCx)

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 25.ADC Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Analog reference voltage	V AREF SR	V AGND + 1	–	V DDA + 0.05 19	V
Analog reference ground 18	V AGND SR	V SSM - 0.05	–	V AREF - 1	V
Analog reference voltage range 18 20	V AREF - V AGND SR	1	–	V DDA + 0.1	V
Analog input voltage	V AIN SR	V AGND	–	V DDA	V
Input leakage at analog inputs 21	I OZ1 CC	-100	–	200	nA	0.03 × V DDA < V AIN < 0.97 × V DDA
		-500	–	100	nA	0 V ≤ V AIN ≤ 0.03 × V DDA
		-100	–	500	nA	0.97 × V DDA ≤ V AIN ≤ V DDA
Input leakage current at VAREF	I OZ2 CC	-1	–	1	µA	0 V ≤ V AREF ≤ V DDA
Input leakage current at VAGND	I OZ3 CC	-1	–	1	µA	0 V ≤ V AGND ≤ V DDA
Internal ADC clock	f ADCI CC	2	–	30	MHz	V DDA = 3.3 V
Switched capacitance at the analog voltage inputs 22	C AINSW CC	–	4	6.5	pF
Total capacitance of an analog input	C AINTOT CC	–	12	20	pF
Switched capacitance at the positive reference voltage input 18 23	C AREFSW CC	–	15	30	pF
Total capacitance of the voltage reference inputs 18	C AREFTOT CC	–	20	40	pF
Total Unadjusted Error	TUE CC	-4	–	4	LSB	12-bit resolution; V DDA = 3.3 V; V AREF = V DDA, dedicated pins for V DDA and V AREF
Differential Non-Linearity Error	EA DNL CC	-3	–	3	LSB
Gain Error 25	EA GAIN CC	-4	–	4	LSB
Integral Non-Linearity 25	EA INL CC	-3	–	3	LSB
Offset Error 25	EA OFF CC	-4	–	4	LSB
Total Unadjusted Error	TUE CC	-6	–	6	LSB	12-bit resolution24; V DDA = 3.3 V; V AREF = V DDA, shared pin for V DDA and V AREF (PG-TQFP-64)
Differential Non-Linearity Error 25	EA DNL CC	-4.5	–	4.5	LSB
Gain Error 25	EA GAIN CC	-6	–	6	LSB
Integral Non-Linearity 25	EA INL CC	-4.5	–	4.5	LSB
Offset Error 25	EA OFF CC	-6	–	6	LSB
RMS Noise 26	EN RMS CC	–	1	2 27 28	LSB
Worst case ADC V DDA power supply current per active converter	I DDAA CC	–	1.5	2	mA	during conversion V DDP = 3.6 V, T J = 150 °C
Charge consumption on V AREF per conversion 18	Q CONV CC	–	30	–	pC	0 V ≤ V AREF ≤ V DDA 29
ON resistance of the analog input path	R AIN CC	–	700	1200	Ohm
ON resistance for the ADC test (pull down for AIN7)	R AIN7T CC	180	550	900	Ohm
Resistance of the reference voltage input path	R AREF CC	–	700	1700	Ohm

Figure 12. VADC Reference Voltage Range

The power-up calibration of the ADC requires a maximum number of 4352 f _ADCI cycles.

Figure 13. ADCx Input Circuits

Figure 14. ADCx Analog Input Leakage Current

Conversion Time

Table 26.Conversion Time (Operating Conditions apply)

Parameter	Symbol	Values	Unit	Note
Conversion time	t C CC	2 × T ADC + (2 + N + STC + PC +DM) × T ADCI	µs	N = 8, 10, 12 for N-bit conversion T ADC = 1 / f PERIPH T ADCI = 1 / f ADCI

• STC defines additional clock cycles to extend the sample time

• PC adds two cycles if post-calibration is enabled

• DM adds one cycle for an extended conversion time of the MSB

Conversion Time Examples

System assumptions:

f _ADC = 120 MHz i.e. t _ADC = 8.33 ns, DIVA = 3, f _ADCI = 30 MHz i.e. t _ADCI = 33.3 ns

According to the given formulas the following minimum conversion times can be achieved (STC = 0, DM = 0):

12-bit post-calibrated conversion (PC = 2):

t _CN12C = (2 + 12 + 2) × t _ADCI + 2 × t _ADC = 16 × 33.3 ns + 2 × 8.33 ns = 550 ns

12-bit uncalibrated conversion:

t _CN12 = (2 + 12) × t _ADCI + 2 × t _ADC = 14 × 33.3 ns + 2 × 8.33 ns = 483 ns

10-bit uncalibrated conversion:

t _CN10 = (2 + 10) × t _ADCI + 2 × t _ADC = 12 × 33.3 ns + 2 × 8.33 ns = 417 ns

8-bit uncalibrated:

t _CN8 = (2 + 8) × t _ADCI + 2 × t _ADC = 10 × 33.3 ns + 2 × 8.33 ns = 350 ns

Digital to Analog Converters (DACx)

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 27.DAC Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
RMS supply current	I DD CC	–	2.5	4	mA	per active DAC channel,without load currents of DAC outputs
Resolution	RES CC	–	12	–	Bit
Update rate	f URATE_A CC	–		2	Msample/s	data rate, where DAC can follow 64 LSB code jumps to ±1 LSB accuracy
Update rate	f URATE_F CC	–		5	Msample/s	data rate, where DAC can follow 64 LSB code jumps to ±4 LSB accuracy
Settling time	t SETTLE CC	–	1	2	µs	at full scale jump, output voltage reaches target value ± 20 LSB
Slew rate	SR CC	2	5	–	V/µs
Minimum output voltage	V OUT_MIN CC	–	0.3	–	V	code value unsigned: 000 ; signed: 800
Maximum output voltage	V OUT_MAX CC	–	2.5	–	V	code value unsigned: FFF ; signed: 7FF
Integral non-linearity 30	INL CC	-5.5	±2.5	5.5	LSB	R L ≥ 5 kOhm, C L ≤ 50 pF
Differential non-linearity	DNL CC	-2	±1	2	LSB	R L ≥ 5 kOhm, C L ≤ 50 pF
Offset error	ED OFF CC		±20		mV
Gain error	ED G_IN CC	-5	0	5	%
Startup time	t STARTUP CC	–	15	30	µs	time from output enabling till code valid ±16 LSB
3dB Bandwidth of Output Buffer	f C1 CC	2.5	5	–	MHz	verified by design
Output sourcing current	I OUT_SOURCE CC	–	-30	–	mA
Output sinking current	I OUT_SINK CC	–	0.6	–	mA
Output resistance	R OUT CC	–	50	–	Ohm
Load resistance	R L SR	5	–	–	kOhm
Load capacitance	C L SR	–	–	50	pF
Signal-to-Noise Ratio	SNR CC	–	70	–	dB	examination bandwidth < 25 kHz
Total Harmonic Distortion	THD CC	–	70	–	dB	examination bandwidth < 25 kHz
Power Supply Rejection Ratio	PSRR CC	–	56	–	dB	to V DDA verified by design

Conversion Calculation

Unsigned:

DACxDATA = 4095 × (V _OUT - V _{OUT_MIN}) / (V _{OUT_MAX} - V _{OUT_MIN})

Signed:

DACxDATA = 4095 × (V _OUT - V _{OUT_MIN}) / (V _{OUT_MAX} - V _{OUT_MIN}) - 2048

Figure 15. DAC Conversion Examples

Out-of-Range Comparator (ORC)

The Out-of-Range Comparator (ORC) triggers on analog input voltages ( V _AIN ) above the analog reference

31

( V _AREF ) on selected input pins (GxORCy) and generates a service request trigger (GxORCOUTy).

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

The parameters in Table 28 apply for the maximum reference voltage V _AREF = V _DDA + 50 mV.

Table 28.ORC Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
DC Switching Level	V ODC CC	100	125	200	mV	V AIN ≥ V AREF + V ODC
Hysteresis	V OHYS CC	50	–	V ODC	mV
Detection Delay of a persistent Overvoltage	t ODD CC	55	–	450	ns	V AIN ≥ V AREF + 200 mV
		45	–	105	ns	V AIN ≥ V AREF + 400 mV
Always detected Overvoltage Pulse	t OPDD CC	440	–	–	ns	V AIN ≥ V AREF + 200 mV
		90	–	–	ns	V AIN ≥ V AREF + 400 mV
Never detected Overvoltage Pulse	t OPDN CC	–	–	49	ns	V AIN ≥ V AREF + 200 mV
		–	–	30	ns	V AIN ≥ V AREF + 400 mV
Release Delay	t ORD CC	65	–	105	ns	V AIN ≤ V AREF
Enable Delay	t OED CC	–	100	200	ns

Figure 16. GxORCOUTy Trigger Generation

Figure 17. ORC Detection Ranges

High Resolution PWM (HRPWM)

The following chapters describe the operating conditions, characteristics and timing requirements, for all the components inside the HRPWM module. Each description is given for just one sub unit, e.g., one CSG or one HRC.

All the timing information is related to the module clock, f _hrpwm .

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

HRC characteristics

Table 29

summarizes the characteristics of the HRC units.

Table 29.HRC characteristics (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
High resolution step size 32 33	t HRS CC	–	150	–	ps
Startup time (after reset release)	t start CC	–	–	2	µs

CMP and 10-bit DAC characteristics

Table 30

summarizes the characteristics of the CSG unit.

The specified characteristics require that the setup of the HRPWM follows the initialization sequence as documented in the Reference Manual.

Table 30.CMP and 10-bit DAC characteristics (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
DAC Resolution	RES CC		10		bits
DAC differential nonlinearity	DNL CC	-1	–	1.5	LSB	Monotonic behavior, See Figure 18
DAC integral nonlinearity	INL CC	-3	–	3	LSB	See Figure 18
CSG Output Jitter	D CSG CC	–	–	1	clk
Bias startup time	t start CC	–	–	98	us
Bias supply current	I DDbias CC	–	–	400	µA
CSGy startup time	t CSGS CC	–	–	2	µs
Input operation current 34	I DDCIN CC	-10	–	33	µA	See Figure 19
High Speed Mode
DAC output voltage range	V DOUT CC	V SS	–	V DDP	V
DAC propagation delay - Full scale	t FShs CC	–	–	80	ns	See Figure 20
Input Selector propagation delay - Full scale	t Dhs CC	–	–	100	ns	See Figure 20
Comparator bandwidth	t Dhs CC	20	–	–	ns
DAC CLK frequency	f clk SR	–	–	30	MHz
Supply current	I DDhs CC	–	–	940	µA
Low Speed Mode
DAC output voltage range	V DOUT CC	0.1 × V DDP 35	–	V DDP	V
DAC propagation delay - Full Scale	t FSls CC	–	–	160	ns	See Figure 20
Input Selector propagation delay - Full Scale	t Dls CC	–	–	200	ns	See Figure 20
Comparator bandwidth	t Dls CC	20	–	–	ns
DAC CLK frequency	f clk SR	–	–	30	MHz
Supply current	I DDls CC	–	–	300	µA

Figure 18. CSG DAC INL and DNL example

Figure 19. Input operation current

Figure 20. DAC and Input Selector Propagation Delay

Clocks

HRPWM DAC Conversion Clock

The DAC conversion clock can be generated internally or it can be controlled via a HRPWM module pin.

Table 31.External DAC conversion trigger operating conditions

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Frequency	f etrg SR	–	–	30 37	MHz
ON time	t onetrg SR	2 T ccu	–	–	ns
OFF time	t offetrg SR	2 T ccu 36 37	–	–	ns

CSG External Clock

It is possible to select an external source, that can be used as a clock for the slope generation, HRPWMx.ECLKy. This clock is synchronized internally with the module clock and therefore the external clock needs to meet the criterion described on

Table 32

.

Table 32.External clock operating conditions

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Frequency	f eclk SR	–	–	f hrpwm /4	MHz
ON time	t oneclk SR	2 T ccu	–	–	ns
OFF time	t offeclk SR	2 T ccu 38 39	–	–	ns	Only the rising edge is used

Low Power Analog Comparator (LPAC)

The Low Power Analog Comparator (LPAC) triggers a wake-up event from Hibernate state or an interrupt trigger during normal operation. It does so by comparing V _BAT or another external sensor voltage V _LPS with a pre-programmed threshold voltage.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 33.Low Power Analog Comparator Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
V BAT supply voltage range for LPAC operation	V BAT SR	2.1	–	3.6	V
Sensor voltage range	V LPCS CC	0	–	1.2	V
Threshold step size	V th CC	–	18.75	–	mV
Threshold trigger accuracy	Δ V th CC	–	–	±10	%	for V th > 0.4 V
Conversion time	t LPCC CC	–	–	250	µs
Average current consumption over time	I LPCAC CC	–	–	15	µA	conversion interval 10 ms
Current consumption during conversion	I LPCC CC	–	150	–	µA	40

Die Temperature Sensor

The Die Temperature Sensor (DTS) measures the junction temperature T _J .

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 34.Die Temperature Sensor Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Temperature sensor range	T SR SR	-40	–	150	°C
Linearity Error (to the below defined formula)	Δ T LE CC	–	±1	–	°C	per Δ T J ≤ 30 °C
Offset Error	Δ T OE CC	–	±6	–	°C	Δ T OE = T J - T DTS V DDP ≤ 3.3 V 41
Measurement time	t M CC	–	–	100	µs
Start-up time after reset inactive	t TSST SR	–	–	10	µs

The following formula calculates the temperature measured by the DTS in [°C] from the RESULT bit field of the DTSSTAT register.

Temperature T _DTS = (RESULT - 605) / 2.05 [°C]

This formula and the values defined in

Table 34

apply with the following calibration values:

• DTSCON.BGTRIM = 8

• DTSCON.REFTRIM = 4

USB OTG Interface DC Characteristics

The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification and the OTG Specification Rev. 1.3. High-Speed Mode is not supported.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 35.USB OTG VBUS and ID Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
VBUS input voltage range	V IN CC	0.0	–	5.25	V
A-device VBUS valid threshold	V B1 CC	4.4	–	–	V
A-device session valid threshold	V B2 CC	0.8	–	2.0	V
B-device session valid threshold	V B3 CC	0.8	–	4.0	V
B-device session end threshold	V B4 CC	0.2	–	0.8	V
VBUS input resistance to ground	R VBUS_IN CC	40	–	100	kOhm
B-device VBUS pull-up resistor	R VBUS_PU CC	281	–	–	Ohm	Pull-up voltage = 3.0 V
B-device VBUS pull-down resistor	R VBUS_PD CC	656	–	–	Ohm
USB.ID pull-up resistor	R UID_PU CC	14	–	25	kOhm
VBUS input current	I VBUS_IN CC	–	–	150	µA	0 V ≤ V IN ≤ 5.25 V: T AVG = 1 ms

Table 36.USB OTG Data Line (USB_DP, USB_DM) Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Input low voltage	V IL SR	–	–	0.8	V
Input high voltage (driven)	V IH SR	2.0	–	–	V
Input high voltage (floating) 42	V IHZ SR	2.7	–	3.6	V
Differential input sensitivity	V DIS CC	0.2	–	–	V
Differential common mode range	V CM CC	0.8	–	2.5	V
Output low voltage	V OL CC	0.0	–	0.3	V	1.5 kOhm pull-up to 3.6 V
Output high voltage	V OH CC	2.8	–	3.6	V	15 kOhm pull-down to 0 V
DP pull-up resistor (idle bus)	R PUI CC	900	–	1575	Ohm
DP pull-up resistor (upstream port receiving)	R PUA CC	1425	–	3090	Ohm
DP, DM pull-down resistor	R PD CC	14.25	–	24.8	kOhm
Input impedance DP, DM	Z INP CC	300	–	–	kOhm	0 V ≤ V IN ≤ V DDP
Driver output resistance DP, DM	Z DRV CC	28	–	44	Ohm

Oscillator Pins

Note:
It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

The oscillator pins can be operated with an external crystal (see

Figure 21

) or in direct input mode (see

Figure 22

).

Figure 21. Oscillator in Crystal Mode

Figure 22. Oscillator in Direct Input Mode

Table 37.OSC_XTAL Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Input frequency	f OSC SR	4	–	40	MHz	Direct Input Mode selected
		4	–	25	MHz	External Crystal Mode selected
Oscillator start-up time 43	t OSCS CC	–	–	10	ms
Input voltage at XTAL1	V IX SR	-0.5	–	V DDP + 0.5	V
Input amplitude (peak-to-peak) at XTAL1 44 45	V PPX SR	0.4 × V DDP	–	V DDP + 1.0	V
Input high voltage at XTAL1	V IHBX SR	1.0	–	V DDP + 0.5	V
Input low voltage at XTAL1 46	V ILBX SR	-0.5	–	0.4	V
Input leakage current at XTAL1	I ILX1 CC	-100	–	100	nA	Oscillator power down 0 V ≤ V IX ≤ V DDP

Table 38.RTC_XTAL Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Input frequency	f OSC SR	–	32.768	–	kHz
Oscillator start-up time 47 49	t OSCS CC	–	–	5	s
Input voltage at RTC_XTAL1	V IX SR	-0.3	–	V BAT + 0.3	V
Input amplitude (peak-to-peak) at RTC_XTAL1 48 50	V PPX SR	0.4	–	–	V
Input high voltage at RTC_XTAL1	V IHBX SR	0.6 × V BAT	–	V BAT + 0.3	V
Input low voltage at RTC_XTAL1 51	V ILBX SR	-0.3	–	0.36 × V BAT	V
Input Hysteresis for RTC_XTAL1 51 52	V HYSX CC	0.1 × V BAT		–	V	3.0 V ≤ V BAT < 3.6 V
		0.03 × V BAT		–	V	V BAT < 3.0 V
Input leakage current at RTC_XTAL1	I ILX1 CC	-100	–	100	nA	Oscillator power down 0 V ≤ V IX ≤ V BAT

Power Supply Current

The total power supply current defined below consists of a leakage and a switching component.

Application relevant values are typically lower than those given in the following tables, and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations).

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

If not stated otherwise, the operating conditions for the parameters in the following table are:

V _DDP = 3.3 V, T _A = 25 °C

Table 39.Power Supply Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Active supply current 53 Peripherals enabled Frequency: f CPU / f PERIPH / f CCU in MHz	I DDPA CC	–	113	–	mA	120 / 120 / 120
		–	102	–		120 / 60 / 60
		–	82	–		60 / 60 / 120
		–	61	–		24 / 24 / 24
		–	51	–		1 / 1 / 1
Active supply current Code execution from RAM Flash in Sleep mode Frequency: f CPU / f PERIPH / f CCU in MHz	I DDPA CC	–	53	–	mA	120 / 120 / 120
		–	50	–		120 / 60 / 60
Active supply current 54 Peripherals disabled Frequency: f CPU / f PERIPH in MHz	I DDPA CC	–	80	–	mA	120 / 120 / 120
		–	80	–		120 / 60 / 60
		–	65	–		60 / 60 / 120
		–	55	–		24 / 24 / 24
		–	50	–		1 / 1 / 1
Sleep supply current 55 Peripherals enabled Frequency: Frequency: f CPU / f PERIPH / f CCU in MHz	I DDPS CC	–	104	–	mA	120 / 120 / 120
		–	93	–		120 / 60 / 60
		–	78	–		60 / 60 / 120
		–	57	–		24 / 24 / 24
		–	46	–		1 / 1 / 1
f CPU / f PERIPH / f CCU in kHz		–	46	–		100 / 100 / 100
Sleep supply current 56 Peripherals disabled Frequency: f CPU / f PERIPH / f CCU in MHz	I DDPS CC	–	72	–	mA	120 / 120 / 120
		–	71	–		120 / 60 / 60
		–	61	–		60 / 60 / 120
		–	52	–		24 / 24 / 24
		–	46	–		1 / 1 / 1
f CPU / f PERIPH / f CCU in kHz		–	46	–		100 / 100 / 100
Deep Sleep supply current 57 Flash in Sleep mode Frequency: f CPU / f PERIPH / f CCU in MHz	I DDPD CC	–	8	–	mA	24 / 24 / 24
		–	5	–		4 / 4 / 4
		–	4	–		1 / 1 / 1
f CPU / f PERIPH / f CCU in kHz		–	4.5	–		100 / 100 / 100 58
Hibernate supply current RTC on 59	I DDPH CC	–	12.8	–	µA	V BAT = 3.3 V
		–	9.0	–		V BAT = 2.4 V
		–	7.7	–		V BAT = 2.0 V
Hibernate supply current RTC off 60	I DDPH CC	–	12.0	–	µA	V BAT = 3.3 V
		–	8.4	–		V BAT = 2.4 V
		–	7.0	–		V BAT = 2.0 V
Worst case active supply current 61	I DDPA CC	–	–	170 62	mA	V DDP = 3.6 V, T J = 150 °C
V DDA power supply current	I DDA CC	–	–	– 63	mA
I DDP current at $\overline{PORST}$ Low	I DDP_PORST CC	–	–	30	mA	V DDP = 3.6 V, T J = 150 °C
Power Dissipation	P DISS CC	–	–	1	W	V DDP = 3.6 V, T J = 150 °C
Wake-up time from Sleep to Active mode	t SSA CC	–	6	–	cycles
Wake-up time from Deep Sleep to Active mode		–	–	–	ms	Defined by the wake-up of the Flash module, see Flash Memory Parameters
Wake-up time from Hibernate mode		–	–	–	ms	Wake-up via power-on reset event, see Power-Up and Supply Monitoring

Peripheral Idle Currents

Test conditions:

• f _sys and derived clocks at 120 MHz

• V _DDP = 3.3 V, T _a =25 °C

• all peripherals are held in reset (see the PRSTAT registers in the Reset Control Unit of the SCU)

• the peripheral clocks are disabled (see CGATSTAT registers in the Clock Control Unit of the SCU

• no I/O activity

• the given values are a result of differential measurements with asserted and deasserted peripheral reset and enabled clock of the peripheral under test

The tested peripheral is left in the state after the peripheral reset is deasserted, no further initialisation or configuration is done. E.g. no timer is running in the CCUs, no communication active in the USICs, etc.

Table 40.Peripheral Idle Currents

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
PORTS ETH USB FCE WDT POSIFx	I PER CC	–	≤ 0.3	–	mA
MultiCAN ERU LEDTSCU0 CCU4x CCU8x		–	≤ 1.0	–
DAC (digital)		–	1.3	–
USICx		–	3.0	–
DSD VADC (digital) 64		–	4.5	–
DMAx		–	6.0	–

Flash Memory Parameters

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 41.Flash Memory Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Erase Time per 256 Kbyte Sector	t ERP CC	–	5	5.5	s
Erase Time per 64 Kbyte Sector	t ERP CC	–	1.2	1.4	s
Erase Time per 16 Kbyte Logical Sector	t ERP CC	–	0.3	0.4	s
Program time per page 65	t PRP CC	–	5.5	11	ms
Erase suspend delay	t FL_ErSusp CC	–	–	15	ms
Wait time after margin change	t FL_MarginDel CC	10	–	–	µs
Wake-up time	t WU CC	–	–	270	µs
Read access time	t a CC	20	–	–	ns	For operation with 1 / f CPU < t a wait states must be configured 66
Data Retention Time, Physical Sector	t RET CC	20	–	–	years	Max. 1000 erase/program cycles
Data Retention Time, Logical Sector 67 68	t RETL CC	20	–	–	years	Max. 100 erase/program cycles
Data Retention Time, User Configuration Block (UCB) 67 68	t RTU CC	20	–	–	years	Max. 4 erase/program cycles per UCB
Endurance on 64 Kbyte Physical Sector PS4	N EPS4 CC	10000	–	–	cycles	BA-marking devices only!Cycling distributed over life time 69

AC Parameters

Testing Waveforms

Figure 23. Rise/Fall Time Parameters

Figure 24. Testing Waveform, Output Delay

Figure 25. Testing Waveform, Output High Impedance

Power-Up and Supply Monitoring

$\overline{PORST}$ is always asserted when V _DDP and/or V _DDC violate the respective thresholds.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Figure 26. $\overline{PORST}$ Circuit

Table 42.Supply Monitoring Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Digital supply voltage reset threshold	V POR CC	2.79 70	–	3.05 71	V	72
Core supply voltage reset threshold	V PV CC	–	–	1.17	V
V DDP voltage to ensure defined pad states	V DDPPA CC	–	1.0	–	V
$\overline{PORST}$ rise time	t PR SR	–	–	2	μs
Startup time from power-on reset with code execution from Flash	t SSW CC	–	2.5	3.5	ms	Time to the first user code instruction
V DDC ramp up time	t VCR CC	–	550	–	μs	Ramp up after power-on or after a reset triggered by a violation of V POR or V PV

Figure 27. Power-Up Behavior

Power Sequencing

While starting up and shutting down as well as when switching power modes of the system it is important to limit the current load steps. A typical cause for such load steps is changing the CPU frequency f _CPU . Load steps exceeding the below defined values may cause a power on reset triggered by the supply monitor.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 43.Power Sequencing Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Positive Load Step Current	Δ I PLS SR	–	–	50	mA	Load increase on V DDP Δ t ≤ 10 ns
Negative Load Step Current	Δ I NLS SR	–	–	150	mA	Load decrease on V DDP Δ t ≤ 10 ns
V DDC Voltage Over- / Undershoot from Load Step	Δ V LS CC	–	–	±100	mV	For maximum positive or negative load step
Positive Load Step Settling Time	t PLSS SR	50	–	–	µs
Negative Load Step Settling Time	t NLSS SR	100	–	–	µs
External Buffer Capacitor on V DDC	C EXT SR	3	4.7	6	µF	In addition C = 100 nF capacitor on each V DDC pin

Positive Load Step Examples

System assumptions:

f _CPU = f _SYS, target frequency f _CPU = 120 MHz, main PLL f _VCO = 480 MHz, stepping done by K2 divider, t _PLSS between individual steps:

24 MHz - 48 MHz - 68 MHz - 96 MHz - 120 MHz (K2 steps 20 - 10 - 7 - 5 - 4)

24 MHz - 68 MHz - 96 MHz - 120 MHz (K2 steps 20 - 7 - 5 - 4)

24 MHz - 68 MHz - 120 MHz (K2 steps 20 - 7 - 4)

Phase Locked Loop (PLL) Characteristics

Main and USB PLL

Table 44.PLL Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Accumulated Jitter	D P CC	–	–	±5	ns	accumulated over 300 cycles f SYS = 120 MHz
Duty Cycle 73	D DC CC	46	50	54	%	Low pulse to total period, assuming an ideal input clock source
PLL base frequency	f PLLBASE CC	30	–	140	MHz
VCO input frequency	f REF CC	4	–	16	MHz
VCO frequency range	f VCO CC	260	–	520	MHz
PLL lock-in time	t L CC	–	–	400	µs

Internal Clock Source Characteristics

Fast Internal Clock Source

Table 45.Fast Internal Clock Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Nominal frequency	f OFINC CC	–	36.5	–	MHz	not calibrated
		–	24	–	MHz	calibrated
Accuracy	Δ f OFI CC	-0.5	–	0.5	%	automatic calibration 74 75
		-15	–	15	%	factory calibration, V DDP = 3.3 V
		-25	–	25	%	no calibration, V DDP = 3.3 V
		-7	–	7	%	Variation over voltage range 76 3.13 V ≤ V DDP ≤ 3.63 V
Start-up time	t OFIS CC	–	50	–	µs

Slow Internal Clock Source

Table 46.Slow Internal Clock Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Nominal frequency	f OSI CC	–	32.768	–	kHz
Accuracy	Δ f OSI CC	-4	–	4	%	V BAT = const. 0 °C ≤ T A ≤ 85 °C
		-5	–	5	%	V BAT = const. T A < 0 °C or T A > 85 °C
		-5	–	5	%	2.4 V ≤ V BAT , T A = 25 °C
		-10	–	10	%	1.95 V ≤ V BAT < 2.4 V, T A = 25 °C
Start-up time	t OSIS CC	–	50	–	µs

JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Note:
Operating conditions apply.

Table 47.JTAG Interface Timing Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
TCK clock period	t 1 SR	25	–	–	ns
TCK high time	t 2 SR	10	–	–	ns
TCK low time	t 3 SR	10	–	–	ns
TCK clock rise time	t 4 SR	–	–	4	ns
TCK clock fall time	t 5 SR	–	–	4	ns
TDI/TMS setup to TCK rising edge	t 6 SR	6	–	–	ns
TDI/TMS hold after TCK rising edge	t 7 SR	6	–	–	ns
TDO valid after TCK falling edge (propagation delay)	t 8 CC	–	–	13	ns	C L = 50 pF
		3	–	–	ns	C L = 20 pF
TDO hold after TCK falling edge 77	t 18 CC	2	–	–	ns
TDO high imped. to valid from TCK falling edge 77 78	t 9 CC	–	–	14	ns	C L = 50 pF
TDO valid to high imped. from TCK falling edge 77	t 10 CC	–	–	13.5	ns	C L = 50 pF

Figure 28. Test Clock Timing (TCK)

Figure 29. JTAG Timing

Serial Wire Debug Port (SW-DP) Timing

The following parameters are applicable for communication through the SW-DP interface.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Note:
Operating conditions apply.

Table 48.SWD Interface Timing Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
SWDCLK clock period	t SC SR	25	–	–	ns	C L = 30 pF
		40	–	–	ns	C L = 50 pF
SWDCLK high time	t 1 SR	10	–	500000	ns
SWDCLK low time	t 2 SR	10	–	500000	ns
SWDIO input setup to SWDCLK rising edge	t 3 SR	6	–	–	ns
SWDIO input hold after SWDCLK rising edge	t 4 SR	6	–	–	ns
SWDIO output valid time after SWDCLK rising edge	t 5 CC	–	–	17	ns	C L = 50 pF
		–	–	13	ns	C L = 30 pF
SWDIO output hold time from SWDCLK rising edge	t 6 CC	3	–	–	ns

Figure 30. SWD Timing

Embedded Trace Macro Cell (ETM) Timing

The Data timing are to the active clock edge, in half-rate clocking mode that is the rising and falling clock edge.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Note:
Operating conditions apply, with C _L ≤ 15 pF.

Table 49.ETM Interface Timing Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
TRACECLK period	t 1 CC	16.7	–	–	ns	–
TRACECLK high time	t 2 CC	2	–	–	ns	–
TRACECLK low time	t 3 CC	2	–	–	ns	–
TRACECLK and TRACEDATA rise time	t 4 CC	–	–	3	ns	–
TRACECLK and TRACEDATA fall time	t 5 CC	–	–	3	ns	–
TRACEDATA output valid time	t 6 CC	-2	–	3	ns	–

Figure 31. ETM Clock Timing

Figure 32. ETM Data Timing

Peripheral Timing

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Note:
Operating conditions apply.

Delta-Sigma Demodulator Digital Interface Timing

The following parameters are applicable for the digital interface of the Delta-Sigma Demodulator (DSD).

The data timing is relative to the active clock edge. Depending on the operation mode of the connected modulator that can be the rising and falling clock edge.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 50.DSD Interface Timing Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
MCLK period in master mode	t 1 CC	33.3	–	–	ns	t 1 ≥ 4 x t PERIPH
MCLK high time in master mode	t 2 CC	9	–	–	ns	t 2 > t PERIPH 79
MCLK low time in master mode	t 3 CC	9	–	–	ns	t 3 > t PERIPH 79
MCLK period in slave mode	t 1 SR	33.3	–	–	ns	t 1 ≥ 4 × t PERIPH 79
MCLK high time in slave mode	t 2 SR	t PERIPH	–	–	ns	79
MCLK low time in slave mode	t 3 SR	t PERIPH	–	–	ns	79
DIN input setup time to the active clock edge	t 4 SR	t PERIPH + 4	–	–	ns	79
DIN input hold time from the active clock edge	t 5 SR	t PERIPH + 3	–	–	ns	79

Figure 33. DSD Data Timing

Synchronous Serial Interface (USIC SSC) Timing

The following parameters are applicable for a USIC channel operated in SSC mode.

Note:
Operating Conditions apply.

Table 51.USIC SSC Master Mode Timing

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
SCLKOUT master clock period	t CLK CC	33.3	–	–	ns
Slave select output SELO active to first SCLKOUT transmit edge	t 1 CC	t SYS - 6.5	–	–	ns
Slave select output SELO inactive after last SCLKOUT receive edge	t 2 CC	t SYS - 8.5 80	–	–	ns
Data output DOUT[3:0] valid time	t 3 CC	-6	–	8	ns
Receive data input DX0/DX[5:3] setup time to SCLKOUT receive edge	t 4 SR	23	–	–	ns
Data input DX0/DX[5:3] hold time from SCLKOUT receive edge	t 5 SR	1	–	–	ns

Table 52.USIC SSC Slave Mode Timing

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
DX1 slave clock period	t CLK SR	66.6	–	–	ns
Select input DX2 setup to first clock input DX1 transmit edge	t 10 SR	3	–	–	ns
Select input DX2 hold after last clock input DX1 receive edge 81	t 11 SR	4	–	–	ns
Receive data input DX0/DX[5:3] setup time to shift clock receive edge 81	t 12 SR	6	–	–	ns
Data input DX0/DX[5:3] hold time from clock input DX1 receive edge 81	t 13 SR	4	–	–	ns
Data output DOUT[3:0] valid time	t 14 CC	0	–	24	ns

Figure 34. USIC - SSC Master/Slave Mode Timing

Note:
This timing diagram shows a standard configuration, for which the slave select signal is low-active, and the serial clock signal is not shifted and not inverted.

Inter-IC (IIC) Interface Timing

The following parameters are applicable for a USIC channel operated in IIC mode.

Note:
Operating Conditions apply.

Table 53.USIC IIC Standard Mode Timing ⁸²

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Fall time of both SDA and SCL	t 1 CC/SR	–	–	300	ns
Rise time of both SDA and SCL	t 2 CC/SR	–	–	1000	ns
Data hold time	t 3 CC/SR	0	–	–	µs
Data set-up time	t 4 CC/SR	250	–	–	ns
LOW period of SCL clock	t 5 CC/SR	4.7	–	–	µs
HIGH period of SCL clock	t 6 CC/SR	4.0	–	–	µs
Hold time for (repeated) START condition	t 7 CC/SR	4.0	–	–	µs
Set-up time for repeated START condition	t 8 CC/SR	4.7	–	–	µs
Set-up time for STOP condition	t 9 CC/SR	4.0	–	–	µs
Bus free time between a STOP and START condition	t 10 CC/SR	4.7	–	–	µs
Capacitive load for each bus line	C b SR	–	–	400	pF

Table 54.USIC IIC Fast Mode Timing ⁸³

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Fall time of both SDA and SCL	t 1 CC/SR	20 + 0.1* C b	–	300	ns
Rise time of both SDA and SCL	t 2 CC/SR	20 + 0.1* C b 84	–	300	ns
Data hold time	t 3 CC/SR	0	–	–	µs
Data set-up time	t 4 CC/SR	100	–	–	ns
LOW period of SCL clock	t 5 CC/SR	1.3	–	–	µs
HIGH period of SCL clock	t 6 CC/SR	0.6	–	–	µs
Hold time for (repeated) START condition	t 7 CC/SR	0.6	–	–	µs
Set-up time for repeated START condition	t 8 CC/SR	0.6	–	–	µs
Set-up time for STOP condition	t 9 CC/SR	0.6	–	–	µs
Bus free time between a STOP and START condition	t 10 CC/SR	1.3	–	–	µs
Capacitive load for each bus line	C b SR	–	–	400	pF

Figure 35. USIC IIC Stand and Fast Mode Timing

Inter-IC Sound (IIS) Interface Timing

The following parameters are applicable for a USIC channel operated in IIS mode.

Note:
Operating Conditions apply.

Table 55.USIC IIS Master Transmitter Timing

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Clock period	t 1 CC	33.3	–	–	ns
Clock HIGH	t 2 CC	0.35 × t 1min	–	–	ns
Clock Low	t 3 CC	0.35 × t 1min	–	–	ns
Hold time	t 4 CC	0	–	–	ns
Clock rise time	t 5 CC	–	–	0.15 × t 1min	ns

Figure 36. USIC IIS Master Transmitter Timing

Table 56.USIC IIS Slave Receiver Timing

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Clock period	t 6 SR	66.6	–	–	ns
Clock HIGH	t 7 SR	0.35 × t 6min	–	–	ns
Clock Low	t 8 SR	0.35 × t 6min	–	–	ns
Set-up time	t 9 SR	0.2 × t 6min	–	–	ns
Hold time	t 10 SR	0	–	–	ns

Figure 37. USIC IIS Slave Receiver Timing

USB Interface Characteristics

The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification and the OTG Specification Rev. 1.3. High-Speed Mode is not supported.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 57.USB Timing Parameters (operating conditions apply)

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Rise time	t R CC	4	–	20	ns	C L = 50 pF
Fall time	t F CC	4	–	20	ns	C L = 50 pF
Rise/Fall time matching	t R / t F CC	90	–	111.11	%	C L = 50 pF
Crossover voltage	V CRS CC	1.3	–	2.0	V	C L = 50 pF

Figure 38. USB Signal Timing

Ethernet Interface (ETH) Characteristics

For proper operation of the Ethernet Interface it is required that f _SYS ≥ 100 MHz.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

ETH Measurement Reference Points

Figure 39. ETH Measurement Reference Points

ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)

Table 58.ETH Management Signal Timing Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
ETH_MDC period	t 1 CC	400	–	–	ns	C L = 25 pF
ETH_MDC high time	t 2 CC	160	–	–	ns
ETH_MDC low time	t 3 CC	160	–	–	ns
ETH_MDIO setup time (output)	t 4 CC	10	–	–	ns
ETH_MDIO hold time (output)	t 5 CC	10	–	–	ns
ETH_MDIO data valid (input)	t 6 SR	0	–	300	ns

Figure 40. ETH Management Signal Timing

ETH RMII Parameters

In the following, the parameters of the RMII (Reduced Media Independent Interface) are described.

Table 59.ETH RMII Signal Timing Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
ETH_RMII_REF_CL clock period	t 13 SR	20	–	–	ns	C L = 25 pF; 50 ppm
ETH_RMII_REF_CL clock high time	t 14 SR	7	–	13	ns	C L = 25 pF
ETH_RMII_REF_CL clock low time	t 15 SR	7	–	13	ns
ETH_RMII_RXD[1:0], ETH_RMII_CRS setup time	t 16 SR	4	–	–	ns
ETH_RMII_RXD[1:0], ETH_RMII_CRS hold time	t 17 SR	2	–	–	ns
ETH_RMII_TXD[1:0], ETH_RMII_TXEN data valid	t 18 CC	4	–	15	ns

Figure 41. ETH RMII Signal Timing

Package and Reliability

The XMC4400 is a member of the XMC4000 Family of microcontrollers. It is also compatible to a certain extent with members of similar families or subfamilies.

Each package is optimized for the device it houses. Therefore, there may be slight differences between packages of the same pin-count but for different device types. In particular, the size of the Exposed Die Pad may vary.

If different device types are considered or planned for an application, it must be ensured that the board layout fits all packages under consideration.

Package Parameters

Table 60

provides the thermal characteristics of the packages used in XMC4400.

Table 60.Thermal Characteristics of the Packages

Parameter	Symbol	Limit Values		Unit	Package Types
		Min.	Max.
Exposed Die Pad dimensions (including U-Groove where applicable)	Ex × Ey CC	–	7.0 × 7.0	mm	PG-LQFP-100-25 PG-LQFP-100-29
		–	5.7 × 5.7	mm	PG-TQFP-64-19 PG-TQFP-64-21
Exposed Die Pad dimensions excluding U-Groove	Ax × Ay CC	–	6.2 × 6.2	mm	PG-LQFP-100-25
		–	–	mm	PG-LQFP-100-29
		–	4.9 × 4.9	mm	PG-TQFP-64-19
		–	–	mm	PG-TQFP-64-21
Thermal resistance Junction-Ambient T J ≤ 150 °C	R ΘJA CC	–	22.5	K/W	PG-LQFP-100-25 PG-LQFP-100-29 85
		–	20.0	K/W	PG-TQFP-64-19 85 PG-TQFP-64-21 85

Note:
For electrical reasons, it is required to connect the exposed pad to the board ground V

SS

, independent of EMC and thermal requirements.

Thermal Considerations

When operating the XMC4400 in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage.

The maximum heat that can be dissipated depends on the package and its integration into the target board. The “Thermal resistance R _ΘJA ” quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 150 °C.

The difference between junction temperature and ambient temperature is determined by

Δ T = ( P _INT + P _IOSTAT + P _IODYN ) × R _ΘJA

The internal power consumption is defined as

P _INT = V _DDP × I _DDP (switching current and leakage current).

The static external power consumption caused by the output drivers is defined as

P _IOSTAT = Σ((V _DDP - V _OH) × I _OH) + Σ(V _OL × I _OL)

The dynamic external power consumption caused by the output drivers ( P _IODYN ) depends on the capacitive load connected to the respective pins and their switching frequencies.

If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation:

• Reduce V _DDP , if possible in the system

• Reduce the system frequency

• Reduce the number of output pins

• Reduce the load on active output drivers

Package Outlines

The availability of different packages for different devices types is listed in

Table 1

, specific packages for different device markings are listed in

Table 2

.

The exposed die pad dimensions are listed in

Table 60

.

Figure 42. PG-LQFP-100-25 (Plastic Green Low Profile Quad Flat Package)

Figure 43. PG-LQFP-100-29 (Plastic Green Low Profile Quad Flat Package)

Figure 44. PG-TQFP-64-19 (Plastic Green Low Profile Quad Flat Package)

Figure 45. PG-TQFP-64-21 (Plastic Green Low Profile Quad Flat Package)

All dimensions in mm.

You can find complete information about Infineon packages, packing and marking in our Infineon Internet Page “Packages”:

http://www.infineon.com/packages

Quality Declarations

The qualification of the XMC4400 is executed according to the JEDEC standard JESD47H.

Note:
For automotive applications refer to the Infineon automotive microcontrollers.

Table 61.Quality Parameters

Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Operation lifetime	t OP CC	20	−	−	a	T J ≤ 109°C, device permanent on
ESD susceptibility according to Human Body Model (HBM)	V HBM SR	−	−	2000	V	EIA/JESD22-A114-B
ESD susceptibility according to Charged Device Model (CDM)	V CDM SR	−	−	500	V	Conforming to JESD22-C101-C
Moisture sensitivity level	MSL CC	−	−	3	−	JEDEC J-STD-020D
Soldering temperature	T SDR SR	−	−	260	°C	Profile according to JEDEC J-STD-020D

Revision history

Document revision	Date	Description of changes
V1.3	2018-09-01	Added RMS Noise parameter in VADC Parameters table. Added a section listing the packages of the different markings. Added BA marking variant. Added footnote explaining minimum V BAT requirements to start the hibernate domain and/or oscillation of a crystal on RTC_XTAL. Changed pull device definition to System Requirement (SR) to reflect that the specified currents are defined by the characteristics of the external load/driver. Added information that PORST Pull-up is identical to the pull-up on standard I/O pins. Updated C AINSW , C AINTOT and R AIN parameters with improved values. Added footnote on test configuration for LPAC measurement. Corrected parameter name of of USB pull device (upstream port receiving) definition according to USB standard (referenced to DM instead of DP) Relaxed RTC_XTAL V PPX parameter value and changed it to a system requirement. Added footnote on current consumption by enabling of ƒ CCU . Added Flash endurance parameter for 64 Kbytes Physical Sector PS4 N EPS4 for devices with BA marking. Added PG-TQFP-64-19 and PG-LQFP-100-25 package information. Added tables describing the differences between PG-LQFP-100-11 to PGLQFP-100-25 as well as PG-LQFP-64-19 to PG-TQFP-64-19 packages Updated to JEDEC standard J-STD-020D for the moisture sensitivity level and added solder temperature parameter according to the same standard.
V1.4	2024-12-05	Updated template. The following are updated: Table 1 : Replaced PG-yQFP-64 with PG-TQFP-64. Deleted Note 2 on “y” placeholder. Table 2 : Deleted Marking column and package details (PG-LQFP-100-11 and PG-LQFP-64-19). Updated package variant XMC4400-F64: Added package details (PG-TQFP-64-21). Updated package variant XMC4400-F100: Added package details (PG-LQFP-64-29). Table 7 : Replaced PG-LQFP-64 with PG-TQFP-64. Figure 3 : Deleted PG-LQFP-64 in the figure title. Figure 5 : Deleted PG-LQFP-64 in the figure title (XMC4400 PG-TQFP-64 Pin Configuration (top view)). Table 10 : Deleted LQFP-64. Table 25 : Replaced PG-LQFP-64 with PG-TQFP-64 in the Description for Differential Non-Linearity Error and Gain Error parameters. Table 60 : Deleted package details: PG-LQFP-100-11 and PG-LQFP-64-19 Added package details: PG-LQFP-100-29 and PG-TQFP-64-21 Deleted Table 61 “Differences PG-LQFP-100-11 to PG-LQFP-100-24” Deleted Table 62 “Differences PG-LQFP-64-19 to PG-TQFP-64-19”. Deleted package diagram in Figure 42 (PG-LQFP-100-11). Figure 43 : Added package diagram: PG-LQFP-100-29. Figure 44 : Deleted package diagram: PG-LQFP-64-19. Added package diagram: PG-TQFP-64-19. Figure 45 : Added package diagram: PG-TQFP-64-21.

1

x is a placeholder for the supported temperature range.

2

x is a placeholder for the supported temperature range.

3

x is a placeholder for the supported temperature range.

4

Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port I/O Function table.

5

The port groups are defined in

Table 17

.

6

The port groups are defined in

Table 17

.

7

See also the Supply Monitoring thresholds,

Power-Up and Supply Monitoring

.

8

Voltage overshoot to 4.0 V is permissible at Power-Up and $\overline{PORST}$ low, provided the pulse duration is less than 100 µs and the cumulated sum of the pulses does not exceed 1 h over lifetime.

9

Different limits apply for LPAC operation,

Low Power Analog Comparator (LPAC)

10

To start the hibernate domain it is required that V _BAT ≥ 2.1 V, for a reliable start of the oscillation of RTC_XTAL in crystal mode it is required that V _BAT ≥ 3.0 V.

11

The port groups are defined in

Table 17

.

12

Current required to override the pull device with the opposite logic level (“force current”). With active pull device, at load currents between force and keep current the input state is undefined.

13

Load current at which the pull device still maintains the valid logic level (“keep current”). With active pull device, at load currents between force and keep current the input state is undefined.

14

Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not be guaranteed that it suppresses switching due to external system noise.

15

POD = Pin Out Driver

16

POD = Pin Out Driver

17

Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not be guaranteed that it suppresses switching due to external system noise

18

Applies to AINx, when used as alternate reference input.

19

A running conversion may become imprecise in case the normal conditions are violated (voltage overshoot).

20

If the analog reference voltage is below V _DDA , then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE, DNL, INL, Gain, and Offset errors increase also by the factor 1/k.

21

The leakage current definition is a continuous function, as shown in figure ADCx Analog Inputs Leakage. The numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function (see

Figure 14

).

22

The sampling capacity of the conversion C-network is pre-charged to V _AREF /2 before the sampling moment. Because of the parasitic elements, the voltage measured at AINx can deviate from V _AREF /2.

23

This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead, smaller capacitances are successively switched to the reference voltage.

24

For 10-bit conversions, the errors are reduced to 1/4; for 8-bit conversions, the errors are reduced to 1/16. Never less than ±1 LSB.

25

The sum of DNL/INL/GAIN/OFF errors does not exceed the related total unadjusted error TUE.

26

This parameter is valid for soldered devices and requires careful analog board design.

27

Resulting worst case combined error is arithmetic combination of TUE and EN _RMS .

28

Value is defined for one sigma Gauss distribution.

29

The resulting current for a conversion can be calculated with I _AREF = Q _CONV / t _c. The fastest 12-bit post-calibrated conversion of t _c = 550 ns results in a typical average current of I _AREF = 54.5 μA.

30

According to best straight line method.

31

Always the standard VADC reference, alternate references do not apply to the ORC.

32

The step size for clock frequencies equal to 180, 120 and 80 MHz is 150 ps.

33

The step size for clock frequencies different from 180, 120 and 80 MHz but within the range from 180 to 64 MHz can be between 118 to 180 ps (fixed over process and operating conditions)

34

Typical input resistance R _CIN = 100kOhm.

35

The INL error increases for DAC output voltages below this limit.

36

50% duty cycle is not obligatory

37

Only valid if the signal was not previously synchronized/generated with the fccu clock (or a synchronous clock)

38

50% duty cycle is not obligatory

39

Only valid if the signal was not previously synchronized/generated with the fccu clock (or a synchronous clock)

40

Single channel conversion, measuring V _BAT = 3.3 V, 8 cycles settling time

41

At V _{DDP_max} = 3.63 V the typical offset error increases by an additional Δ T _OE = ±1 °C.

42

Measured at A-connector with 1.5 kOhm ± 5% to 3.3 V ± 0.3 V connected to USB_DP or USB_DM and at B-connector with 15 kOhm ± 5% to ground connected to USB_DP and USB_DM.

43

t _OSCS is defined from the moment the oscillator is enabled with SCU_OSCHPCTRL.MODE until the oscillations reach an amplitude at XTAL1 of 0.4 * V _DDP .

44

The external oscillator circuitry must be optimized by the customer and checked for negative resistance and amplitude as recommended and specified by crystal suppliers.

45

If the shaper unit is enabled and not bypassed.

46

If the shaper unit is bypassed, dedicated DC-thresholds have to be met.

47

t _OSCS is defined from the moment the oscillator is enabled by the user with SCU_OSCULCTRL.MODE until the oscillations reach an amplitude at RTC_XTAL1 of 400 mV.

48

The external oscillator circuitry must be optimized by the customer and checked for negative resistance and amplitude as recommended and specified by crystal suppliers.

49

For a reliable start of the oscillation in crystal mode it is required that V _BAT ≥ 3.0 V. A running oscillation is maintained across the full V _BAT voltage range.

50

If the shaper unit is enabled and not bypassed.

51

If the shaper unit is bypassed, dedicated DC-thresholds have to be met.

52

Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not be guaranteed that it suppresses switching due to external system noise.

53

CPU executing code from Flash, all peripherals idle.

54

CPU executing code from Flash. Ethernet, USB and CCU clock off.

55

CPU in sleep, all peripherals idle, Flash in Active mode.

56

CPU in sleep, Flash in Active mode.

57

CPU in sleep, peripherals disabled, after wake-up code execution from RAM.

58

To wake-up the Flash from its Sleep mode, f _CPU ≥ 1 MHz is required.

59

OSC_ULP operating with external crystal on RTC_XTAL

60

OSC_ULP off, Hibernate domain operating with OSC_SI clock

61

Test Power Loop: f _SYS = 120 MHz, CPU executing benchmark code from Flash, all CCUs in 100kHz timer mode, all ADC groups in continuous conversion mode, USICs as SPI in internal loop-back mode, CAN in 500kHz internal loop-back mode, interrupt triggered DMA block transfers to parity protected RAMs and FCE, DTS measurements and FPU calculations.

The power consumption of each customer application will most probably be lower than this value, but must be evaluated separately.

62

I _DDP decreases typically by 5 mA when f _SYS decreases by 10 MHz, at constant T _J

63

Sum of currents of all active converters (ADC and DAC)

64

The current consumption of the analog components are given in the dedicated Datasheet sections of the respective peripheral.

65

In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes an additional time of 5.5 ms.

66

The following formula applies to the wait state configuration: FCON.WSPFLASH × (1 / f _CPU ) ≥ t _a .

67

Storage and inactive time included.

68

Values given are valid for an average weighted junction temperature of T _J = 110°C.

69

Only valid with robust EEPROM emulation algorithm, equally cycling the logical sectors. For more details see the Reference Manual.

70

Minimum threshold for reset assertion.

71

Maximum threshold for reset deassertion.

72

The V _DDP monitoring has a typical hysteresis of V _PORHYS = 180 mV.

73

50% for even K2 divider values, 50±(10/K2) for odd K2 divider values.

74

Error in addition to the accuracy of the reference clock.

75

Automatic calibration compensates variations of the temperature and in the V _DDP supply voltage.

76

Deviations from the nominal V _DDP voltage induce an additional error to the uncalibrated and/or factory calibrated oscillator frequency.

77

The falling edge on TCK is used to generate the TDO timing.

78

The setup time for TDO is given implicitly by the TCK cycle time.

79

t _PERIPH = 1 / f _PERIPH

80

t _SYS = 1 / f _PB

81

These input timing are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0).

82

Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximately 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

83

Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximately 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

84

C _b refers to the total capacitance of one bus line in pF.

85

Device mounted on a 4-layer JEDEC board (JESD 51-7) with thermal vias; exposed pad soldered.