CYT2B7 TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Datasheet

General description

Infineon's TRAVEO™ T2G 32-bit Automotive MCU is a high-performance, low-power controller designed for automotive applications, compliant to ISO 26262 for functional safety and ISO 21434 for cybersecurity. CYT2B7 is a family of TRAVEO™ T2G microcontrollers targeted at automotive systems such as body control units. CYT2B7 has an Arm® Cortex®-M4F CPU for primary processing, and an Arm® Cortex®-M0+ CPU for peripheral and security processing. These devices contain embedded peripherals supporting Controller Area Network with Flexible Data rate (CAN FD), and Local Interconnect Network (LIN). TRAVEO™ T2G devices are manufactured on an advanced 40-nm process. CYT2B7 incorporates a low-power flash memory, multiple high-performance analog and digital peripherals, and enables the creation of a secure computing platform.

Features

Dual CPU subsystem
- 160-MHz (max) 32-bit Arm® Cortex®-M4F CPU with
  - Single-cycle multiply
  - Single-precision floating point unit (FPU)
  - Memory protection unit (MPU)
- 100-MHz (max) 32-bit Arm® Cortex®-M0+ CPU with
  - Single-cycle multiply
  - Memory Protection Unit
- Inter-processor communication in hardware
- Three DMA controllers
  - Peripheral DMA controller #0 (P-DMA0) with 89 channels
  - Peripheral DMA controller #1 (P-DMA1) with 33 channels
  - Memory DMA controller #0 (M-DMA0) with 4 channels
Integrated memories
- 1088 KB of code-flash with an additional 96 KB of work-flash
  - Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it
  - Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])
  - Flash programming through SWD/JTAG interface
- 128 KB of SRAM with selectable retention granularity
ISO 21434 compliant / EVITA Full¹
- Supports enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
- Secure boot and authentication
  - Using digital signature verification
  - Using fast secure boot
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES: 64-bit blocks, 64-bit key
- Vector unit ² supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve (ECC)
- SHA-1/2/3 ² : SHA-512, SHA-256, SHA-160 with variable length input data
- CRC ² : supports CCITT CRC16 and IEEE-802.3 CRC32
- True random number generator (TRNG) and pseudo random number generator (PRNG)
- Galois/Counter Mode (GCM)
ISO 26262 functional safety compliant for ASIL-B
- Memory protection unit (MPU)
- Shared memory protection unit (SMPU)
- Peripheral protection unit (PPU)
- Watchdog timer (WDT)
- Multi-counter watchdog timer (MCWDT)
- Low-voltage detector (LVD)
- Brown-out detector (BOD)
- Overvoltage detection (OVD)
- Clock supervisor (CSV)
- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash)
Low-power 2.7-v to 5.5-v operation
- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power management
- Configurable options for robust BOD
  - Two threshold levels (2.7 V and 3.0 V) for BOD on V _DDD and V _DDA
  - One threshold level (1.1 V) for BOD on V _CCD
Wakeup support
- Up to two pins to wakeup from Hibernate mode
- Up to 152 GPIO pins to wakeup from Sleep modes
- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes
Clock sources
- Internal main oscillator (IMO)
- Internal low-speed oscillator (ILO)
- External crystal oscillator (ECO)
- Watch crystal oscillator (WCO)
- Phase-locked loop (PLL)
- Frequency-locked loop (FLL)
Communication interfaces
- Up to six CAN FD channels
  - Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and transceivers
  - Compliant to ISO 11898-1:2015
  - Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD
  - ISO 16845:2015 certificate available
- Up to eight runtime-reconfigurable SCB (serial communication block) channels, each configurable as I ² C, SPI, or UART
- Up to eight independent LIN channels
  - LIN protocol compliant with ISO 17987
Timers
- Up to 75 16-bit and four 32-bit timer/counter pulse-width modulator (TCPWM) blocks
  - Up to 12 16-bit counters for motor control
  - Up to 63 16-bit counters and four 32-bit counters for regular operations
  - Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time (PWM_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes
- Up to 11 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep
  - Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion, and so on)
Real time clock (RTC)
- Year/Month/Date, Day-of-week, Hour:Minute:Second fields
- 12- and 24-hour formats
- Automatic leap-year correction
I/O
- Up to 152 Programmable I/Os
- Two I/O types
  - GPIO Standard (GPIO_STD)
  - GPIO Enhanced (GPIO_ENH)
Regulators
- Generates 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply
- Two types of regulators
  - DeepSleep
  - Core internal
Programmable analog
- Three SAR A/D converters with up to 67 external channels (64 I/Os + 3 I/Os for motor control)
  - ADC0 supports 24 logical channels, with 24 + 1 physical connections
  - ADC1 supports 32 logical channels, with 32 + 1 physical connections
  - ADC2 supports 8 logical channels, with 8 + 1 physical connections
  - Any external channel can be connected to any logical channel in the respective SAR
- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps
- Each ADC also supports up to six internal analog inputs like
  - Bandgap reference to establish absolute voltage levels
  - Calibrated diode for junction temperature calculations
  - Two AMUXBUS inputs and two direct connections to monitor supply levels
- Each ADC supports addressing of external multiplexers
- Each ADC has a sequencer supporting autonomous scanning of configured channels
- Synchronized sampling of all ADCs for motor-sense applications
Smart I/O
- Up to five Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os
- Up to 36 I/Os (GPIO_STD) supported
Debug interface
- JTAG controller and interface compliant to IEEE-1149.1-2001
- Arm® SWD (Serial Wire Debug) port
- Supports Arm® Embedded Trace Macrocell (ETM) Trace
  - Data trace using SWD
  - Instruction and data trace using JTAG
Compatible with industry-standard tools
- GHS/MULTI or IAR EWARM for code development and debugging
Packages
- 64-LQFP, 10 × 10 × 1.7 mm (max), 0.5-mm lead pitch
- 80-LQFP, 12 × 12 × 1.7 mm (max). 0.5-mm lead pitch
- 100-LQFP, 14 × 14 × 1.7 mm (max), 0.5-mm lead pitch
- 144-LQFP, 20 × 20 × 1.7 mm (max), 0.5-mm lead pitch
- 176-LQFP, 24 × 24 × 1.7 mm (max), 0.5-mm lead pitch
Certification
- Qualified for automotive application according to AEC-Q100

Features list

Table 1.
CYT2B7 feature list for all packages
Features	Packages
Features	64-LQFP	80-LQFP	100-LQFP	144-LQFP	176-LQFP
CPU
Core	32-bit Arm® Cortex®-M4F CPU and 32-bit Arm® Cortex®-M0+ CPU
Functional safety	ISO 26262 ASIL-B compliant
Operating voltage	2.7 V to 5.5 V
Core voltage	1.05 V to 1.15 V
Operating frequency	Arm® Cortex®-M4F 160 MHz (max) and Arm® Cortex®-M0+ 100 MHz (max), related by integer frequency ratio (that is, 1:1, 1:2, 1:3, and so on)
MPU, PPU	Supported
FPU	Single precision (32-bit)
DSP-MUL/DIV/MAC	Supported by Arm® Cortex®-M4F CPU
Memory
Code-flash	1088 KB (960 KB + 128 KB)
Work-flash	96 KB (72 KB + 24 KB)
SRAM (configurable for retention)	128 KB
ROM	32 KB
Communication Interfaces
CAN0 (CAN FD: Up to 8 Mbps)	3 ch
CAN1 (CAN FD: Up to 8 Mbps)	2 ch	3 ch
CAN RAM	24 KB per instance (3 ch), 48 KB in total
Serial communication block (SCB/UART)	7 ch	8 ch
Serial communication block (SCB/I ² C)	6 ch		8 ch
Serial communication block (SCB/SPI)	3 ch	6 ch	8 ch
LIN0	6 ch	7 ch		8 ch
Timers
RTC	1 ch
TCPWM (16-bit) (Motor Control)	12 ch
TCPWM (16-bit)	63 ch
TCPWM (32-bit)	4 ch
External Interrupts	49	63	78	122	152
Analog
12-bit, 1 Msps SAR ADC	3 units (SAR0/24, SAR1/32, SAR2/8 logical channels)
	27 external channels (SAR0 11 ch, SAR1 9 ch, SAR2 7 ch)	34 external channels (SAR0 12 ch, SAR1 14 ch, SAR2 8 ch)	39 external channels (SAR0 14 ch, SAR1 17 ch, SAR2 8 ch)	54 external channels (SAR0 21 ch, SAR1 25 ch, SAR2 8 ch)	64 external channels (SAR0 24 ch, SAR1 32 ch, SAR2 8 ch)
	18 ch (6 per ADC) Internal sampling
Motor Control Input	3 ch (synchronous sampling of one channel on each of the 3 ADCs)
Security - ISO 21434 compliant
Flash Security (program/work read protection)	Supported
Flash Chip erase enable	Configurable
eSHE/HSM	By separate firmware ³
System
DMA Controller	P-DMA0 with 89 channels (16 general purpose), P-DMA1 with 33 channels (8 general purpose), and M-DMA0 with 4 channels
Internal main oscillator	8 MHz
Internal low-speed oscillator	32.768 kHz (nominal)
PLL	Input frequency: 3.988 to 33.34 MHz, PLL output frequency: up to 160 MHz
FLL	Input frequency: 0.25 to 80 MHz, FLL output frequency: up to 100 MHz
Watchdog timer and multi-counter watchdog timer	Supported (WDT + 2× MCWDT) MCWDT#0 tied to CM0+, MCWDT#1 to CM4
Clock supervisor	Supported
Cyclic wakeup from DeepSleep	Supported
GPIO_STD	45	59	74	118	148
GPIO_ENH	4
Smart I/O (Blocks)	3 blocks, 9 I/Os	3 blocks, 14 I/Os	4 blocks, 20 I/Os	5 blocks, 29 I/Os	5 blocks, 36 I/Os
Low-voltage detect	Two, 26 selectable levels
Maximum ambient temperature	105°C for S-grade and 125°C for E-grade
Debug interface	SWD/JTAG
Debug trace	Arm® Cortex®-M4F ETB size of 8 KB, Arm® Cortex®-M0+ MTB size of 4 KB

Communication peripheral instance list

The following table lists the instances supported under each package for communication peripherals, based on the minimum pins needed for the functionality.

Table 2.
Peripheral instance list
Module	64-LQFP	80-LQFP	100-LQFP	144-LQFP	176-LQFP	Minimum pin functions
CAN0	0/1/2	0/1/2	0/1/2	0/1/2	0/1/2	TX, RX
CAN1	0/2	0/1/2	0/1/2	0/1/2	0/1/2	TX, RX
LIN0	0/1/2/3/4/7	0/1/2/3/4/6/7	0/1/2/3/4/6/7	0/1/2/3/4/5/6/7	0/1/2/3/4/5/6/7	TX, RX
SCB/UART	0/1/2/3/4/5/7	0/1/2/3/4/5/6/7	0/1/2/3/4/5/6/7	0/1/2/3/4/5/6/7	0/1/2/3/4/5/6/7	TX, RX
SCB/I ² C	0/2/3/4/5/7	0/1/3/4/5/7	0/1/2/3/4/5/6/7	0/1/2/3/4/5/6/7	0/1/2/3/4/5/6/7	SCL, SDA
SCB/SPI	0/3/4	0/1/3/4/5/7	0/1/2/3/4/5/6/7	0/1/2/3/4/5/6/7	0/1/2/3/4/5/6/7	MISO, MOSI, SCK, SELECT0

Blocks and functionality

Block diagram

The Figure 1 shows the CYT2B7 architecture, giving a simplified view of the interconnection between subsystems and blocks. CYT2B7 has four major subsystems: CPU, system resources, peripherals, and I/O ⁴ , ⁵ . The color-coding shows the lowest power mode where the particular block is still functional.

CYT2B7 provides extensive support for programming, testing, debugging, and tracing of both hardware and firmware.

Debug-on-chip functionality enables in-system debugging using the production device. It does not require special interfaces, debugging pods, simulators, or emulators.

The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet, J-Link, and GHS.

The debug circuits are enabled by default.

CYT2B7 provides a high level of security with robust flash protection and the ability to disable features such as debug.

Additionally, each device interface can be permanently disabled for applications concerned with phishing attacks from a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled.

Functional description

CPU subsystem

CPU

The CYT2B7 CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU, and a 32-bit Arm® Cortex®-M4F CPU with MPU, and single-precision FPU. This subsystem also includes P-/M-DMA controllers, a cryptographic accelerator, 1088 KB of code-flash, 96 KB of work-flash, 128 KB of SRAM, and 32 KB of ROM.

The Cortex®-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash, SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by an inter-processor communication (IPC) mechanism using hardware semaphores.

DMA controllers

CYT2B7 has three DMA controllers: P-DMA0 with 16 general-purpose and 73 dedicated channels, P-DMA1 with 8 general-purpose and 25 dedicated channels, and M-DMA0 with four channels. P-DMA is used for peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels. General purpose channels have a rich interconnect matrix including P-DMA cross triggering which enables demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel) to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each channel. They support independent accesses to peripherals using the AHB multi-layer bus.

Flash

CYT2B7 has 1088 KB (960 KB with a 32-KB sector size, and 128 KB with an 8-KB sector size) of code-flash with an additional work-flash of up to 96 KB (72 KB with 2-KB sector size, and 24 KB with 128-B sectors size). Work-flash is optimized for reprogramming many more times than code-flash. Code-flash supports Read-While-Write (RWW) operation allowing flash to be updated while the CPU is active. Both the code-flash and work-flash areas support dual-bank operation for over-the-air (OTA) programming.

SRAM

CYT2B7 has 128 KB of SRAM with two independent controllers. The first controller, SRAM0, provides DeepSleep retention in 32-KB increments, while SRAM1 is selectable between fully retained and not retained.

ROM

CYT2B7 has 32-KB ROM that contains boot and configuration routines. This ROM enables secure boot and authentication of user flash to guarantee a secure system.

Cryptography accelerator for security

The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy check, pseudo random number generation, true random number generation, galois/counter mode, and a vector unit to support asymmetric key cryptography such as RSA and ECC.

Depending on the part number, this block is either completely or partially available or not available at all. See Ordering information for more details.

System resources

Power system

The power system ensures that the supply voltage levels meet the requirements of each power mode, and provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip reset during the initial power ramp.

Three Brown-Out Detection (BOD) circuits monitor the external supply voltages (V _DDD , V _DDA , V _CCD ). The BOD on V _DDD and V _CCD are initially enabled and cannot be disabled. The BOD on V _DDA is initially disabled and can be enabled by the user. For the external supplies V _DDD and V _DDA , BOD circuits are software configurable with two settings; a 2.7-V minimum voltage that is robust for all internal signaling and a 3.0-V minimum voltage, which is also robust for all I/O specifications (which are guaranteed at 2.7 V). The BOD on V _CCD is provided as a safety measure and is not a robust detector.

Three overvoltage detection (OVD) circuits are provided for monitoring external supplies (V _DDD , V _DDA , V _CCD ), and overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on V _DDD and V _DDA are configurable with two settings; a 5.0-V and 5.5-V maximum voltage. Two voltage-detection circuits are provided to monitor the external supply voltage (V _DDD ) for falling and rising levels, each configurable for one of the 26 selectable levels.

All BOD, OVD, and OCD circuits on V _DDD and V _CCD generate a reset, because these protect the CPUs and fault logic. The BOD and OVD circuits on V _DDA can be configured to generate either a reset, or a fault.

Regulators

CYT2B7 contains two regulators that provide power to the low-voltage core transistors: DeepSleep and core internal. These regulators accept a 2.7–5.5-V V _DDD supply and provide a low-noise 1.1-V supply to various parts of the device. These regulators are automatically enabled and disabled by hardware and firmware when switching between power modes. The core internal and core external regulators operate in active mode, and provide power to the CPU subsystem and associated peripherals.

DeepSleep

The DeepSleep regulator is used to maintain power to a small number of blocks when in DeepSleep mode. These blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other configuration memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal regulator is disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is disabled.

Core internal

The core internal regulator supports load currents up to 150 mA, and is operational during the device start-up (boot process), and in Active/Sleep modes.

Clock system

The CYT2B7 clock system provides clocks to all subsystems that require them, and glitch-free switching between different clock sources. In addition, the clock system ensures that no metastable conditions occur.

The clock system for CYT2B7 consists of the 8-MHz IMO, two ILOs, three watchdog timers, a PLL, an FLL, five clock supervisors (CSV), a 3.988- to 33.34 MHz ECO, and a 32.768-kHz WCO.

The clock system supports two main clock domains: CLK_HF, and CLK_LF.

CLK_HFx are the Active mode clocks. Each can use any of the high frequency clock sources including IMO, EXT_CLK, ECO, FLL, or PLL
CLK_LF is a DeepSleep domain clock and provides a reference clock for the MCWDT or RTC modules. The reference clock for the CLK_LF domain is either disabled or selectable from ILO0, ILO1, or WCO

Table 3.
CLK_HF destinations
Name	Description
CLK_HF0	CPUSS clocks, PERI, and AHB infrastructure
CLK_HF1	Event Generator, also available in HSIOM as an output

IMO clock source

The IMO is the frequency reference in CYT2B7 when no external reference is available or enabled. The IMO operates at a frequency of around 8 MHz.

ILO clock source

An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks for a watchdog timer when in DeepSleep mode. There are two ILOs to ensure clock supervisor (CSV) capability in DeepSleep mode. ILO-driven counters can be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also used for clock supervision.

PLL and FLL

A PLL or FLL may be used to generate high-speed clocks from the IMO, the ECO, or EXT_CLK. The FLL provides a much faster lock than the PLL (5 µs instead of 35 µs) in exchange for a small amount of frequency error ⁶ .

Clock supervisor (CSV)

Each CSV allows one clock (reference) to supervise the behavior of another clock (monitored). Each CSV has counters for both the monitored and reference clocks. Parameters for each counter determine the frequency of the reference clock as well as the upper and lower frequency limits of the monitored clock. If the frequency range comparator detects a stopped clock or a clock outside the specified frequency range, an abnormal state is signaled and either a reset or an interrupt is generated.

EXT_CLK

One of the two GPIO_STD I/Os can be used to provide an external clock input of up to 80 MHz. This clock can be used as the source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain.

ECO

The ECO provides high-frequency clocking using an external crystal connected to the ECO_IN and ECO_OUT pins. It supports fundamental mode (non-overtone) quartz crystals, in the range of 3.988 to 33.34 MHz. When used in conjunction with the PLL, it generates CPU and peripheral clocks up to device’s maximum frequency. ECO accuracy depends on the selected crystal. If the ECO is disabled, the associated pins can be used for any of the available I/O functions.

WCO

The WCO is a low-power, watch-crystal oscillator intended for real-time-clock applications. It requires an external 32.768-kHz crystal connected to the WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock reference for CLK_LF, which is the clock source for the MCWDT and RTC.

Reset

CYT2B7 can be reset from a variety of sources, including software. Reset events are asynchronous and guarantee reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT, software reset, fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES_L pin is available for external reset.

Watchdog timers

CYT2B7 has one watchdog timer (WDT) and two multi-counter watchdog timers (MCWDT).

The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from Hibernate. Watchdog operation is possible during all power modes. To prevent a device reset from a WDT timeout, the WDT must be serviced during a configured window. A watchdog reset is recorded in the reset cause register.

An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are only available in Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.

Power modes

CYT2B7 has the following six power modes:

Active – all peripherals are available
Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are available, but with limited capability
Sleep – all peripherals except the CPUs are available
Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are available, but with limited capability
DeepSleep – only peripherals which work with CLK_LF are available
Hibernate – the device and I/O states are frozen, the device resets on wakeup

Peripherals

Peripheral clock dividers

Integer and fractional clock dividers are provided for peripheral and timing purposes.

Table 4.
Clock dividers
Divider	Count	Description
div_8	32	Integer divider, 8 bits
div_16	16	Integer divider, 16 bits
div_24_5	8	Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)

Peripheral protection unit

The Peripheral Protection Unit (PPU) controls and monitors unauthorized access from all masters (CPU, P-/M-DMA, Crypto, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on the bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).

12-bit SAR ADC

CYT2B7 contains three 1-Msps SAR ADCs. These ADCs can be clocked at up to 26.67 MHz and provide a 12-bit result in 26 clock cycles.

The references for all three SAR ADCs come from a dedicated pair of inputs: VREFH and VREFL ⁷ .

CYT2B7 devices support up to 85 logical ADC channels, and external inputs from up to 67 I/Os. Each ADC also supports six internal connections for diagnostic and monitoring purposes. The number of ADC channels (per ADC and package type) are listed in Table 1 .

Each ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching is controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates subsequent conversions for repetitive or group conversions without CPU intervention.

Each SAR ADC has an analog multiplexer used to connect the signals to be measured to the ADC. It has 32 GPIO_STD inputs, one special GPIO_STD input for motor-sense, and six additional inputs to measure internal signals such as a band-gap reference, a temperature sensor, and power supplies. The device supports synchronous sampling of one motor-sense channel on each of the three ADCs.

CYT2B7 has one temperature sensor that is shared by all three ADCs. The temperature sensor must only be sampled by one ADC at a time. Software post processing is required to convert the temperature sensor reading into kelvin or Celsius values.

To accommodate signals with varying source impedances and frequencies, it is possible to have different sample times programmed for each channel. Each ADC also supports range comparison, which allows fast detection of out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate the measurement for out-of-range values.

The ADCs are not usable in DeepSleep and Hibernate modes as they require a high-speed clock. The ADC input reference voltage VREFH range is 2.7 V to V _DDA and VREFL is V _SSA .

Timer/counter/PWM block (TCPWM)

The TCPWM block consists of 16-bit (75 channels) and 32-bit (four channels) counters with a user-programmable period. Twelve of the 16-bit counters include extra features to support motor control operations. Each TCPWM counter contains a capture register to record the count at the time of an event, a period register (used to either stop or auto-reload the counter when its count is equal to the period register), and compare registers to generate signals that are used as PWM duty-cycle outputs.

Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature, PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.

In motor-control applications, the counter within the TCPWM block supports enhanced quadrature mode with features such as asymmetric PWM generation, dead-time insertion (16-bit), and association of different dead times for PWM output signals.

The TCPWM block also provides true and complement outputs, with programmable offset between them, to allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time for software intervention).

Serial communication blocks (SCB)

CYT2B7 contains eight serial communication blocks, each configurable to support I ² C, UART, or SPI.

I ² C interface

An SCB can be configured to implement a full I ² C master (capable of multi-master arbitration) or slave interface. Each SCB configured for I ² C can operate at speeds of up to 1 Mbps (Fast-mode Plus ⁸ ) and has flexible buffering options to reduce the interrupt overhead and latency of the CPU. In addition, each SCB supports FIFO buffering for receive and transmit data, which, by increasing the time for the CPU to read the data, reduces the need for clock stretching. The I ² C interface is compatible with Standard, Fast-mode, and Fast-mode Plus devices as specified in the NXP I ² C-bus specification and user manual (UM10204). The I ² C-bus I/O is implemented with GPIO in open-drain modes ⁹ , ¹⁰ .

UART interface

When configured as a UART, each SCB provides a full-featured UART with maximum signaling rate determined by the configured peripheral-clock frequency and over-sampling rate. It supports infrared interface (IrDA) and SmartCard (ISO 7816) protocols, which are minor variants of the UART protocol. It also supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines. Common UART functions such as parity, number of stop bits, break detect, and frame error are supported. FIFO buffering of transmit and receive data allows greater CPU service latencies to be tolerated.

The LIN protocol is supported by the UART. LIN is based on a single-master multi-slave topology. There is one master node and multiple slave nodes on the LIN bus. The SCB UART supports only LIN slave functionality. Compared to the dedicated LIN blocks, an SCB/UART used for LIN requires a higher level of software interaction and increased CPU load.

SPI interface

The SPI configuration supports full Motorola SPI, TI Synchronous Serial Protocol (SSP, essentially adds a start pulse that is used to synchronize SPI-based codecs), and National Microwire (a half-duplex form of SPI). The SPI interface can use the FIFO. The SPI interface operates with up to a 12.5-MHz SPI Clock. SCB also supports EZSPI ¹¹ mode.

SCB0 supports the following additional features:

Operable as a slave in DeepSleep mode
I ² C slave EZ (EZI2C ¹² ) mode with up to 256-B data buffer for multi-byte communication without CPU intervention
I ² C slave externally-clocked operations
Command/response mode with a 512-B data buffer for multi-byte communication without CPU intervention

CAN FD

CYT2B7 supports two CAN FD controller blocks, each supporting three CAN FD channels. All CAN FD controllers are compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in hardware.

All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx handler manages message acceptance filtering, transfer of received messages from the CAN core to a message RAM, and provides receive-message status. The Tx handler is responsible for the transfer of transmit messages from the message RAM, to the CAN core, and provides transmit-message status.

Local interconnect network (LIN)

CYT2B7 contains up to eight LIN channels. Each channel supports transmission/reception of data following the LIN protocol according to ISO standard 17987. Each LIN channel connects to an external transceiver through a 3-pin interface (including an enable function) and supports master and slave functionality. Each channel also supports classic and enhanced checksum, along with break detection during message reception and wake-up signaling. Break detection, sync field, checksum calculations, and error interrupts are handled in hardware.

One-time-programmable (OTP) eFuse

CYT2B7 contains a 1024-bit OTP eFuse memory that can be used to store and access a unique and unalterable identifier or serial number for each device. eFuses are also used to control the device life-cycle (manufacturing, programming, normal operation, end-of-life, and so on) and the security state. Of the 1024 bits, 192 are available for user purposes.

Event generator

The event generator supports generation of interrupts and triggers in Active mode and interrupts in DeepSleep mode. The event generators are used to trigger a specific device operation (execution of an interrupt handler, a SAR ADC conversion, and so on) and to provide a cyclic wakeup mechanism from DeepSleep mode. They provide CPU-free triggers for device functions, and reduce CPU involvement in triggering device functions, thus reducing overall power consumption and processing overhead.

Trigger multiplexer

CYT2B7 supports connecting various peripherals using trigger signals. Triggers are used to inform a peripheral of the occurrence of an event or change of state. These triggers are used to affect or initiate some action in other peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a destination. Triggers provide active logic functionality and are typically supported in Active mode.

I/Os

CYT2B7 has up to 152 programmable I/Os.

The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on, and reset, the I/Os are forced to the High-Z state. During the Hibernate mode, I/Os are frozen.

Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service routine (ISR) associated with it.

I/O port power source mapping is listed in Table 5 . The associated supply determines the V _OH , V _OL , V _IH , and V _IL levels when configured for CMOS and Automotive thresholds.

Table 5.
I/O port power source
Supply	Ports
VDDD	P0, P1, P2, P3, P4, P5, P16, P17, P18, P19, P20, P21, P22, P23
VDDIO_1	P6, P7, P8, P9 ¹³
VDDIO_2	P10, P11, P12, P13, P14, P15

Port nomenclature

Px.y describes a particular bit “y” available within an I/O port “x.”

For example, P4.2 reads “port 4, bit 2”.

Each I/O implements the following:

Programmable drive mode
- High impedance
- Resistive pull-up
- Resistive pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up or pull-down
- Weak pull-up or pull-down

CYT2B7 has two types of programmable I/Os: GPIO standard and GPIO Enhanced.

GPIO Standard (GPIO_STD)

Supports standard automotive signaling across the 2.7-V to 5.5-V V _DDIO range. GPIO Standard I/Os have multiple configurable drive levels, drive modes, and selectable input levels.

GPIO Enhanced (GPIO_ENH)

Supports extended functionality automotive signaling across the 2.7-V to 5.5-V V _DDIO range with higher currents at lower voltages (full I ² C timing support, slew-rate control).

Both GPIO_STD and GPIO_ENH implement the following:

Configurable input threshold (CMOS, TTL, or Automotive)
Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)
Analog input mode (input and output buffers disabled)

Smart I/O

Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals coming into the chip. CYT2B7 has five Smart I/O blocks. Operation can be synchronous or asynchronous and the blocks operate in all device power modes except for the Hibernate mode.

CYT2B7 address map

The CYT2B7 microcontroller supports the memory spaces shown in Figure 2 .

1088KB (960KB + 128KB) of code-flash, used in the single- or dual-bank mode based on the associated bit in the flash control register
- Single-bank mode - 1088KB
- Dual-bank mode - 544KB per bank
96KB (72KB + 24KB) of work-flash, used in the single- or dual-bank mode based on the associated bit in the flash control register
- Single-bank mode - 96KB
- Dual-bank mode - 48KB per bank
32KB of secure ROM
128KB of SRAM (First 2 KB is reserved for internal usage)

Flash base address map

Table 6 through Table 11 give information about the sector mapping of the code- and work-flash regions along with their respective base addresses.

Table 6.
Code-flash Address Mapping in Single Bank Mode
Code-flash Size (KB)	Large Sectors (LS)	Small Sectors (SS)	Large Sector Base Address	Small Sector Base Address
1088	32KB × 30	8KB × 16	0x1000 0000	0x100F 0000

Table 7.
Work-flash Address Mapping in Single Bank Mode
Work-flash Size (KB)	Large Sectors	Small Sectors	Large Sector Base Address	Small Sector Base Address
96	2KB × 36	128 B × 192	0x1400 0000	0x1401 2000

Table 8.
Code-flash Address Mapping in Dual Bank Mode (Mapping A)
Code-flash Size (KB)	First Half LS	First Half SS	Second Half LS	Second Half SS	First Half LS Base Address	First Half SS Base Address	Second Half LS Base Address	Second Half SS Base Address
1088	32KB × 15	8KB × 8	32KB × 15	8KB × 8	0x1000 0000	0x1007 8000	0x1200 0000	0x1207 8000

Table 9.
Code-flash Address Mapping in Dual Bank Mode (Mapping B)
Code-flash Size (KB)	First Half LS	First Half SS	Second Half LS	Second Half SS	First Half LS Base Address	First Half SS Base Address	Second Half LS Base Address	Second Half SS Base Address
1088	32KB × 15	8KB × 8	32KB × 15	8KB × 8	0x1200 0000	0x1207 8000	0x1000 0000	0x1007 8000

Table 10.
Work-flash Address Mapping in Dual Bank Mode (Mapping A)
Work-flash Size (KB)	First Half LS	First Half SS	Second Half LS	Second Half SS	First Half LS Base Address	First Half SS Base Address	Second Half LS Base Address	Second Half SS Base Address
96	2KB × 18	128 B × 96	2KB × 18	128 B × 96	0x1400 0000	0x1400 9000	0x1500 0000	0x1500 9000

Table 11.
Work-flash Address Mapping in Dual Bank Mode (Mapping B)
Work-flash Size (KB)	First Half LS	First Half SS	Second Half LS	Second Half SS	First Half LS Base Address	First Half SS Base Address	Second Half LS Base Address	Second Half SS Base Address
96	2KB × 18	128 B × 96	2KB × 18	128 B × 96	0x1500 0000	0x1500 9000	0x1400 0000	0x1400 9000

Peripheral I/O map

Table 12.
CYT2B7 peripheral I/O map
Section	Description	Base Address	Instances	Instance Size	Group	Slave
PERI	Peripheral interconnect	0x4000 0000			0	0
	Peripheral group (0, 1, 2, 3, 5, 6, 9)	0x4000 4000	7	0x20
	Peripheral trigger group	0x4000 8000	11	0x400
	Peripheral 1:1 trigger group	0x4000 C000	11	0x400
PERI_MS	Peripheral interconnect, master interface	0x4001 0000			0	1
	PERI Programmable PPU	0x4001 0000	6 ¹⁶	0x40
	PERI Fixed PPU	0x4001 0800	458	0x40
Crypto	Cryptography component	0x4010 0000			1	0
CPUSS	CPU subsystem (CPUSS)	0x4020 0000			2	0
FAULT	Fault structure subsystem	0x4021 0000			2	1
FAULT	Fault structures	0x4021 0000	4	0x100	2	1
IPC	Inter process communication	0x4022 0000			2	2
	IPC structures	0x4022 0000	8	0x20
	IPC interrupt structures	0x4022 1000	8	0x20
PROT	Protection	0x4023 0000			2	3
	Shared memory protection unit structures	0x4023 2000	16	0x40
	Memory protection unit structures	0x4023 4000	16	0x400
FLASHC	Flash controller	0x4024 0000			2	4
SRSS	System Resources Subsystem Core Registers	0x4026 0000			2	5
	Clock Supervision High Frequency	0x4026 1400	3	0x10
	Clock Supervision Reference Frequency	0x4026 1710	1
	Clock Supervision Low Frequency	0x4026 1720	1
	Clock Supervision Internal Low Frequency	0x4026 1730	1
	Multi Counter WDT	0x4026 8000	2	0x100
	Free Running WDT	0x4026 C000	1
BACKUP	SRSS Backup Domain/RTC	0x4027 0000			2	6
BACKUP	Backup Register	0x4027 1000	4	0x04	2	6
P-DMA	P-DMA0 Controller	0x4028 0000			2	7
	P-DMA0 channel structures	0x4028 8000	89	0x40	2	7
	P-DMA1 Controller	0x4029 0000			2	8
	P-DMA1 channel structures	0x4029 8000	33	0x40	2	8
M-DMA	M-DMA0 Controller	0x402A 0000			2	9
M-DMA	M-DMA0 channels	0x402A 1000	4	0x100	2	9
eFUSE	eFUSE Customer Data (192 bits)	0x402C 0868	6	0x04	2	10
HSIOM	High-Speed I/O Matrix (HSIOM)	0x4030 0000	24	0x10	3	0
GPIO	GPIO port control/configuration	0x4031 0000	24	0x80	3	1
SMARTIO	Programmable I/O configuration	0x4032 0000			3	2
SMARTIO	SMARTIO port configuration	0x4032 0C00	5	0x100	3	2
TCPWM	Timer/Counter/PWM 0 (TCPWM0)	0x4038 0000			3	3
	TCPWM0 Group #0 (16-bit)	0x4038 0000	63	0x80
	TCPWM0 Group #1 (16-bit, Motor control)	0x4038 8000	12	0x80
	TCPWM0 Group #2 (32-bit)	0x4039 0000	4	0x80
EVTGEN	Event generator 0 (EVTGEN0)	0x403F 0000			3	4
EVTGEN	Event generator 0 comparator structures	0x403F 0800	11	0x20	3	4
LIN	Local Interconnect Network 0 (LIN0)	0x4050 0000			5	0
LIN	LIN0 Channels	0x4050 8000	8	0x100	5	0
TTCANFD	CAN0 controller	0x4052 0000	3	0x200	5	1
	Message RAM CAN0	0x4053 0000		0x6000	5	1
	CAN1 controller	0x4054 0000	3	0x200	5	2
	Message RAM CAN1	0x4055 0000		0x6000	5	2
SCB	Serial Communications Block (SPI/UART/I ² C)	0x4060 0000	8	0x10000	6	0-7
PASS0 SAR	Programmable Analog Subsystem (PASS0)	0x4090 0000			9	0
	SAR0 channel controller	0x4090 0000
	SAR1 channel controller	0x4090 1000
	SAR2 channel controller	0x4090 2000
	SAR0 channel structures	0x4090 0800	24	0x40
	SAR1 channel structures	0x4090 1800	32	0x40
	SAR2 channel structures	0x4090 2800	8	0x40

CYT2B7 clock diagram

CYT2B7 CPU start-up sequence

The start-up sequence is described in the following steps:

System Reset (@0x0000 0000)
CM0+ executes ROM boot (@0x0000 0004)
1. Applies trims
2. Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisory flash
3. Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it
CM0+ executes flash boot (from Supervisory flash @0x1700 2000)
1. Debug pins are configured as per the SWD/JTAG spec ¹⁷
2. Sets CM0+ Vector Table Base Register (CPUSS_CM0_VECTOR_TABLE_BASE - part of CPU Subsystem) to the beginning of flash (@0x1000 0000)
3. CM0+ branches to its Reset handler
CM0+ starts execution
1. Moves CM0+ vector table to SRAM (updates CM0+ vector table base)
2. Sets CM4_VECTOR_TABLE_BASE (@0x0000 0200) to the location of CM4 vector table mentioned in flash (specified in CM4 linker definition file)
3. Releases CM4 from reset
4. Continues execution of CM0+ user application
CM4 executes directly from either code-flash or SRAM
1. CM4 branches to its Reset handler
2. Continues execution of CM4 user application

Pin assignment

Figure 7.
144-LQFP pin assignment with alternate functions

Figure 9.
100-LQFP pin assignment with alternate functions

Figure 11.
80-LQFP pin assignment with alternate functions

Figure 13.
64-LQFP pin assignment with alternate functions

High-speed I/O matrix connections

Table 13.
HSIOM connections reference
Name	Number	Description
HSIOM_SEL_GPIO	0	GPIO controls 'out'
HSIOM_SEL_GPIO_DSI	1	Reserved
HSIOM_SEL_DSI_DSI	2
HSIOM_SEL_DSI_GPIO	3
HSIOM_SEL_AMUXA	4
HSIOM_SEL_AMUXB	5
HSIOM_SEL_AMUXA_DSI	6
HSIOM_SEL_AMUXB_DSI	7
HSIOM_SEL_ACT_0	8	Active functionality 0
HSIOM_SEL_ACT_1	9	Active functionality 1
HSIOM_SEL_ACT_2	10	Active functionality 2
HSIOM_SEL_ACT_3	11	Active functionality 3
HSIOM_SEL_DS_0	12	DeepSleep functionality 0
HSIOM_SEL_DS_1	13	DeepSleep functionality 1
HSIOM_SEL_DS_2	14	DeepSleep functionality 2
HSIOM_SEL_DS_3	15	DeepSleep functionality 3
HSIOM_SEL_ACT_4	16	Active functionality 4
HSIOM_SEL_ACT_5	17	Active functionality 5
HSIOM_SEL_ACT_6	18	Active functionality 6
HSIOM_SEL_ACT_7	19	Active functionality 7
HSIOM_SEL_ACT_8	20	Active functionality 8
HSIOM_SEL_ACT_9	21	Active functionality 9
HSIOM_SEL_ACT_10	22	Active functionality 10
HSIOM_SEL_ACT_11	23	Active functionality 11
HSIOM_SEL_ACT_12	24	Active functionality 12
HSIOM_SEL_ACT_13	25	Active functionality 13
HSIOM_SEL_ACT_14	26	Active functionality 14
HSIOM_SEL_ACT_15	27	Active functionality 15
HSIOM_SEL_DS_4	28	DeepSleep functionality 4
HSIOM_SEL_DS_5	29	DeepSleep functionality 5
HSIOM_SEL_DS_6	30	DeepSleep functionality 6
HSIOM_SEL_DS_7	31	DeepSleep functionality 7

Package pin list and alternate functions

Most pins have alternate functionality, as specified in Table 14

Port 11 has the following additional features,

Ability to pass full-level analog signals to the SAR without clipping to V _DDD in cases where V _DDD < V _DDA
Ability to simultaneously capture all three ADC signals with highest priority (ADC[0:2]_M)
Lower noise, for the most sensitive sensors

Table 14.
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O ¹⁸,¹⁹
Name		Package					DeepSleep Mapping ²⁰			Analog	SMARTIO
	HCon#0 ²¹	176-LQFP	144-LQFP	100-LQFP	80-LQFP	64-LQFP	HCon#14	HCon#29	HCon#30
	I/O Type	Pin	Pin	Pin	Pin	Pin	DS #0 ²²	DS #1	DS #2
P0.0	GPIO_ENH	2	2	2	2	1			SCB0_MISO (0)
P0.1	GPIO_ENH	3	3	3	3	2			SCB0_MOSI (0)
P0.2	GPIO_ENH	4	4	4	4	3	SCB0_SCL (0)		SCB0_CLK (0)
P0.3	GPIO_ENH	5	5	5	5	4	SCB0_SDA (0)		SCB0_SEL0 (0)
P1.0	GPIO_STD	6	6	NA	NA	NA	SCB0_SCL (1)		SCB0_MISO (1)
P1.1	GPIO_STD	7	7	NA	NA	NA	SCB0_SDA (1)		SCB0_MOSI (1)
P1.2	GPIO_STD	8	NA	NA	NA	NA			SCB0_CLK (1)
P1.3	GPIO_STD	9	NA	NA	NA	NA			SCB0_SEL0 (1)
P2.0	GPIO_STD	10	8	6	6	5		SWJ_TRSTN	SCB0_SEL1 (0)
P2.1	GPIO_STD	11	9	7	7	6			SCB0_SEL2 (0)
P2.2	GPIO_STD	12	10	8	8	NA			SCB0_SEL3 (0)
P2.3	GPIO_STD	13	11	9	9	NA
P2.4	GPIO_STD	14	12	NA	NA	NA
P2.5	GPIO_STD	15	NA	NA	NA	NA
P3.0	GPIO_STD	16	13	10	NA	NA
P3.1	GPIO_STD	17	14	11	NA	NA
P3.2	GPIO_STD	18	15	NA	NA	NA
P3.3	GPIO_STD	19	16	NA	NA	NA
P3.4	GPIO_STD	20	17	NA	NA	NA
P3.5	GPIO_STD	21	NA	NA	NA	NA
P4.0	GPIO_STD	24	20	NA	NA	NA
P4.1	GPIO_STD	25	21	NA	NA	NA
P4.2	GPIO_STD	26	NA	NA	NA	NA
P4.3	GPIO_STD	27	NA	NA	NA	NA
P4.4	GPIO_STD	28	NA	NA	NA	NA
P5.0	GPIO_STD	29	22	14	10	7
P5.1	GPIO_STD	30	23	15	11	8
P5.2	GPIO_STD	31	24	16	12	NA
P5.3	GPIO_STD	32	25	17	13	NA
P5.4	GPIO_STD	33	26	NA	NA	NA
P5.5	GPIO_STD	34	NA	NA	NA	NA
P6.0	GPIO_STD	35	27	18	14	9				ADC[0]_0
P6.1	GPIO_STD	36	28	19	15	10				ADC[0]_1
P6.2	GPIO_STD	37	29	20	16	11				ADC[0]_2
P6.3	GPIO_STD	38	30	21	17	12				ADC[0]_3
P6.4	GPIO_STD	39	31	22	18	13				ADC[0]_4
P6.5	GPIO_STD	40	32	23	19	14				ADC[0]_5
P6.6	GPIO_STD	41	33	NA	NA	15				ADC[0]_6
P6.7	GPIO_STD	42	34	NA	NA	NA				ADC[0]_7
P7.0	GPIO_STD	48	40	29	22	18				ADC[0]_8
P7.1	GPIO_STD	49	41	30	23	19				ADC[0]_9
P7.2	GPIO_STD	50	42	31	24	20				ADC[0]_10
P7.3	GPIO_STD	51	43	32	25	NA				ADC[0]_11
P7.4	GPIO_STD	52	44	33	NA	NA				ADC[0]_12
P7.5	GPIO_STD	53	45	34	NA	NA				ADC[0]_13
P7.6	GPIO_STD	54	46	NA	NA	NA				ADC[0]_14
P7.7	GPIO_STD	55	47	NA	NA	NA				ADC[0]_15
P8.0	GPIO_STD	56	48	35	26	21
P8.1	GPIO_STD	57	49	36	27	22				ADC[0]_16
P8.2	GPIO_STD	58	50	37	28	NA				ADC[0]_17
P8.3	GPIO_STD	59	51	NA	NA	NA				ADC[0]_18
P8.4	GPIO_STD	60	NA	NA	NA	NA				ADC[0]_19
P9.0	GPIO_STD	61	52	NA	NA	NA				ADC[0]_20
P9.1	GPIO_STD	62	53	NA	NA	NA				ADC[0]_21
P9.2	GPIO_STD	63	NA	NA	NA	NA				ADC[0]_22
P9.3	GPIO_STD	64	NA	NA	NA	NA				ADC[0]_23
P10.0	GPIO_STD	65	54	NA	NA	NA
P10.1	GPIO_STD	66	55	NA	NA	NA
P10.2	GPIO_STD	67	56	NA	NA	NA
P10.3	GPIO_STD	68	57	NA	NA	NA
P10.4	GPIO_STD	69	58	NA	NA	NA				ADC[1]_0
P10.5	GPIO_STD	70	NA	NA	NA	NA				ADC[1]_1
P10.6	GPIO_STD	71	NA	NA	NA	NA				ADC[1]_2
P10.7	GPIO_STD	72	NA	NA	NA	NA				ADC[1]_3
P11.0	GPIO_STD	73	59	38	29	23				ADC[0]_M
P11.1	GPIO_STD	74	60	39	30	24				ADC[1]_M
P11.2	GPIO_STD	75	61	40	31	25				ADC[2]_M
P12.0	GPIO_STD	80	66	45	36	30				ADC[1]_4	SMARTIO12_0
P12.1	GPIO_STD	81	67	46	37	31				ADC[1]_5	SMARTIO12_1
P12.2	GPIO_STD	82	68	47	38	NA				ADC[1]_6	SMARTIO12_2
P12.3	GPIO_STD	83	69	48	39	NA				ADC[1]_7	SMARTIO12_3
P12.4	GPIO_STD	84	70	49	NA	NA				ADC[1]_8	SMARTIO12_4
P12.5	GPIO_STD	85	71	NA	NA	NA				ADC[1]_9	SMARTIO12_5
P12.6	GPIO_STD	86	NA	NA	NA	NA				ADC[1]_10	SMARTIO12_6
P12.7	GPIO_STD	87	NA	NA	NA	NA				ADC[1]_11	SMARTIO12_7
P13.0	GPIO_STD	90	74	52	42	34				ADC[1]_12	SMARTIO13_0
P13.1	GPIO_STD	91	75	53	43	35				ADC[1]_13	SMARTIO13_1
P13.2	GPIO_STD	92	76	54	44	36				ADC[1]_14	SMARTIO13_2
P13.3	GPIO_STD	93	77	55	45	37				ADC[1]_15	SMARTIO13_3
P13.4	GPIO_STD	94	78	56	46	NA				ADC[1]_16	SMARTIO13_4
P13.5	GPIO_STD	95	79	57	47	NA				ADC[1]_17	SMARTIO13_5
P13.6	GPIO_STD	96	80	58	48	NA				ADC[1]_18	SMARTIO13_6
P13.7	GPIO_STD	97	81	59	49	NA				ADC[1]_19	SMARTIO13_7
P14.0	GPIO_STD	98	82	60	50	38				ADC[1]_20	SMARTIO14_0
P14.1	GPIO_STD	99	83	61	51	39				ADC[1]_21	SMARTIO14_1
P14.2	GPIO_STD	100	84	62	NA	40				ADC[1]_22	SMARTIO14_2
P14.3	GPIO_STD	101	85	63	NA	NA				ADC[1]_23	SMARTIO14_3
P14.4	GPIO_STD	102	86	NA	NA	NA				ADC[1]_24	SMARTIO14_4
P14.5	GPIO_STD	103	87	NA	NA	NA				ADC[1]_25	SMARTIO14_5
P14.6	GPIO_STD	104	NA	NA	NA	NA				ADC[1]_26	SMARTIO14_6
P14.7	GPIO_STD	105	NA	NA	NA	NA				ADC[1]_27	SMARTIO14_7
P15.0	GPIO_STD	106	88	NA	NA	NA				ADC[1]_28	SMARTIO15_0
P15.1	GPIO_STD	107	89	NA	NA	NA				ADC[1]_29	SMARTIO15_1
P15.2	GPIO_STD	108	90	NA	NA	NA				ADC[1]_30	SMARTIO15_2
P15.3	GPIO_STD	109	91	NA	NA	NA				ADC[1]_31	SMARTIO15_3
P16.0	GPIO_STD	112	92	NA	NA	NA
P16.1	GPIO_STD	113	93	NA	NA	NA
P16.2	GPIO_STD	114	94	NA	NA	NA
P16.3	GPIO_STD	115	NA	NA	NA	NA
P17.0	GPIO_STD	116	95	64	NA	NA					SMARTIO17_0
P17.1	GPIO_STD	117	96	65	NA	NA					SMARTIO17_1
P17.2	GPIO_STD	118	97	66	NA	NA					SMARTIO17_2
P17.3	GPIO_STD	119	98	NA	NA	NA					SMARTIO17_3
P17.4	GPIO_STD	120	99	NA	NA	NA					SMARTIO17_4
P17.5	GPIO_STD	121	NA	NA	NA	NA					SMARTIO17_5
P17.6	GPIO_STD	122	NA	NA	NA	NA					SMARTIO17_6
P17.7	GPIO_STD	123	NA	NA	NA	NA					SMARTIO17_7
P18.0	GPIO_STD	124	100	67	52	41				ADC[2]_0
P18.1	GPIO_STD	125	101	68	53	42				ADC[2]_1
P18.2	GPIO_STD	126	102	69	54	NA				ADC[2]_2
P18.3	GPIO_STD	127	103	70	55	43				ADC[2]_3
P18.4	GPIO_STD	128	104	71	56	44				ADC[2]_4
P18.5	GPIO_STD	129	105	72	57	45				ADC[2]_5
P18.6	GPIO_STD	130	106	73	58	46				ADC[2]_6
P18.7	GPIO_STD	131	107	74	59	47				ADC[2]_7
P19.0	GPIO_STD	134	110	77	62	NA
P19.1	GPIO_STD	135	111	78	63	NA
P19.2	GPIO_STD	136	112	79	NA	NA
P19.3	GPIO_STD	137	113	80	NA	NA
P19.4	GPIO_STD	138	114	NA	NA	NA
P20.0	GPIO_STD	139	115	NA	NA	NA
P20.1	GPIO_STD	140	116	NA	NA	NA
P20.2	GPIO_STD	141	117	NA	NA	NA
P20.3	GPIO_STD	142	118	NA	NA	NA
P20.4	GPIO_STD	143	NA	NA	NA	NA
P20.5	GPIO_STD	144	NA	NA	NA	NA
P20.6	GPIO_STD	145	NA	NA	NA	NA
P20.7	GPIO_STD	146	NA	NA	NA	NA
P21.0	GPIO_STD	147	119	81	64	50				WCO_IN
P21.1	GPIO_STD	148	120	82	65	51				WCO_OUT ²³
P21.2	GPIO_STD	149	121	83	66	52				ECO_IN ²³
P21.3	GPIO_STD	150	122	84	67	53				ECO_OUT ²³
P21.4 ²⁴	GPIO_STD	151	NA	NA	NA	NA				HIBERNATE_WAKEUP[0]
P21.5	GPIO_STD	157	128	90	NA	NA
P21.6	GPIO_STD	158	129	NA	NA	NA
P21.7	GPIO_STD	159	NA	NA	NA	NA		RTC_CAL
P22.0	GPIO_STD	160	130	91	73	59
P22.1	GPIO_STD	161	131	92	74	NA
P22.2	GPIO_STD	162	132	93	NA	NA
P22.3	GPIO_STD	163	133	94	NA	NA
P22.4	GPIO_STD	164	134	NA	NA	NA
P22.5	GPIO_STD	165	135	NA	NA	NA
P22.6	GPIO_STD	166	136	NA	NA	NA
P22.7	GPIO_STD	167	NA	NA	NA	NA
P23.0	GPIO_STD	168	137	NA	NA	NA
P23.1	GPIO_STD	169	138	NA	NA	NA
P23.2	GPIO_STD	170	NA	NA	NA	NA
P23.3	GPIO_STD	171	139	95	75	60
P23.4	GPIO_STD	172	140	96	76	61		SWJ_SWO_TDO
P23.5	GPIO_STD	173	141	97	77	62		SWJ_SWCLK_TCLK
P23.6	GPIO_STD	174	142	98	78	63		SWJ_SWDIO_TMS
P23.7	GPIO_STD	175	143	99	79	64		SWJ_SWDOE_TDI		HIBERNATE_WAKEUP[1]
XRES_L		152	123	85	68	54

Power pin assignments

Table 15.
Power pin assignments
Name	Package					Remarks
Name	64-LQFP	80-LQFP	100-LQFP	144-LQFP	176-LQFP	Remarks
VDDD	55, 48, 16	80, 69, 60	100, 86, 75, 24, 12	144, 124, 108, 35, 18	176, 153, 132, 110, 43, 22	Main digital supply
VSSD	57, 56, 49, 33, 17	71, 70, 61, 41, 21, 1	88, 87, 76, 51, 27, 26, 13, 1	126, 125, 109, 73, 38, 37, 19, 1	155, 154, 133, 111, 89, 46, 45, 23, 1	Main digital ground
VDDIO_1	NA	20	25	36	44	I/O supply for analog I/Os (except analog I/Os on V _DDA )
VDDIO_2	32	40	50	72	88	I/O supply for analog I/Os (except analog I/Os on V _DDA ), P11
VCCD ²⁵	58	72	89, 28	127, 39	156, 47	Main regulated supply, driven by internal LDO regulator
VREFH	29	35	44	65	79	High reference voltage for SAR ADCs
VREFL	26	32	41	62	76	Low reference voltage for SAR ADCs
VDDA	28	34	43	64	78	Main analog supply for SAR ADCs
VSSA	27	33	42	63	77	Main analog ground

Alternate function pin assignments

Table 16.
Alternate pin functions in Active Mode ²⁶,²⁷
Name	Active Mapping
	HCon#8 ²⁸	HCon#9	HCon#10	HCon#11	HCon#16	HCon#17	HCon#18	HCon#19	HCon#20	HCon#21	HCon#26	HCon#27
	ACT#0 ²⁹	ACT#1	ACT#2	ACT#3	ACT#4	ACT#5	ACT#6	ACT#7	ACT#8	ACT#9	ACT#14	ACT#15
P0.0	PWM0_18	PWM0_22_N	TC0_18_TR0	TC0_22_TR1		SCB0_RX (0)	SCB7_SDA (2)		LIN1_RX
P0.1	PWM0_17	PWM0_18_N	TC0_17_TR0	TC0_18_TR1		SCB0_TX (0)	SCB7_SCL (2)		LIN1_TX
P0.2	PWM0_14	PWM0_17_N	TC0_14_TR0	TC0_17_TR1		SCB0_RTS (0)			LIN1_EN	CAN0_1_TX
P0.3	PWM0_13	PWM0_14_N	TC0_13_TR0	TC0_14_TR1		SCB0_CTS (0)				CAN0_1_RX
P1.0	PWM0_12	PWM0_13_N	TC0_12_TR0	TC0_13_TR1
P1.1	PWM0_11	PWM0_12_N	TC0_11_TR0	TC0_12_TR1
P1.2	PWM0_10	PWM0_11_N	TC0_10_TR0	TC0_11_TR1							TRIG_IN[0]
P1.3	PWM0_8	PWM0_10_N	TC0_8_TR0	TC0_10_TR1							TRIG_IN[1]
P2.0	PWM0_7	PWM0_8_N	TC0_7_TR0	TC0_8_TR1		SCB7_RX (0)		SCB7_MISO (0)	LIN0_RX	CAN0_0_TX	TRIG_IN[2]
P2.1	PWM0_6	PWM0_7_N	TC0_6_TR0	TC0_7_TR1		SCB7_TX (0)	SCB7_SDA (0)	SCB7_MOSI (0)	LIN0_TX	CAN0_0_RX	TRIG_IN[3]
P2.2	PWM0_5	PWM0_6_N	TC0_5_TR0	TC0_6_TR1		SCB7_RTS (0)	SCB7_SCL (0)	SCB7_CLK (0)	LIN0_EN		TRIG_IN[4]
P2.3	PWM0_4	PWM0_5_N	TC0_4_TR0	TC0_5_TR1		SCB7_CTS (0)		SCB7_SEL0 (0)	LIN5_RX		TRIG_IN[5]
P2.4	PWM0_3	PWM0_4_N	TC0_3_TR0	TC0_4_TR1				SCB7_SEL1 (0)	LIN5_TX		TRIG_IN[6]
P2.5	PWM0_2	PWM0_3_N	TC0_2_TR0	TC0_3_TR1				SCB7_SEL2 (0)	LIN5_EN		TRIG_IN[7]
P3.0	PWM0_1	PWM0_2_N	TC0_1_TR0	TC0_2_TR1		SCB6_RX (0)		SCB6_MISO (0)				TRIG_DBG[0]
P3.1	PWM0_0	PWM0_1_N	TC0_0_TR0	TC0_1_TR1		SCB6_TX (0)	SCB6_SDA (0)	SCB6_MOSI (0)				TRIG_DBG[1]
P3.2	PWM0_M_3	PWM0_0_N	TC0_M_3_TR0	TC0_0_TR1		SCB6_RTS (0)	SCB6_SCL (0)	SCB6_CLK (0)
P3.3	PWM0_M_2	PWM0_M_3_N	TC0_M_2_TR0	TC0_M_3_TR1		SCB6_CTS (0)		SCB6_SEL0 (0)
P3.4	PWM0_M_1	PWM0_M_2_N	TC0_M_1_TR0	TC0_M_2_TR1				SCB6_SEL1 (0)
P3.5	PWM0_M_0	PWM0_M_1_N	TC0_M_0_TR0	TC0_M_1_TR1				SCB6_SEL2 (0)
P4.0	PWM0_4	PWM0_M_0_N	TC0_4_TR0	TC0_M_0_TR1	EXT_MUX[0]_0	SCB5_RX (0)		SCB5_MISO (0)	LIN1_RX		TRIG_IN[10]
P4.1	PWM0_5	PWM0_4_N	TC0_5_TR0	TC0_4_TR1	EXT_MUX[0]_1	SCB5_TX (0)	SCB5_SDA (0)	SCB5_MOSI (0)	LIN1_TX		TRIG_IN[11]
P4.2	PWM0_6	PWM0_5_N	TC0_6_TR0	TC0_5_TR1	EXT_MUX[0]_2	SCB5_RTS (0)	SCB5_SCL (0)	SCB5_CLK (0)	LIN1_EN		TRIG_IN[12]
P4.3	PWM0_7	PWM0_6_N	TC0_7_TR0	TC0_6_TR1	EXT_MUX[0]_EN	SCB5_CTS (0)		SCB5_SEL0 (0)		CAN0_1_TX	TRIG_IN[13]
P4.4	PWM0_8	PWM0_7_N	TC0_8_TR0	TC0_7_TR1				SCB5_SEL1 (0)		CAN0_1_RX
P5.0	PWM0_9	PWM0_8_N	TC0_9_TR0	TC0_8_TR1				SCB5_SEL2 (0)	LIN7_RX
P5.1	PWM0_10	PWM0_9_N	TC0_10_TR0	TC0_9_TR1					LIN7_TX
P5.2	PWM0_11	PWM0_10_N	TC0_11_TR0	TC0_10_TR1					LIN7_EN
P5.3	PWM0_12	PWM0_11_N	TC0_12_TR0	TC0_11_TR1					LIN2_RX
P5.4	PWM0_13	PWM0_12_N	TC0_13_TR0	TC0_12_TR1					LIN2_TX
P5.5	PWM0_14	PWM0_13_N	TC0_14_TR0	TC0_13_TR1					LIN2_EN
P6.0	PWM0_M_0	PWM0_14_N	TC0_M_0_TR0	TC0_14_TR1		SCB4_RX (0)		SCB4_MISO (0)	LIN3_RX
P6.1	PWM0_0	PWM0_M_0_N	TC0_0_TR0	TC0_M_0_TR1		SCB4_TX (0)	SCB4_SDA (0)	SCB4_MOSI (0)	LIN3_TX
P6.2	PWM0_M_1	PWM0_0_N	TC0_M_1_TR0	TC0_0_TR1		SCB4_RTS (0)	SCB4_SCL (0)	SCB4_CLK (0)	LIN3_EN	CAN0_2_TX
P6.3	PWM0_1	PWM0_M_1_N	TC0_1_TR0	TC0_M_1_TR1		SCB4_CTS (0)		SCB4_SEL0 (0)	LIN4_RX	CAN0_2_RX		CAL_SUP_NZ
P6.4	PWM0_M_2	PWM0_1_N	TC0_M_2_TR0	TC0_1_TR1				SCB4_SEL1 (0)	LIN4_TX
P6.5	PWM0_2	PWM0_M_2_N	TC0_2_TR0	TC0_M_2_TR1				SCB4_SEL2 (0)	LIN4_EN
P6.6	PWM0_M_3	PWM0_2_N	TC0_M_3_TR0	TC0_2_TR1				SCB4_SEL3 (0)			TRIG_IN[8]
P6.7	PWM0_3	PWM0_M_3_N	TC0_3_TR0	TC0_M_3_TR1							TRIG_IN[9]
P7.0	PWM0_M_4	PWM0_3_N	TC0_M_4_TR0	TC0_3_TR1		SCB5_RX (1)		SCB5_MISO (1)	LIN4_RX
P7.1	PWM0_15	PWM0_M_4_N	TC0_15_TR0	TC0_M_4_TR1		SCB5_TX (1)	SCB5_SDA (1)	SCB5_MOSI (1)	LIN4_TX
P7.2	PWM0_M_5	PWM0_15_N	TC0_M_5_TR0	TC0_15_TR1		SCB5_RTS (1)	SCB5_SCL (1)	SCB5_CLK (1)	LIN4_EN
P7.3	PWM0_16	PWM0_M_5_N	TC0_16_TR0	TC0_M_5_TR1		SCB5_CTS (1)		SCB5_SEL0 (1)
P7.4	PWM0_M_6	PWM0_16_N	TC0_M_6_TR0	TC0_16_TR1				SCB5_SEL1 (1)
P7.5	PWM0_17	PWM0_M_6_N	TC0_17_TR0	TC0_M_6_TR1				SCB5_SEL2 (1)
P7.6	PWM0_M_7	PWM0_17_N	TC0_M_7_TR0	TC0_17_TR1							TRIG_IN[16]
P7.7	PWM0_18	PWM0_M_7_N	TC0_18_TR0	TC0_M_7_TR1							TRIG_IN[17]
P8.0	PWM0_19	PWM0_18_N	TC0_19_TR0	TC0_18_TR1					LIN2_RX	CAN0_0_TX
P8.1	PWM0_20	PWM0_19_N	TC0_20_TR0	TC0_19_TR1					LIN2_TX	CAN0_0_RX	TRIG_IN[14]
P8.2	PWM0_21	PWM0_20_N	TC0_21_TR0	TC0_20_TR1					LIN2_EN		TRIG_IN[15]
P8.3	PWM0_22	PWM0_21_N	TC0_22_TR0	TC0_21_TR1								TRIG_DBG[0]
P8.4	PWM0_23	PWM0_22_N	TC0_23_TR0	TC0_22_TR1								TRIG_DBG[1]
P9.0	PWM0_24	PWM0_23_N	TC0_24_TR0	TC0_23_TR1
P9.1	PWM0_25	PWM0_24_N	TC0_25_TR0	TC0_24_TR1
P9.2	PWM0_26	PWM0_25_N	TC0_26_TR0	TC0_25_TR1
P9.3	PWM0_27	PWM0_26_N	TC0_27_TR0	TC0_26_TR1
P10.0	PWM0_28	PWM0_27_N	TC0_28_TR0	TC0_27_TR1		SCB4_RX (1)		SCB4_MISO (1)			TRIG_IN[18]
P10.1	PWM0_29	PWM0_28_N	TC0_29_TR0	TC0_28_TR1		SCB4_TX (1)	SCB4_SDA (1)	SCB4_MOSI (1)			TRIG_IN[19]
P10.2	PWM0_30	PWM0_29_N	TC0_30_TR0	TC0_29_TR1		SCB4_RTS (1)	SCB4_SCL (1)	SCB4_CLK (1)
P10.3	PWM0_31	PWM0_30_N	TC0_31_TR0	TC0_30_TR1		SCB4_CTS (1)		SCB4_SEL0 (1)
P10.4	PWM0_32	PWM0_31_N	TC0_32_TR0	TC0_31_TR1				SCB4_SEL1 (1)
P10.5	PWM0_33	PWM0_32_N	TC0_33_TR0	TC0_32_TR1				SCB4_SEL2 (1)
P10.6	PWM0_34	PWM0_33_N	TC0_34_TR0	TC0_33_TR1
P10.7	PWM0_35	PWM0_34_N	TC0_35_TR0	TC0_34_TR1
P11.0
P11.1
P11.2
P12.0	PWM0_36	PWM0_35_N	TC0_36_TR0	TC0_35_TR1						CAN0_2_TX	TRIG_IN[20]
P12.1	PWM0_37	PWM0_36_N	TC0_37_TR0	TC0_36_TR1					LIN6_EN	CAN0_2_RX	TRIG_IN[21]
P12.2	PWM0_38	PWM0_37_N	TC0_38_TR0	TC0_37_TR1	EXT_MUX[1]_EN				LIN6_RX
P12.3	PWM0_39	PWM0_38_N	TC0_39_TR0	TC0_38_TR1	EXT_MUX[1]_0				LIN6_TX
P12.4	PWM0_40	PWM0_39_N	TC0_40_TR0	TC0_39_TR1	EXT_MUX[1]_1
P12.5	PWM0_41	PWM0_40_N	TC0_41_TR0	TC0_40_TR1	EXT_MUX[1]_2
P12.6	PWM0_42	PWM0_41_N	TC0_42_TR0	TC0_41_TR1
P12.7	PWM0_43	PWM0_42_N	TC0_43_TR0	TC0_42_TR1
P13.0	PWM0_M_8	PWM0_43_N	TC0_M_8_TR0	TC0_43_TR1	EXT_MUX[2]_0	SCB3_RX (0)		SCB3_MISO (0)
P13.1	PWM0_44	PWM0_M_8_N	TC0_44_TR0	TC0_M_8_TR1	EXT_MUX[2]_1	SCB3_TX (0)	SCB3_SDA (0)	SCB3_MOSI (0)
P13.2	PWM0_M_9	PWM0_44_N	TC0_M_9_TR0	TC0_44_TR1	EXT_MUX[2]_2	SCB3_RTS (0)	SCB3_SCL (0)	SCB3_CLK (0)
P13.3	PWM0_45	PWM0_M_9_N	TC0_45_TR0	TC0_M_9_TR1	EXT_MUX[2]_EN	SCB3_CTS (0)		SCB3_SEL0 (0)
P13.4	PWM0_M_10	PWM0_45_N	TC0_M_10_TR0	TC0_45_TR1				SCB3_SEL1 (0)
P13.5	PWM0_46	PWM0_M_10_N	TC0_46_TR0	TC0_M_10_TR1				SCB3_SEL2 (0)
P13.6	PWM0_M_11	PWM0_46_N	TC0_M_11_TR0	TC0_46_TR1				SCB3_SEL3 (0)			TRIG_IN[22]
P13.7	PWM0_47	PWM0_M_11_N	TC0_47_TR0	TC0_M_11_TR1							TRIG_IN[23]
P14.0	PWM0_48	PWM0_47_N	TC0_48_TR0	TC0_47_TR1		SCB2_RX (0)		SCB2_MISO (0)		CAN1_0_TX
P14.1	PWM0_49	PWM0_48_N	TC0_49_TR0	TC0_48_TR1		SCB2_TX (0)	SCB2_SDA (0)	SCB2_MOSI (0)		CAN1_0_RX
P14.2	PWM0_50	PWM0_49_N	TC0_50_TR0	TC0_49_TR1		SCB2_RTS (0)	SCB2_SCL (0)	SCB2_CLK (0)	LIN6_RX
P14.3	PWM0_51	PWM0_50_N	TC0_51_TR0	TC0_50_TR1		SCB2_CTS (0)		SCB2_SEL0 (0)	LIN6_TX
P14.4	PWM0_52	PWM0_51_N	TC0_52_TR0	TC0_51_TR1				SCB2_SEL1 (0)	LIN6_EN
P14.5	PWM0_53	PWM0_52_N	TC0_53_TR0	TC0_52_TR1				SCB2_SEL2 (0)
P14.6	PWM0_54	PWM0_53_N	TC0_54_TR0	TC0_53_TR1							TRIG_IN[24]
P14.7	PWM0_55	PWM0_54_N	TC0_55_TR0	TC0_54_TR1							TRIG_IN[25]
P15.0	PWM0_56	PWM0_55_N	TC0_56_TR0	TC0_55_TR1
P15.1	PWM0_57	PWM0_56_N	TC0_57_TR0	TC0_56_TR1
P15.2	PWM0_58	PWM0_57_N	TC0_58_TR0	TC0_57_TR1
P15.3	PWM0_59	PWM0_58_N	TC0_59_TR0	TC0_58_TR1
P16.0	PWM0_60	PWM0_59_N	TC0_60_TR0	TC0_59_TR1	PWM0_H_0
P16.1	PWM0_61	PWM0_60_N	TC0_61_TR0	TC0_60_TR1	PWM0_H_0_N
P16.2	PWM0_62	PWM0_61_N	TC0_62_TR0	TC0_61_TR1	PWM0_H_1
P16.3	PWM0_62	PWM0_62_N	TC0_62_TR0	TC0_62_TR1	PWM0_H_1_N
P17.0	PWM0_61	PWM0_62_N	TC0_61_TR0	TC0_62_TR1						CAN1_1_TX
P17.1	PWM0_60	PWM0_61_N	TC0_60_TR0	TC0_61_TR1	PWM0_H_2	SCB3_RX (1)		SCB3_MISO (1)		CAN1_1_RX
P17.2	PWM0_59	PWM0_60_N	TC0_59_TR0	TC0_60_TR1	PWM0_H_2_N	SCB3_TX (1)	SCB3_SDA (1)	SCB3_MOSI (1)
P17.3	PWM0_58	PWM0_59_N	TC0_58_TR0	TC0_59_TR1	PWM0_H_3	SCB3_RTS (1)	SCB3_SCL (1)	SCB3_CLK (1)			TRIG_IN[26]
P17.4	PWM0_57	PWM0_58_N	TC0_57_TR0	TC0_58_TR1	PWM0_H_3_N	SCB3_CTS (1)		SCB3_SEL0 (1)			TRIG_IN[27]
P17.5	PWM0_56	PWM0_57_N	TC0_56_TR0	TC0_57_TR1				SCB3_SEL1 (1)
P17.6	PWM0_M_4	PWM0_56_N	TC0_M_4_TR0	TC0_56_TR1				SCB3_SEL2 (1)
P17.7	PWM0_M_5	PWM0_M_4_N	TC0_M_5_TR0	TC0_M_4_TR1
P18.0	PWM0_M_6	PWM0_M_5_N	TC0_M_6_TR0	TC0_M_5_TR1	PWM0_H_0	SCB1_RX (0)		SCB1_MISO (0)				FAULT_OUT_0
P18.1	PWM0_M_7	PWM0_M_6_N	TC0_M_7_TR0	TC0_M_6_TR1	PWM0_H_0_N	SCB1_TX (0)	SCB1_SDA (0)	SCB1_MOSI (0)				FAULT_OUT_1
P18.2	PWM0_55	PWM0_M_7_N	TC0_55_TR0	TC0_M_7_TR1	PWM0_H_1	SCB1_RTS (0)	SCB1_SCL (0)	SCB1_CLK (0)
P18.3	PWM0_54	PWM0_55_N	TC0_54_TR0	TC0_55_TR1	PWM0_H_1_N	SCB1_CTS (0)		SCB1_SEL0 (0)				TRACE_CLOCK (0)
P18.4	PWM0_53	PWM0_54_N	TC0_53_TR0	TC0_54_TR1	PWM0_H_2			SCB1_SEL1 (0)				TRACE_DATA_0 (0)
P18.5	PWM0_52	PWM0_53_N	TC0_52_TR0	TC0_53_TR1	PWM0_H_2_N			SCB1_SEL2 (0)				TRACE_DATA_1 (0)
P18.6	PWM0_51	PWM0_52_N	TC0_51_TR0	TC0_52_TR1	PWM0_H_3			SCB1_SEL3 (0)		CAN1_2_TX		TRACE_DATA_2 (0)
P18.7	PWM0_50	PWM0_51_N	TC0_50_TR0	TC0_51_TR1	PWM0_H_3_N					CAN1_2_RX		TRACE_DATA_3 (0)
P19.0	PWM0_M_3	PWM0_50_N	TC0_M_3_TR0	TC0_50_TR1	TC0_H_0_TR0	SCB2_RX (1)		SCB2_MISO (1)				FAULT_OUT_2
P19.1	PWM0_26	PWM0_M_3_N	TC0_26_TR0	TC0_M_3_TR1	TC0_H_0_TR1	SCB2_TX (1)	SCB2_SDA (1)	SCB2_MOSI (1)				FAULT_OUT_3
P19.2	PWM0_27	PWM0_26_N	TC0_27_TR0	TC0_26_TR1	TC0_H_1_TR0	SCB2_RTS (1)	SCB2_SCL (1)	SCB2_CLK (1)			TRIG_IN[28]
P19.3	PWM0_28	PWM0_27_N	TC0_28_TR0	TC0_27_TR1	TC0_H_1_TR1	SCB2_CTS (1)		SCB2_SEL0 (1)			TRIG_IN[29]
P19.4	PWM0_29	PWM0_28_N	TC0_29_TR0	TC0_28_TR1	TC0_H_2_TR0			SCB2_SEL1 (1)
P20.0	PWM0_30	PWM0_29_N	TC0_30_TR0	TC0_29_TR1	TC0_H_2_TR1			SCB2_SEL2 (1)	LIN5_RX
P20.1	PWM0_49	PWM0_30_N	TC0_49_TR0	TC0_30_TR1	TC0_H_3_TR0				LIN5_TX
P20.2	PWM0_48	PWM0_49_N	TC0_48_TR0	TC0_49_TR1	TC0_H_3_TR1				LIN5_EN
P20.3	PWM0_47	PWM0_48_N	TC0_47_TR0	TC0_48_TR1		SCB1_RX (1)		SCB1_MISO (1)		CAN1_2_TX
P20.4	PWM0_46	PWM0_47_N	TC0_46_TR0	TC0_47_TR1		SCB1_TX (1)	SCB1_SDA (1)	SCB1_MOSI (1)		CAN1_2_RX
P20.5	PWM0_45	PWM0_46_N	TC0_45_TR0	TC0_46_TR1		SCB1_RTS (1)	SCB1_SCL (1)	SCB1_CLK (1)
P20.6	PWM0_44	PWM0_45_N	TC0_44_TR0	TC0_45_TR1		SCB1_CTS (1)		SCB1_SEL0 (1)
P20.7	PWM0_43	PWM0_44_N	TC0_43_TR0	TC0_44_TR1				SCB1_SEL1 (1)
P21.0	PWM0_42	PWM0_43_N	TC0_42_TR0	TC0_43_TR1				SCB1_SEL2 (1)
P21.1	PWM0_41	PWM0_42_N	TC0_41_TR0	TC0_42_TR1
P21.2	PWM0_40	PWM0_41_N	TC0_40_TR0	TC0_41_TR1							EXT_CLK	TRIG_DBG[1]
P21.3	PWM0_39	PWM0_40_N	TC0_39_TR0	TC0_40_TR1
P21.4	PWM0_38	PWM0_39_N	TC0_38_TR0	TC0_39_TR1
P21.5	PWM0_37	PWM0_38_N	TC0_37_TR0	TC0_38_TR1					LIN0_RX
P21.6	PWM0_36	PWM0_37_N	TC0_36_TR0	TC0_37_TR1					LIN0_TX
P21.7	PWM0_35	PWM0_36_N	TC0_35_TR0	TC0_36_TR1					LIN0_EN			CAL_SUP_NZ
P22.0	PWM0_34	PWM0_35_N	TC0_34_TR0	TC0_35_TR1		SCB6_RX (1)		SCB6_MISO (1)		CAN1_1_TX		TRACE_DATA_0 (1)
P22.1	PWM0_33	PWM0_34_N	TC0_33_TR0	TC0_34_TR1		SCB6_TX (1)	SCB6_SDA (1)	SCB6_MOSI (1)		CAN1_1_RX		TRACE_DATA_1 (1)
P22.2	PWM0_32	PWM0_33_N	TC0_32_TR0	TC0_33_TR1		SCB6_RTS (1)	SCB6_SCL (1)	SCB6_CLK (1)				TRACE_DATA_2 (1)
P22.3	PWM0_31	PWM0_32_N	TC0_31_TR0	TC0_32_TR1		SCB6_CTS (1)		SCB6_SEL0 (1)				TRACE_DATA_3 (1)
P22.4	PWM0_30	PWM0_31_N	TC0_30_TR0	TC0_31_TR1				SCB6_SEL1 (1)				TRACE_CLOCK (1)
P22.5	PWM0_29	PWM0_30_N	TC0_29_TR0	TC0_30_TR1				SCB6_SEL2 (1)	LIN7_RX
P22.6	PWM0_28	PWM0_29_N	TC0_28_TR0	TC0_29_TR1					LIN7_TX
P22.7	PWM0_27	PWM0_28_N	TC0_27_TR0	TC0_28_TR1					LIN7_EN
P23.0	PWM0_M_8	PWM0_27_N	TC0_M_8_TR0	TC0_27_TR1		SCB7_RX (1)		SCB7_MISO (1)		CAN1_0_TX		FAULT_OUT_0
P23.1	PWM0_M_9	PWM0_M_8_N	TC0_M_9_TR0	TC0_M_8_TR1		SCB7_TX (1)	SCB7_SDA (1)	SCB7_MOSI (1)		CAN1_0_RX		FAULT_OUT_1
P23.2	PWM0_M_10	PWM0_M_9_N	TC0_M_10_TR0	TC0_M_9_TR1		SCB7_RTS (1)	SCB7_SCL (1)	SCB7_CLK (1)				FAULT_OUT_2
P23.3	PWM0_M_11	PWM0_M_10_N	TC0_M_11_TR0	TC0_M_10_TR1		SCB7_CTS (1)		SCB7_SEL0 (1)			TRIG_IN[30]	FAULT_OUT_3
P23.4	PWM0_25	PWM0_M_11_N	TC0_25_TR0	TC0_M_11_TR1				SCB7_SEL1 (1)			TRIG_IN[31]	TRIG_DBG[0]
P23.5	PWM0_24	PWM0_25_N	TC0_24_TR0	TC0_25_TR1				SCB7_SEL2 (1)
P23.6	PWM0_23	PWM0_24_N	TC0_23_TR0	TC0_24_TR1
P23.7	PWM0_22	PWM0_23_N	TC0_22_TR0	TC0_23_TR1							EXT_CLK	CAL_SUP_NZ

Table 17.
Pin Mux descriptions
Sl.No.	Pin	Module	Description
1	PWMx_y	TCPWM	TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR line out, x-TCPWM block, y-counter number
2	PWMx_y_N	TCPWM	TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR complementary line out (N), x-TCPWM block, y-counter number
3	PWMx_M_y	TCPWM	TCPWM 16-bit PWM with motor control line out, x-TCPWM block, y-counter number
4	PWMx_M_y_N	TCPWM	TCPWM 16-bit PWM with motor control complementary line out (N), x-TCPWM block, y-counter number
5	PWMx_H_y	TCPWM	TCPWM 32-bit PWM, PWM_DT and PWM_PR line out, x-TCPWM block, y-counter number
6	PWMx_H_y_N	TCPWM	TCPWM 32-bit PWM, PWM_DT and PWM_PR complementary line out (N), x-TCPWM block, y-counter number
7	TCx_y_TRz	TCPWM	TCPWM 16-bit dedicated counter input triggers, x-TCPWM block, y-counter number, z-trigger number
8	TCx_M_y_TRz	TCPWM	TCPWM 16-bit dedicated counter input triggers with motor control, x-TCPWM block, y-counter number, z-trigger number
9	TCx_H_y_TRz	TCPWM	TCPWM 32-bit dedicated counter input triggers, x-TCPWM block, y-counter number, z-trigger number
10	SCBx_RX	SCB	UART Receive, x-SCB block
11	SCBx_TX	SCB	UART Transmit, x-SCB block
12	SCBx_RTS	SCB	UART Request to Send (Handshake), x-SCB block
13	SCBx_CTS	SCB	UART Clear to Send (Handshake), x-SCB block
14	SCBx_SDA	SCB	I ² C Data line, x-SCB block
15	SCBx_SCL	SCB	I ² C Clock line, x-SCB block
16	SCBx_MISO	SCB	SPI Master Input Slave Output, x-SCB block
17	SCBx_MOSI	SCB	SPI Master Output Slave Input, x-SCB block
18	SCBx_CLK	SCB	SPI Serial Clock, x-SCB block
19	SCBx_SELy	SCB	SPI Slave Select, x-SCB block, y-select line
20	LINx_RX	LIN	LIN Receive line, x-LIN block
21	LINx_TX	LIN	LIN Transmit line, x-LIN block
22	LINx_EN	LIN	LIN Enable line, x-LIN block
23	CANx_y_TX	CANFD	CAN Transmit line, x-CAN block, y-channel number
24	CANx_y_RX	CANFD	CAN Receive line, x-CAN block, y-channel number
25	CAL_SUP_NZ	CPUSS	ETAS Calibration support line
26	FAULT_OUT_x	SRSS	Fault output line x-0 to 3
27	TRACE_DATA_x	SRSS	Trace dataout line x-0 to 3
28	TRACE_CLOCK	SRSS	Trace clock line
29	RTC_CAL	SRSS RTC	RTC calibration clock input
30	SWJ_TRSTN	SRSS	JTAG Test reset line (Active low)
31	SWJ_SWO_TDO	SRSS	JTAG Test data output/SWO (Serial Wire Output)
32	SWJ_SWCLK_TCLK	SRSS	JTAG Test clock/SWD clock (Serial Wire Clock)
33	SWJ_SWDIO_TMS	SRSS	JTAG Test mode select/SWD data (Serial Wire Data Input/Output)
34	SWJ_SWDOE_TDI	SRSS	JTAG Test data input
35	HIBERNATE_WAKEUP[x]	SRSS	Hibernate wakeup line x-0 to 1
36	ADC[x]_y	PASS SAR	SAR, channel, x-SAR number, y-channel number
37	ADC[x]_M	PASS SAR	SAR motor control input, x-SAR number
38	EXT_MUX[x]_y	PASS SAR	External SAR MUX inputs, x-MUX number, y-MUX input 0 to 2
39	EXT_MUX[x]_EN	PASS SAR	External SAR MUX enable line
40	EXT_CLK	SRSS	External clock input or output
41	TRIG_IN[x]	HSIOM	HSIOM_IO_INPUT[x] of trigger inputs, x-0 to 47
42	TRIG_DBG[x]	HSIOM	HSIOM_IO_OUTPUT[x] of trigger outputs, x-0 to 1
43	WCO_IN	SRSS	Watch crystal oscillator input
44	WCO_OUT	SRSS	Watch crystal oscillator output
45	ECO_IN	SRSS	External crystal oscillator input
46	ECO_OUT	SRSS	External crystal oscillator output

Interrupts and wake-up assignments

Table 18.
Peripheral interrupt assignments and wake-up sources
Interrupt	Source	Power Mode	Description
0	cpuss_interrupts_ipc_0_IRQn	DeepSleep	CPUSS Inter Process Communication Interrupt #0
1	cpuss_interrupts_ipc_1_IRQn	DeepSleep	CPUSS Inter Process Communication Interrupt #1
2	cpuss_interrupts_ipc_2_IRQn	DeepSleep	CPUSS Inter Process Communication Interrupt #2
3	cpuss_interrupts_ipc_3_IRQn	DeepSleep	CPUSS Inter Process Communication Interrupt #3
4	cpuss_interrupts_ipc_4_IRQn	DeepSleep	CPUSS Inter Process Communication Interrupt #4
5	cpuss_interrupts_ipc_5_IRQn	DeepSleep	CPUSS Inter Process Communication Interrupt #5
6	cpuss_interrupts_ipc_6_IRQn	DeepSleep	CPUSS Inter Process Communication Interrupt #6
7	cpuss_interrupts_ipc_7_IRQn	DeepSleep	CPUSS Inter Process Communication Interrupt #7
8	cpuss_interrupts_fault_0_IRQn	DeepSleep	CPUSS Fault Structure #0 Interrupt
9	cpuss_interrupts_fault_1_IRQn	DeepSleep	CPUSS Fault Structure #1 Interrupt
10	cpuss_interrupts_fault_2_IRQn	DeepSleep	CPUSS Fault Structure #2 Interrupt
11	cpuss_interrupts_fault_3_IRQn	DeepSleep	CPUSS Fault Structure #3 Interrupt
12	srss_interrupt_backup_IRQn	DeepSleep	BACKUP domain Interrupt
13	srss_interrupt_mcwdt_0_IRQn	DeepSleep	Multi Counter Watchdog Timer #0 interrupt
14	srss_interrupt_mcwdt_1_IRQn	DeepSleep	Multi Counter Watchdog Timer #1 interrupt
15	srss_interrupt_wdt_IRQn	DeepSleep	Hardware Watchdog Timer interrupt
16	srss_interrupt_IRQn	DeepSleep	Other combined Interrupts for SRSS (LVD, CLKCAL)
17	scb_0_interrupt_IRQn	DeepSleep	SCB0 interrupt (DeepSleep capable)
18	evtgen_0_interrupt_dpslp_IRQn	DeepSleep	Event gen DeepSleep domain interrupt
19	ioss_interrupt_vdd_IRQn	DeepSleep	I/O Supply (V _DDIO , V _DDA , V _DDD ) state change Interrupt
20	ioss_interrupt_gpio_IRQn	DeepSleep	Consolidated Interrupt for GPIO_STD and GPIO_ENH, All Ports
21	ioss_interrupts_gpio_0_IRQn	DeepSleep	GPIO_ENH Port #0 Interrupt
22	ioss_interrupts_gpio_1_IRQn	DeepSleep	GPIO_STD Port #1 Interrupt
23	ioss_interrupts_gpio_2_IRQn	DeepSleep	GPIO_STD Port #2 Interrupt
24	ioss_interrupts_gpio_3_IRQn	DeepSleep	GPIO_STD Port #3 Interrupt
25	ioss_interrupts_gpio_4_IRQn	DeepSleep	GPIO_STD Port #4 Interrupt
26	ioss_interrupts_gpio_5_IRQn	DeepSleep	GPIO_STD Port #5 Interrupt
27	ioss_interrupts_gpio_6_IRQn	DeepSleep	GPIO_STD Port #6 Interrupt
28	ioss_interrupts_gpio_7_IRQn	DeepSleep	GPIO_STD Port #7 Interrupt
29	ioss_interrupts_gpio_8_IRQn	DeepSleep	GPIO_STD Port #8 Interrupt
30	ioss_interrupts_gpio_9_IRQn	DeepSleep	GPIO_STD Port #9 Interrupt
31	ioss_interrupts_gpio_10_IRQn	DeepSleep	GPIO_STD Port #10 Interrupt
32	ioss_interrupts_gpio_11_IRQn	DeepSleep	GPIO_STD Port #11 Interrupt
33	ioss_interrupts_gpio_12_IRQn	DeepSleep	GPIO_STD Port #12 Interrupt
34	ioss_interrupts_gpio_13_IRQn	DeepSleep	GPIO_STD Port #13 Interrupt
35	ioss_interrupts_gpio_14_IRQn	DeepSleep	GPIO_STD Port #14 Interrupt
36	ioss_interrupts_gpio_15_IRQn	DeepSleep	GPIO_STD Port #15 Interrupt
37	ioss_interrupts_gpio_16_IRQn	DeepSleep	GPIO_STD Port #16 Interrupt
38	ioss_interrupts_gpio_17_IRQn	DeepSleep	GPIO_STD Port #17 Interrupt
39	ioss_interrupts_gpio_18_IRQn	DeepSleep	GPIO_STD Port #18 Interrupt
40	ioss_interrupts_gpio_19_IRQn	DeepSleep	GPIO_STD Port #19 Interrupt
41	ioss_interrupts_gpio_20_IRQn	DeepSleep	GPIO_STD Port #20 Interrupt
42	ioss_interrupts_gpio_21_IRQn	DeepSleep	GPIO_STD Port #21 Interrupt
43	ioss_interrupts_gpio_22_IRQn	DeepSleep	GPIO_STD Port #22 Interrupt
44	ioss_interrupts_gpio_23_IRQn	DeepSleep	GPIO_STD Port #23 Interrupt
45	cpuss_interrupt_crypto_IRQn	Active	Crypto Accelerator Interrupt
46	cpuss_interrupt_fm_IRQn	Active	FLASH Macro Interrupt
47	cpuss_interrupts_cm4_fp_IRQn	Active	CM4 Floating Point operation fault
48	cpuss_interrupts_cm0_cti_0_IRQn	Active	CM0+ CTI (Cross Trigger Interface) #0
49	cpuss_interrupts_cm0_cti_1_IRQn	Active	CM0+ CTI #1
50	cpuss_interrupts_cm4_cti_0_IRQn	Active	CM4 CTI #0
51	cpuss_interrupts_cm4_cti_1_IRQn	Active	CM4 CTI #1
52	evtgen_0_interrupt_IRQn	Active	Event gen Active domain interrupt
53	canfd_0_interrupt0_IRQn	Active	CAN0, Consolidated Interrupt #0 for all three channels
54	canfd_0_interrupt1_IRQn	Active	CAN0, Consolidated Interrupt #1 for all three channels
55	canfd_1_interrupt0_IRQn	Active	CAN1, Consolidated Interrupt #0 for all three channels
56	canfd_1_interrupt1_IRQn	Active	CAN1, Consolidated Interrupt #1 for all three channels
57	canfd_0_interrupts0_0_IRQn	Active	CAN0, Interrupt #0, Channel #0
58	canfd_0_interrupts0_1_IRQn	Active	CAN0, Interrupt #0, Channel #1
59	canfd_0_interrupts0_2_IRQn	Active	CAN0, Interrupt #0, Channel #2
60	canfd_0_interrupts1_0_IRQn	Active	CAN0, Interrupt #1, Channel #0
61	canfd_0_interrupts1_1_IRQn	Active	CAN0, Interrupt #1, Channel #1
62	canfd_0_interrupts1_2_IRQn	Active	CAN0, Interrupt #1, Channel #2
63	canfd_1_interrupts0_0_IRQn	Active	CAN1, Interrupt #0, Channel #0
64	canfd_1_interrupts0_1_IRQn	Active	CAN1, Interrupt #0, Channel #1
65	canfd_1_interrupts0_2_IRQn	Active	CAN1, Interrupt #0, Channel #2
66	canfd_1_interrupts1_0_IRQn	Active	CAN1, Interrupt #1, Channel #0
67	canfd_1_interrupts1_1_IRQn	Active	CAN1, Interrupt #1, Channel #1
68	canfd_1_interrupts1_2_IRQn	Active	CAN1, Interrupt #1, Channel #2
69	lin_0_interrupts_0_IRQn	Active	LIN0, Channel #0 Interrupt
70	lin_0_interrupts_1_IRQn	Active	LIN0, Channel #1 Interrupt
71	lin_0_interrupts_2_IRQn	Active	LIN0, Channel #2 Interrupt
72	lin_0_interrupts_3_IRQn	Active	LIN0, Channel #3 Interrupt
73	lin_0_interrupts_4_IRQn	Active	LIN0, Channel #4 Interrupt
74	lin_0_interrupts_5_IRQn	Active	LIN0, Channel #5 Interrupt
75	lin_0_interrupts_6_IRQn	Active	LIN0, Channel #6 Interrupt
76	lin_0_interrupts_7_IRQn	Active	LIN0, Channel #7 Interrupt
77	scb_1_interrupt_IRQn	Active	SCB1 Interrupt
78	scb_2_interrupt_IRQn	Active	SCB2 Interrupt
79	scb_3_interrupt_IRQn	Active	SCB3 Interrupt
80	scb_4_interrupt_IRQn	Active	SCB4 Interrupt
81	scb_5_interrupt_IRQn	Active	SCB5 Interrupt
82	scb_6_interrupt_IRQn	Active	SCB6 Interrupt
83	scb_7_interrupt_IRQn	Active	SCB7 Interrupt
84	pass_0_interrupts_sar_0_IRQn	Active	SAR0, Logical Channel #0 Interrupt
85	pass_0_interrupts_sar_1_IRQn	Active	SAR0, Logical Channel #1 Interrupt
86	pass_0_interrupts_sar_2_IRQn	Active	SAR0, Logical Channel #2 Interrupt
87	pass_0_interrupts_sar_3_IRQn	Active	SAR0, Logical Channel #3 Interrupt
88	pass_0_interrupts_sar_4_IRQn	Active	SAR0, Logical Channel #4 Interrupt
89	pass_0_interrupts_sar_5_IRQn	Active	SAR0, Logical Channel #5 Interrupt
90	pass_0_interrupts_sar_6_IRQn	Active	SAR0, Logical Channel #6 Interrupt
91	pass_0_interrupts_sar_7_IRQn	Active	SAR0, Logical Channel #7 Interrupt
92	pass_0_interrupts_sar_8_IRQn	Active	SAR0, Logical Channel #8 Interrupt
93	pass_0_interrupts_sar_9_IRQn	Active	SAR0, Logical Channel #9 Interrupt
94	pass_0_interrupts_sar_10_IRQn	Active	SAR0, Logical Channel #10 Interrupt
95	pass_0_interrupts_sar_11_IRQn	Active	SAR0, Logical Channel #11 Interrupt
96	pass_0_interrupts_sar_12_IRQn	Active	SAR0, Logical Channel #12 Interrupt
97	pass_0_interrupts_sar_13_IRQn	Active	SAR0, Logical Channel #13 Interrupt
98	pass_0_interrupts_sar_14_IRQn	Active	SAR0, Logical Channel #14 Interrupt
99	pass_0_interrupts_sar_15_IRQn	Active	SAR0, Logical Channel #15 Interrupt
100	pass_0_interrupts_sar_16_IRQn	Active	SAR0, Logical Channel #16 Interrupt
101	pass_0_interrupts_sar_17_IRQn	Active	SAR0, Logical Channel #17 Interrupt
102	pass_0_interrupts_sar_18_IRQn	Active	SAR0, Logical Channel #18 Interrupt
103	pass_0_interrupts_sar_19_IRQn	Active	SAR0, Logical Channel #19 Interrupt
104	pass_0_interrupts_sar_20_IRQn	Active	SAR0, Logical Channel #20 Interrupt
105	pass_0_interrupts_sar_21_IRQn	Active	SAR0, Logical Channel #21 Interrupt
106	pass_0_interrupts_sar_22_IRQn	Active	SAR0, Logical Channel #22 Interrupt
107	pass_0_interrupts_sar_23_IRQn	Active	SAR0, Logical Channel #23 Interrupt
108	pass_0_interrupts_sar_32_IRQn	Active	SAR1, Logical Channel #0 Interrupt
109	pass_0_interrupts_sar_33_IRQn	Active	SAR1, Logical Channel #1 Interrupt
110	pass_0_interrupts_sar_34_IRQn	Active	SAR1, Logical Channel #2 Interrupt
111	pass_0_interrupts_sar_35_IRQn	Active	SAR1, Logical Channel #3 Interrupt
112	pass_0_interrupts_sar_36_IRQn	Active	SAR1, Logical Channel #4 Interrupt
113	pass_0_interrupts_sar_37_IRQn	Active	SAR1, Logical Channel #5 Interrupt
114	pass_0_interrupts_sar_38_IRQn	Active	SAR1, Logical Channel #6 Interrupt
115	pass_0_interrupts_sar_39_IRQn	Active	SAR1, Logical Channel #7 Interrupt
116	pass_0_interrupts_sar_40_IRQn	Active	SAR1, Logical Channel #8 Interrupt
117	pass_0_interrupts_sar_41_IRQn	Active	SAR1, Logical Channel #9 Interrupt
118	pass_0_interrupts_sar_42_IRQn	Active	SAR1, Logical Channel #10 Interrupt
119	pass_0_interrupts_sar_43_IRQn	Active	SAR1, Logical Channel #11 Interrupt
120	pass_0_interrupts_sar_44_IRQn	Active	SAR1, Logical Channel #12 Interrupt
121	pass_0_interrupts_sar_45_IRQn	Active	SAR1, Logical Channel #13 Interrupt
122	pass_0_interrupts_sar_46_IRQn	Active	SAR1, Logical Channel #14 Interrupt
123	pass_0_interrupts_sar_47_IRQn	Active	SAR1, Logical Channel #15 Interrupt
124	pass_0_interrupts_sar_48_IRQn	Active	SAR1, Logical Channel #16 Interrupt
125	pass_0_interrupts_sar_49_IRQn	Active	SAR1, Logical Channel #17 Interrupt
126	pass_0_interrupts_sar_50_IRQn	Active	SAR1, Logical Channel #18 Interrupt
127	pass_0_interrupts_sar_51_IRQn	Active	SAR1, Logical Channel #19 Interrupt
128	pass_0_interrupts_sar_52_IRQn	Active	SAR1, Logical Channel #20 Interrupt
129	pass_0_interrupts_sar_53_IRQn	Active	SAR1, Logical Channel #21 Interrupt
130	pass_0_interrupts_sar_54_IRQn	Active	SAR1, Logical Channel #22 Interrupt
131	pass_0_interrupts_sar_55_IRQn	Active	SAR1, Logical Channel #23 Interrupt
132	pass_0_interrupts_sar_56_IRQn	Active	SAR1, Logical Channel #24 Interrupt
133	pass_0_interrupts_sar_57_IRQn	Active	SAR1, Logical Channel #25 Interrupt
134	pass_0_interrupts_sar_58_IRQn	Active	SAR1, Logical Channel #26 Interrupt
135	pass_0_interrupts_sar_59_IRQn	Active	SAR1, Logical Channel #27 Interrupt
136	pass_0_interrupts_sar_60_IRQn	Active	SAR1, Logical Channel #28 Interrupt
137	pass_0_interrupts_sar_61_IRQn	Active	SAR1, Logical Channel #29 Interrupt
138	pass_0_interrupts_sar_62_IRQn	Active	SAR1, Logical Channel #30 Interrupt
139	pass_0_interrupts_sar_63_IRQn	Active	SAR1, Logical Channel #31 Interrupt
140	pass_0_interrupts_sar_64_IRQn	Active	SAR2, Logical Channel #0 Interrupt
141	pass_0_interrupts_sar_65_IRQn	Active	SAR2, Logical Channel #1 Interrupt
142	pass_0_interrupts_sar_66_IRQn	Active	SAR2, Logical Channel #2 Interrupt
143	pass_0_interrupts_sar_67_IRQn	Active	SAR2, Logical Channel #3 Interrupt
144	pass_0_interrupts_sar_68_IRQn	Active	SAR2, Logical Channel #4 Interrupt
145	pass_0_interrupts_sar_69_IRQn	Active	SAR2, Logical Channel #5 Interrupt
146	pass_0_interrupts_sar_70_IRQn	Active	SAR2, Logical Channel #6 Interrupt
147	pass_0_interrupts_sar_71_IRQn	Active	SAR2, Logical Channel #7 Interrupt
148	cpuss_interrupts_dmac_0_IRQn	Active	CPUSS M-DMA0, Channel #0 Interrupt
149	cpuss_interrupts_dmac_1_IRQn	Active	CPUSS M-DMA0, Channel #1 Interrupt
150	cpuss_interrupts_dmac_2_IRQn	Active	CPUSS M-DMA0, Channel #2 Interrupt
151	cpuss_interrupts_dmac_3_IRQn	Active	CPUSS M-DMA0, Channel #3 Interrupt
152	cpuss_interrupts_dw0_0_IRQn	Active	CPUSS P-DMA0, Channel #0 Interrupt
153	cpuss_interrupts_dw0_1_IRQn	Active	CPUSS P-DMA0, Channel #1 Interrupt
154	cpuss_interrupts_dw0_2_IRQn	Active	CPUSS P-DMA0, Channel #2 Interrupt
155	cpuss_interrupts_dw0_3_IRQn	Active	CPUSS P-DMA0, Channel #3 Interrupt
156	cpuss_interrupts_dw0_4_IRQn	Active	CPUSS P-DMA0, Channel #4 Interrupt
157	cpuss_interrupts_dw0_5_IRQn	Active	CPUSS P-DMA0, Channel #5 Interrupt
158	cpuss_interrupts_dw0_6_IRQn	Active	CPUSS P-DMA0, Channel #6 Interrupt
159	cpuss_interrupts_dw0_7_IRQn	Active	CPUSS P-DMA0, Channel #7 Interrupt
160	cpuss_interrupts_dw0_8_IRQn	Active	CPUSS P-DMA0, Channel #8 Interrupt
161	cpuss_interrupts_dw0_9_IRQn	Active	CPUSS P-DMA0, Channel #9 Interrupt
162	cpuss_interrupts_dw0_10_IRQn	Active	CPUSS P-DMA0, Channel #10 Interrupt
163	cpuss_interrupts_dw0_11_IRQn	Active	CPUSS P-DMA0, Channel #11 Interrupt
164	cpuss_interrupts_dw0_12_IRQn	Active	CPUSS P-DMA0, Channel #12 Interrupt
165	cpuss_interrupts_dw0_13_IRQn	Active	CPUSS P-DMA0, Channel #13 Interrupt
166	cpuss_interrupts_dw0_14_IRQn	Active	CPUSS P-DMA0, Channel #14 Interrupt
167	cpuss_interrupts_dw0_15_IRQn	Active	CPUSS P-DMA0, Channel #15 Interrupt
168	cpuss_interrupts_dw0_16_IRQn	Active	CPUSS P-DMA0, Channel #16 Interrupt
169	cpuss_interrupts_dw0_17_IRQn	Active	CPUSS P-DMA0, Channel #17 Interrupt
170	cpuss_interrupts_dw0_18_IRQn	Active	CPUSS P-DMA0, Channel #18 Interrupt
171	cpuss_interrupts_dw0_19_IRQn	Active	CPUSS P-DMA0, Channel #19 Interrupt
172	cpuss_interrupts_dw0_20_IRQn	Active	CPUSS P-DMA0, Channel #20 Interrupt
173	cpuss_interrupts_dw0_21_IRQn	Active	CPUSS P-DMA0, Channel #21 Interrupt
174	cpuss_interrupts_dw0_22_IRQn	Active	CPUSS P-DMA0, Channel #22 Interrupt
175	cpuss_interrupts_dw0_23_IRQn	Active	CPUSS P-DMA0, Channel #23 Interrupt
176	cpuss_interrupts_dw0_24_IRQn	Active	CPUSS P-DMA0, Channel #24 Interrupt
177	cpuss_interrupts_dw0_25_IRQn	Active	CPUSS P-DMA0, Channel #25 Interrupt
178	cpuss_interrupts_dw0_26_IRQn	Active	CPUSS P-DMA0, Channel #26 Interrupt
179	cpuss_interrupts_dw0_27_IRQn	Active	CPUSS P-DMA0, Channel #27 Interrupt
180	cpuss_interrupts_dw0_28_IRQn	Active	CPUSS P-DMA0, Channel #28 Interrupt
181	cpuss_interrupts_dw0_29_IRQn	Active	CPUSS P-DMA0, Channel #29 Interrupt
182	cpuss_interrupts_dw0_30_IRQn	Active	CPUSS P-DMA0, Channel #30 Interrupt
183	cpuss_interrupts_dw0_31_IRQn	Active	CPUSS P-DMA0, Channel #31 Interrupt
184	cpuss_interrupts_dw0_32_IRQn	Active	CPUSS P-DMA0, Channel #32 Interrupt
185	cpuss_interrupts_dw0_33_IRQn	Active	CPUSS P-DMA0, Channel #33 Interrupt
186	cpuss_interrupts_dw0_34_IRQn	Active	CPUSS P-DMA0, Channel #34 Interrupt
187	cpuss_interrupts_dw0_35_IRQn	Active	CPUSS P-DMA0, Channel #35 Interrupt
188	cpuss_interrupts_dw0_36_IRQn	Active	CPUSS P-DMA0, Channel #36 Interrupt
189	cpuss_interrupts_dw0_37_IRQn	Active	CPUSS P-DMA0, Channel #37 Interrupt
190	cpuss_interrupts_dw0_38_IRQn	Active	CPUSS P-DMA0, Channel #38 Interrupt
191	cpuss_interrupts_dw0_39_IRQn	Active	CPUSS P-DMA0, Channel #39 Interrupt
192	cpuss_interrupts_dw0_40_IRQn	Active	CPUSS P-DMA0, Channel #40 Interrupt
193	cpuss_interrupts_dw0_41_IRQn	Active	CPUSS P-DMA0, Channel #41 Interrupt
194	cpuss_interrupts_dw0_42_IRQn	Active	CPUSS P-DMA0, Channel #42 Interrupt
195	cpuss_interrupts_dw0_43_IRQn	Active	CPUSS P-DMA0, Channel #43 Interrupt
196	cpuss_interrupts_dw0_44_IRQn	Active	CPUSS P-DMA0, Channel #44 Interrupt
197	cpuss_interrupts_dw0_45_IRQn	Active	CPUSS P-DMA0, Channel #45 Interrupt
198	cpuss_interrupts_dw0_46_IRQn	Active	CPUSS P-DMA0, Channel #46 Interrupt
199	cpuss_interrupts_dw0_47_IRQn	Active	CPUSS P-DMA0, Channel #47 Interrupt
200	cpuss_interrupts_dw0_48_IRQn	Active	CPUSS P-DMA0, Channel #48 Interrupt
201	cpuss_interrupts_dw0_49_IRQn	Active	CPUSS P-DMA0, Channel #49 Interrupt
202	cpuss_interrupts_dw0_50_IRQn	Active	CPUSS P-DMA0, Channel #50 Interrupt
203	cpuss_interrupts_dw0_51_IRQn	Active	CPUSS P-DMA0, Channel #51 Interrupt
204	cpuss_interrupts_dw0_52_IRQn	Active	CPUSS P-DMA0, Channel #52 Interrupt
205	cpuss_interrupts_dw0_53_IRQn	Active	CPUSS P-DMA0, Channel #53 Interrupt
206	cpuss_interrupts_dw0_54_IRQn	Active	CPUSS P-DMA0, Channel #54 Interrupt
207	cpuss_interrupts_dw0_55_IRQn	Active	CPUSS P-DMA0, Channel #55 Interrupt
208	cpuss_interrupts_dw0_56_IRQn	Active	CPUSS P-DMA0, Channel #56 Interrupt
209	cpuss_interrupts_dw0_57_IRQn	Active	CPUSS P-DMA0, Channel #57 Interrupt
210	cpuss_interrupts_dw0_58_IRQn	Active	CPUSS P-DMA0, Channel #58 Interrupt
211	cpuss_interrupts_dw0_59_IRQn	Active	CPUSS P-DMA0, Channel #59 Interrupt
212	cpuss_interrupts_dw0_60_IRQn	Active	CPUSS P-DMA0, Channel #60 Interrupt
213	cpuss_interrupts_dw0_61_IRQn	Active	CPUSS P-DMA0, Channel #61 Interrupt
214	cpuss_interrupts_dw0_62_IRQn	Active	CPUSS P-DMA0, Channel #62 Interrupt
215	cpuss_interrupts_dw0_63_IRQn	Active	CPUSS P-DMA0, Channel #63 Interrupt
216	cpuss_interrupts_dw0_64_IRQn	Active	CPUSS P-DMA0, Channel #64 Interrupt
217	cpuss_interrupts_dw0_65_IRQn	Active	CPUSS P-DMA0, Channel #65 Interrupt
218	cpuss_interrupts_dw0_66_IRQn	Active	CPUSS P-DMA0, Channel #66 Interrupt
219	cpuss_interrupts_dw0_67_IRQn	Active	CPUSS P-DMA0, Channel #67 Interrupt
220	cpuss_interrupts_dw0_68_IRQn	Active	CPUSS P-DMA0, Channel #68 Interrupt
221	cpuss_interrupts_dw0_69_IRQn	Active	CPUSS P-DMA0, Channel #69 Interrupt
222	cpuss_interrupts_dw0_70_IRQn	Active	CPUSS P-DMA0, Channel #70 Interrupt
223	cpuss_interrupts_dw0_71_IRQn	Active	CPUSS P-DMA0, Channel #71 Interrupt
224	cpuss_interrupts_dw0_72_IRQn	Active	CPUSS P-DMA0, Channel #72 Interrupt
225	cpuss_interrupts_dw0_73_IRQn	Active	CPUSS P-DMA0, Channel #73 Interrupt
226	cpuss_interrupts_dw0_74_IRQn	Active	CPUSS P-DMA0, Channel #74 Interrupt
227	cpuss_interrupts_dw0_75_IRQn	Active	CPUSS P-DMA0, Channel #75 Interrupt
228	cpuss_interrupts_dw0_76_IRQn	Active	CPUSS P-DMA0, Channel #76 Interrupt
229	cpuss_interrupts_dw0_77_IRQn	Active	CPUSS P-DMA0, Channel #77 Interrupt
230	cpuss_interrupts_dw0_78_IRQn	Active	CPUSS P-DMA0, Channel #78 Interrupt
231	cpuss_interrupts_dw0_79_IRQn	Active	CPUSS P-DMA0, Channel #79 Interrupt
232	cpuss_interrupts_dw0_80_IRQn	Active	CPUSS P-DMA0, Channel #80 Interrupt
233	cpuss_interrupts_dw0_81_IRQn	Active	CPUSS P-DMA0, Channel #81 Interrupt
234	cpuss_interrupts_dw0_82_IRQn	Active	CPUSS P-DMA0, Channel #82 Interrupt
235	cpuss_interrupts_dw0_83_IRQn	Active	CPUSS P-DMA0, Channel #83 Interrupt
236	cpuss_interrupts_dw0_84_IRQn	Active	CPUSS P-DMA0, Channel #84 Interrupt
237	cpuss_interrupts_dw0_85_IRQn	Active	CPUSS P-DMA0, Channel #85 Interrupt
238	cpuss_interrupts_dw0_86_IRQn	Active	CPUSS P-DMA0, Channel #86 Interrupt
239	cpuss_interrupts_dw0_87_IRQn	Active	CPUSS P-DMA0, Channel #87 Interrupt
240	cpuss_interrupts_dw0_88_IRQn	Active	CPUSS P-DMA0, Channel #88 Interrupt
241	cpuss_interrupts_dw1_0_IRQn	Active	CPUSS P-DMA1, Channel #0 Interrupt
242	cpuss_interrupts_dw1_1_IRQn	Active	CPUSS P-DMA1, Channel #1 Interrupt
243	cpuss_interrupts_dw1_2_IRQn	Active	CPUSS P-DMA1, Channel #2 Interrupt
244	cpuss_interrupts_dw1_3_IRQn	Active	CPUSS P-DMA1, Channel #3 Interrupt
245	cpuss_interrupts_dw1_4_IRQn	Active	CPUSS P-DMA1, Channel #4 Interrupt
246	cpuss_interrupts_dw1_5_IRQn	Active	CPUSS P-DMA1, Channel #5 Interrupt
247	cpuss_interrupts_dw1_6_IRQn	Active	CPUSS P-DMA1, Channel #6 Interrupt
248	cpuss_interrupts_dw1_7_IRQn	Active	CPUSS P-DMA1, Channel #7 Interrupt
249	cpuss_interrupts_dw1_8_IRQn	Active	CPUSS P-DMA1, Channel #8 Interrupt
250	cpuss_interrupts_dw1_9_IRQn	Active	CPUSS P-DMA1, Channel #9 Interrupt
251	cpuss_interrupts_dw1_10_IRQn	Active	CPUSS P-DMA1, Channel #10 Interrupt
252	cpuss_interrupts_dw1_11_IRQn	Active	CPUSS P-DMA1, Channel #11 Interrupt
253	cpuss_interrupts_dw1_12_IRQn	Active	CPUSS P-DMA1, Channel #12 Interrupt
254	cpuss_interrupts_dw1_13_IRQn	Active	CPUSS P-DMA1, Channel #13 Interrupt
255	cpuss_interrupts_dw1_14_IRQn	Active	CPUSS P-DMA1, Channel #14 Interrupt
256	cpuss_interrupts_dw1_15_IRQn	Active	CPUSS P-DMA1, Channel #15 Interrupt
257	cpuss_interrupts_dw1_16_IRQn	Active	CPUSS P-DMA1, Channel #16 Interrupt
258	cpuss_interrupts_dw1_17_IRQn	Active	CPUSS P-DMA1, Channel #17 Interrupt
259	cpuss_interrupts_dw1_18_IRQn	Active	CPUSS P-DMA1, Channel #18 Interrupt
260	cpuss_interrupts_dw1_19_IRQn	Active	CPUSS P-DMA1, Channel #19 Interrupt
261	cpuss_interrupts_dw1_20_IRQn	Active	CPUSS P-DMA1, Channel #20 Interrupt
262	cpuss_interrupts_dw1_21_IRQn	Active	CPUSS P-DMA1, Channel #21 Interrupt
263	cpuss_interrupts_dw1_22_IRQn	Active	CPUSS P-DMA1, Channel #22 Interrupt
264	cpuss_interrupts_dw1_23_IRQn	Active	CPUSS P-DMA1, Channel #23 Interrupt
265	cpuss_interrupts_dw1_24_IRQn	Active	CPUSS P-DMA1, Channel #24 Interrupt
266	cpuss_interrupts_dw1_25_IRQn	Active	CPUSS P-DMA1, Channel #25 Interrupt
267	cpuss_interrupts_dw1_26_IRQn	Active	CPUSS P-DMA1, Channel #26 Interrupt
268	cpuss_interrupts_dw1_27_IRQn	Active	CPUSS P-DMA1, Channel #27 Interrupt
269	cpuss_interrupts_dw1_28_IRQn	Active	CPUSS P-DMA1, Channel #28 Interrupt
270	cpuss_interrupts_dw1_29_IRQn	Active	CPUSS P-DMA1, Channel #29 Interrupt
271	cpuss_interrupts_dw1_30_IRQn	Active	CPUSS P-DMA1, Channel #30 Interrupt
272	cpuss_interrupts_dw1_31_IRQn	Active	CPUSS P-DMA1, Channel #31 Interrupt
273	cpuss_interrupts_dw1_32_IRQn	Active	CPUSS P-DMA1, Channel #32 Interrupt
274	tcpwm_0_interrupts_0_IRQn	Active	TCPWM0 Group #0, Counter #0 Interrupt
275	tcpwm_0_interrupts_1_IRQn	Active	TCPWM0 Group #0, Counter #1 Interrupt
276	tcpwm_0_interrupts_2_IRQn	Active	TCPWM0 Group #0, Counter #2 Interrupt
277	tcpwm_0_interrupts_3_IRQn	Active	TCPWM0 Group #0, Counter #3 Interrupt
278	tcpwm_0_interrupts_4_IRQn	Active	TCPWM0 Group #0, Counter #4 Interrupt
279	tcpwm_0_interrupts_5_IRQn	Active	TCPWM0 Group #0, Counter #5 Interrupt
280	tcpwm_0_interrupts_6_IRQn	Active	TCPWM0 Group #0, Counter #6 Interrupt
281	tcpwm_0_interrupts_7_IRQn	Active	TCPWM0 Group #0, Counter #7 Interrupt
282	tcpwm_0_interrupts_8_IRQn	Active	TCPWM0 Group #0, Counter #8 Interrupt
283	tcpwm_0_interrupts_9_IRQn	Active	TCPWM0 Group #0, Counter #9 Interrupt
284	tcpwm_0_interrupts_10_IRQn	Active	TCPWM0 Group #0, Counter #10 Interrupt
285	tcpwm_0_interrupts_11_IRQn	Active	TCPWM0 Group #0, Counter #11 Interrupt
286	tcpwm_0_interrupts_12_IRQn	Active	TCPWM0 Group #0, Counter #12 Interrupt
287	tcpwm_0_interrupts_13_IRQn	Active	TCPWM0 Group #0, Counter #13 Interrupt
288	tcpwm_0_interrupts_14_IRQn	Active	TCPWM0 Group #0, Counter #14 Interrupt
289	tcpwm_0_interrupts_15_IRQn	Active	TCPWM0 Group #0, Counter #15 Interrupt
290	tcpwm_0_interrupts_16_IRQn	Active	TCPWM0 Group #0, Counter #16 Interrupt
291	tcpwm_0_interrupts_17_IRQn	Active	TCPWM0 Group #0, Counter #17 Interrupt
292	tcpwm_0_interrupts_18_IRQn	Active	TCPWM0 Group #0, Counter #18 Interrupt
293	tcpwm_0_interrupts_19_IRQn	Active	TCPWM0 Group #0, Counter #19 Interrupt
294	tcpwm_0_interrupts_20_IRQn	Active	TCPWM0 Group #0, Counter #20 Interrupt
295	tcpwm_0_interrupts_21_IRQn	Active	TCPWM0 Group #0, Counter #21 Interrupt
296	tcpwm_0_interrupts_22_IRQn	Active	TCPWM0 Group #0, Counter #22 Interrupt
297	tcpwm_0_interrupts_23_IRQn	Active	TCPWM0 Group #0, Counter #23 Interrupt
298	tcpwm_0_interrupts_24_IRQn	Active	TCPWM0 Group #0, Counter #24 Interrupt
299	tcpwm_0_interrupts_25_IRQn	Active	TCPWM0 Group #0, Counter #25 Interrupt
300	tcpwm_0_interrupts_26_IRQn	Active	TCPWM0 Group #0, Counter #26 Interrupt
301	tcpwm_0_interrupts_27_IRQn	Active	TCPWM0 Group #0, Counter #27 Interrupt
302	tcpwm_0_interrupts_28_IRQn	Active	TCPWM0 Group #0, Counter #28 Interrupt
303	tcpwm_0_interrupts_29_IRQn	Active	TCPWM0 Group #0, Counter #29 Interrupt
304	tcpwm_0_interrupts_30_IRQn	Active	TCPWM0 Group #0, Counter #30 Interrupt
305	tcpwm_0_interrupts_31_IRQn	Active	TCPWM0 Group #0, Counter #31 Interrupt
306	tcpwm_0_interrupts_32_IRQn	Active	TCPWM0 Group #0, Counter #32 Interrupt
307	tcpwm_0_interrupts_33_IRQn	Active	TCPWM0 Group #0, Counter #33 Interrupt
308	tcpwm_0_interrupts_34_IRQn	Active	TCPWM0 Group #0, Counter #34 Interrupt
309	tcpwm_0_interrupts_35_IRQn	Active	TCPWM0 Group #0, Counter #35 Interrupt
310	tcpwm_0_interrupts_36_IRQn	Active	TCPWM0 Group #0, Counter #36 Interrupt
311	tcpwm_0_interrupts_37_IRQn	Active	TCPWM0 Group #0, Counter #37 Interrupt
312	tcpwm_0_interrupts_38_IRQn	Active	TCPWM0 Group #0, Counter #38 Interrupt
313	tcpwm_0_interrupts_39_IRQn	Active	TCPWM0 Group #0, Counter #39 Interrupt
314	tcpwm_0_interrupts_40_IRQn	Active	TCPWM0 Group #0, Counter #40 Interrupt
315	tcpwm_0_interrupts_41_IRQn	Active	TCPWM0 Group #0, Counter #41 Interrupt
316	tcpwm_0_interrupts_42_IRQn	Active	TCPWM0 Group #0, Counter #42 Interrupt
317	tcpwm_0_interrupts_43_IRQn	Active	TCPWM0 Group #0, Counter #43 Interrupt
318	tcpwm_0_interrupts_44_IRQn	Active	TCPWM0 Group #0, Counter #44 Interrupt
319	tcpwm_0_interrupts_45_IRQn	Active	TCPWM0 Group #0, Counter #45 Interrupt
320	tcpwm_0_interrupts_46_IRQn	Active	TCPWM0 Group #0, Counter #46 Interrupt
321	tcpwm_0_interrupts_47_IRQn	Active	TCPWM0 Group #0, Counter #47 Interrupt
322	tcpwm_0_interrupts_48_IRQn	Active	TCPWM0 Group #0, Counter #48 Interrupt
323	tcpwm_0_interrupts_49_IRQn	Active	TCPWM0 Group #0, Counter #49 Interrupt
324	tcpwm_0_interrupts_50_IRQn	Active	TCPWM0 Group #0, Counter #50 Interrupt
325	tcpwm_0_interrupts_51_IRQn	Active	TCPWM0 Group #0, Counter #51 Interrupt
326	tcpwm_0_interrupts_52_IRQn	Active	TCPWM0 Group #0, Counter #52 Interrupt
327	tcpwm_0_interrupts_53_IRQn	Active	TCPWM0 Group #0, Counter #53 Interrupt
328	tcpwm_0_interrupts_54_IRQn	Active	TCPWM0 Group #0, Counter #54 Interrupt
329	tcpwm_0_interrupts_55_IRQn	Active	TCPWM0 Group #0, Counter #55 Interrupt
330	tcpwm_0_interrupts_56_IRQn	Active	TCPWM0 Group #0, Counter #56 Interrupt
331	tcpwm_0_interrupts_57_IRQn	Active	TCPWM0 Group #0, Counter #57 Interrupt
332	tcpwm_0_interrupts_58_IRQn	Active	TCPWM0 Group #0, Counter #58 Interrupt
333	tcpwm_0_interrupts_59_IRQn	Active	TCPWM0 Group #0, Counter #59 Interrupt
334	tcpwm_0_interrupts_60_IRQn	Active	TCPWM0 Group #0, Counter #60 Interrupt
335	tcpwm_0_interrupts_61_IRQn	Active	TCPWM0 Group #0, Counter #61 Interrupt
336	tcpwm_0_interrupts_62_IRQn	Active	TCPWM0 Group #0, Counter #62 Interrupt
337	tcpwm_0_interrupts_256_IRQn	Active	TCPWM0 Group #1, Counter #0 Interrupt
338	tcpwm_0_interrupts_257_IRQn	Active	TCPWM0 Group #1, Counter #1 Interrupt
339	tcpwm_0_interrupts_258_IRQn	Active	TCPWM0 Group #1, Counter #2 Interrupt
340	tcpwm_0_interrupts_259_IRQn	Active	TCPWM0 Group #1, Counter #3 Interrupt
341	tcpwm_0_interrupts_260_IRQn	Active	TCPWM0 Group #1, Counter #4 Interrupt
342	tcpwm_0_interrupts_261_IRQn	Active	TCPWM0 Group #1, Counter #5 Interrupt
343	tcpwm_0_interrupts_262_IRQn	Active	TCPWM0 Group #1, Counter #6 Interrupt
344	tcpwm_0_interrupts_263_IRQn	Active	TCPWM0 Group #1, Counter #7 Interrupt
345	tcpwm_0_interrupts_264_IRQn	Active	TCPWM0 Group #1, Counter #8 Interrupt
346	tcpwm_0_interrupts_265_IRQn	Active	TCPWM0 Group #1, Counter #9 Interrupt
347	tcpwm_0_interrupts_266_IRQn	Active	TCPWM0 Group #1, Counter #10 Interrupt
348	tcpwm_0_interrupts_267_IRQn	Active	TCPWM0 Group #1, Counter #11 Interrupt
349	tcpwm_0_interrupts_512_IRQn	Active	TCPWM0 Group #2, Counter #0 Interrupt
350	tcpwm_0_interrupts_513_IRQn	Active	TCPWM0 Group #2, Counter #1 Interrupt
351	tcpwm_0_interrupts_514_IRQn	Active	TCPWM0 Group #2, Counter #2 Interrupt
352	tcpwm_0_interrupts_515_IRQn	Active	TCPWM0 Group #2, Counter #3 Interrupt

Core interrupt types

Table 19.
Core interrupt types
Interrupt	Source	Power Mode	Description
0	CPUIntIdx0_IRQn	DeepSleep	CPU User Interrupt #0
1	CPUIntIdx1_IRQn ³⁰	DeepSleep	CPU User Interrupt #1
2	CPUIntIdx2_IRQn	DeepSleep	CPU User Interrupt #2
3	CPUIntIdx3_IRQn	DeepSleep	CPU User Interrupt #3
4	CPUIntIdx4_IRQn	DeepSleep	CPU User Interrupt #4
5	CPUIntIdx5_IRQn	DeepSleep	CPU User Interrupt #5
6	CPUIntIdx6_IRQn	DeepSleep	CPU User Interrupt #6
7	CPUIntIdx7_IRQn	DeepSleep	CPU User Interrupt #7
8	Internal0_IRQn	Active	Internal Software Interrupt #0
9	Internal1_IRQn	Active	Internal Software Interrupt #1
10	Internal2_IRQn	Active	Internal Software Interrupt #2
11	Internal3_IRQn	Active	Internal Software Interrupt #3
12	Internal4_IRQn	Active	Internal Software Interrupt #4
13	Internal5_IRQn	Active	Internal Software Interrupt #5
14	Internal6_IRQn	Active	Internal Software Interrupt #6
15	Internal7_IRQn	Active	Internal Software Interrupt #7

Trigger multiplexer

Triggers group inputs

Table 20.
Trigger inputs
Input	Trigger Label (TRIG_LABEL)	Description
MUX Group 0 : PDMA0_TR (P-DMA0_0_15 trigger multiplexer)
1:16 ³²	PDMA0_TR_OUT[0:15]	Allow P-DMA0 to chain to itself, useful for triggering once per row for 2D transfer
17:24	PDMA1_TR_OUT[0:7]	Cross connections from P-DMA1 to P-DMA0, Channels 0-7 are used
25:28	MDMA_TR_OUT[0:3]	Cross connections from M-DMA0 to P-DMA0
29:32	FAULT_TR_OUT[0:3]	Allow faults to initiate data transfer for debug purposes
33:34	CTI_TR_OUT[0:1]	Trace events
35:38	EVTGEN_TR_OUT[3:6]	EVTGEN triggers
39:54	HSIOM_IO_INPUT[0:15]	I/O inputs
MUX Group 1 : PDMA1_TR (P-DMA1 trigger multiplexer)
1:16	PDMA0_TR_OUT[0:15]	Allow P-DMA0 to trigger P-DMA1
17:24	PDMA1_TR_OUT[0:7]	Allow P-DMA1 to chain to itself, useful for triggering once per row for 2D transfer
25:28	MDMA_TR_OUT[0:3]	Allow M-DMA0 to trigger P-DMA0
29:32	FAULT_TR_OUT[0:3]	Allow faults to initiate data transfer for debug purposes
33:34	CTI_TR_OUT[0:1]	Trace events
35:38	EVTGEN_TR_OUT[7:10]	EVTGEN triggers
39:54	HSIOM_IO_INPUT[16:31]	I/O inputs
55:60	PASS_GEN_TR_OUT[0:5]	PASS SAR events
MUX Group 2: MDMA (M-DMA0 trigger multiplexer)
1:4	MDMA_TR_OUT[0:3]	Allow M-DMA0 to trigger itself
MUX Group 3: TCPWM_TO_PDMA0 (TCPWM0 to P-DMA0 trigger multiplexer)
1:4	TCPWM_32_TR_OUT0[0:3]	32-bit TCPWM0 counters
5:16	TCPWM_16M_TR_OUT0[0:11]	16-bit Motor enhanced TCPWM0 counters
17:79	TCPWM_16_TR_OUT0[0:62]	16-bit TCPWM0 counters
80:82	CAN0_TT_TR_OUT[0:2]	CAN0 TT Sync Outputs
83:85	CAN1_TT_TR_OUT[0:2]	CAN1 TT Sync Outputs
MUX Group 4: TCPWM_OUT (TCPWM0 loop back multiplexer)
1:4	TCPWM_32_TR_OUT0[0:3]	32-bit TCPWM0 counters
5:16	TCPWM_16M_TR_OUT0[0:11]	16-bit Motor enhanced TCPWM0 counters
17:79	TCPWM_16_TR_OUT0[0:62]	16-bit TCPWM0 counters
80:87	TCPWM_16_TR_OUT1[0:7]	Allows feedback of two signals from same counters
88:90	CAN0_TT_TR_OUT[0:2]	CAN0 TT Sync Outputs
91:93	CAN1_TT_TR_OUT[0:2]	CAN1 TT Sync Outputs
MUX Group 5: TCPWM_IN (TCPWM0 Trigger Multiplexer)
1:16	PDMA0_TR_OUT[0:15]	General purpose P-DMA0 triggers
17:24	PDMA1_TR_OUT[0:7]	General purpose P-DMA1 triggers
25:28	MDMA_TR_OUT[0:3]	M-DMA0 triggers
29:30	CTI_TR_OUT[0:1]	Trace events
31:34	FAULT_TR_OUT[0:3]	Fault events
35:40	PASS_GEN_TR_OUT[0:5]	PASS SAR events
41:72	HSIOM_IO_INPUT[0:31]	I/O inputs
73	SCB_TX_TR_OUT[0]	SCB0 TX trigger
74	SCB_RX_TR_OUT[0]	SCB0 RX trigger
75	SCB_I ² C_SCL_TR_OUT[0]	SCB0 I ² C trigger
76	SCB_TX_TR_OUT[1]	SCB1 TX trigger
77	SCB_RX_TR_OUT[1]	SCB1 RX trigger
78	SCB_I ² C_SCL_TR_OUT[1]	SCB1 I ² C trigger
79	SCB_TX_TR_OUT[2]	SCB2 TX trigger
80	SCB_RX_TR_OUT[2]	SCB2 RX trigger
81	SCB_I ² C_SCL_TR_OUT[2]	SCB2 I ² C trigger
82	SCB_TX_TR_OUT[3]	SCB3 TX trigger
83	SCB_RX_TR_OUT[3]	SCB3 RX trigger
84	SCB_I ² C_SCL_TR_OUT[3]	SCB3 I ² C trigger
85	SCB_TX_TR_OUT[4]	SCB4 TX trigger
86	SCB_RX_TR_OUT[4]	SCB4 RX trigger
87	SCB_I ² C_SCL_TR_OUT[4]	SCB4 I ² C trigger
88	SCB_TX_TR_OUT[5]	SCB5 TX trigger
89	SCB_RX_TR_OUT[5]	SCB5 RX trigger
90	SCB_I ² C_SCL_TR_OUT[5]	SCB5 I ² C trigger
91	SCB_TX_TR_OUT[6]	SCB6 TX trigger
92	SCB_RX_TR_OUT[6]	SCB6 RX trigger
93	SCB_I ² C_SCL_TR_OUT[6]	SCB6 I ² C trigger
94	SCB_TX_TR_OUT[7]	SCB7 TX trigger
95	SCB_RX_TR_OUT[7]	SCB7 RX trigger
96	SCB_I ² C_SCL_TR_OUT[7]	SCB7 I ² C trigger
97:99	CAN0_DBG_TR_OUT[0:2]	CAN0 M-DMA0 events
100:102	CAN0_FIFO0_TR_OUT[0:2]	CAN0 FIFO0 events
103:105	CAN0_FIFO1_TR_OUT[0:2]	CAN0 FIFO1 events
106:108	CAN1_DBG_TR_OUT[0:2]	CAN1 M-DMA0 events
109:111	CAN1_FIFO0_TR_OUT[0:2]	CAN1 FIFO0 events
112:114	CAN1_FIFO1_TR_OUT[0:2]	CAN1 FIFO1 events
115:122	EVTGEN_TR_OUT[3:10]	EVTGEN triggers
MUX Group 6: PASS (PASS SAR trigger multiplexer)
1:16	PDMA0_TR_OUT[0:15]	General purpose P-DMA0 triggers
17:18	CTI_TR_OUT[0:1]	Trace events
19:22	FAULT_TR_OUT[0:3]	Fault events
23:25	EVTGEN_TR_OUT[0:2]	EVTGEN triggers
26:31	PASS_GEN_TR_OUT[0:5]	PASS SAR done signals
32:63	HSIOM_IO_INPUT[0:31]	I/O inputs
64:67	TCPWM_32_TR_OUT1[0:3]	32-bit TCPWM0 counters
68:79	TCPWM_16M_TR_OUT1[0:11]	16-bit Motor enhanced TCPWM0 counters
MUX Group 7: CAN TT sync triggers
1:3	CAN0_TT_TR_OUT[0:2]	CAN0 TT Sync Outputs
4:6	CAN1_TT_TR_OUT[0:2]	CAN1 TT Sync Outputs
MUX Group 8: DebugMain (Debug Multiplexer)
1:5	TR_GROUP9_OUTPUT[0:4]	Output from debug reduction multiplexer #1
6:10	TR_GROUP10_OUTPUT[0:4]	Output from debug reduction multiplexer #2
MUX Group 9: DebugReduction1 (Debug Reduction #1)
1:89	PDMA0_TR_OUT[0:88]	P-DMA0 triggers
90:97	SCB_TX_TR_OUT[0:7]	SCB TTCAN tx Triggers
98:105	SCB_RX_TR_OUT[0:7]	SCB TTCAN rx Triggers
106:113	SCB_I ² C_SCL_TR_OUT[0:7]	SCB I ² C triggers
114:116	CAN0_DBG_TR_OUT[0:2]	CAN0 P-DMA
117:119	CAN0_FIFO0_TR_OUT[0:2]	CAN0 FIFO0
120:122	CAN0_FIFO1_TR_OUT[0:2]	CAN0 FIFO1
123:125	CAN0_TT_TR_OUT[0:2]	CAN TT Sync Outputs
126:128	CAN1_DBG_TR_OUT[0:2]	CAN1 P-DMA
129:131	CAN1_FIFO0_TR_OUT[0:2]	CAN1 FIFO0
132:134	CAN1_FIFO1_TR_OUT[0:2]	CAN1 FIFO1
135:137	CAN1_TT_TR_OUT[0:2]	CAN TT Sync Outputs
138:139	CTI_TR_OUT[0:1]	Trace events
140:143	FAULT_TR_OUT[0:3]	Fault events
144:147	TCPWM_32_TR_OUT0[0:3]	32-bit TCPWM0 counters
148:159	TCPWM_16M_TR_OUT0[0:11]	16-bit Motor enhanced TCPWM0 counters
160:222	TCPWM_16_TR_OUT0[0:62]	16-bit TCPWM0 counters
MUX Group 10: DebugReduction2 (Debug Reduction #2)
1:33	PDMA1_TR_OUT[0:32]	16-bit Motor enhanced TCPWM0 counters
34:37	MDMA_TR_OUT[0:3]	16-bit TCPWM0 counters
38:41	TCPWM_32_TR_OUT1[0:3]	32-bit TCPWM0 counters
42:53	TCPWM_16M_TR_OUT1[0:11]	16-bit Motor enhanced TCPWM0 counters
54:116	TCPWM_16_TR_OUT1[0:62]	16-bit TCPWM0 counters
117:122	PASS_GEN_TR_OUT[0:5]	PASS SAR conversion complete events
123:133	EVTGEN_TR_OUT[0:10]	EVTGEN Triggers

Triggers group outputs

Table 21.
Trigger outputs
Output	Trigger Label(TRIG_LABEL)	Description
MUX Group 0: PDMA0_TR (P-DMA0 trigger multiplexer)
0:7	PDMA0_TR_IN[0:7]	Triggers to P-DMA0[0:7]
MUX Group 1: PDMA1_TR (P-DMA1 trigger multiplexer)
0:7	PDMA1_TR_IN[0:7]	Triggers to P-DMA1[0:7]
MUX Group 2: MDMA (M-DMA0 trigger multiplexer)
0:3	MDMA_TR_IN[0:3]	Triggers to M-DMA0
MUX Group 3: TCPWM_TO_PDMA0 (TCPWM0 to P-DMA0 trigger multiplexer)
0:7	PDMA0_TR_IN[8:15]	Triggers to P-DMA0[8:15]
MUX Group 4: TCPWM_OUT (TCPWM0 loop back multiplexer)
0:15	TCPWM_ALL_CNT_TR_IN[0:15]	All counters trigger input
MUX Group 5: TCPWM_IN (TCPWM0 Trigger Multiplexer)
0:10	TCPWM_ALL_CNT_TR_IN[16:26]	Triggers to TCPWM0
MUX Group 6: PASS (PASS SAR trigger multiplexer)
0:11	PASS_GEN_TR_IN[0:11]	Triggers to SAR ADCs
MUX Group 7: CANTT (CAN TT Sync)
0:2	CAN0_TT_TR_IN[0:2]	CAN0 TT Sync Inputs
3:5	CAN1_TT_TR_IN[0:2]	CAN1 TT Sync Inputs
MUX Group 8: DebugMain (Debug Multiplexer)
0:1	HSIOM_IO_OUTPUT[0:1]	To HSIOM as an output
2:3	CTI_TR_IN[0:1]	To CPU Cross Trigger system
4	PERI_DEBUG_FREEZE_TR_IN	Signal to Freeze PERI operation
5	PASS_DEBUG_FREEZE_TR_IN	Signal to Freeze SAR ADC operation
6	SRSS_WDT_DEBUG_FREEZE_TR_IN	Signal to Freeze WDT operation
7:8	SRSS_MCWDT_DEBUG_FREEZE_TR_IN[0:1]	Signal to Freeze MCWDT operation
9	TCPWM_DEBUG_FREEZE_TR_IN	Signal to Freeze TCPWM0 operation
MUX Group 9: DebugReduction1 (Debug Reduction #1)
0:4	TR_GROUP8_INPUT[1:5]	To main debug multiplexer
MUX Group 10: DebugReduction2 (Debug Reduction #2)
0:4	TR_GROUP8_INPUT[6:10]	To main debug multiplexer

Triggers one-to-one

Table 22.
Triggers 1:1
Input	Trigger In	Trigger Out	Description
MUX Group 0: TCPWM0 to LIN0 Triggers
0:7	TCPWM0_16_TR_OUT0[0:7]	LIN0_CMD_TR_IN[0:7]	TCPWM0 (Group #0 Counter #00 to #07) to LIN0
MUX Group 1: TCPWM0 to PASS SARx direct connect
0	TCPWM0_16M_TR_OUT1[0]	PASS0_CH_TR_IN[0]	TCPWM0 Group #1 Counter #00 (PWM0_M_0) to SAR0 ch#0
1	TCPWM0_16M_TR_OUT1[1]	PASS0_CH_TR_IN[1]	TCPWM0 Group #1 Counter #03 (PWM0_M_3) to SAR0 ch#1
2	TCPWM0_16M_TR_OUT1[2]	PASS0_CH_TR_IN[2]	TCPWM0 Group #1 Counter #06 (PWM0_M_6) to SAR0 ch#2
3	TCPWM0_16M_TR_OUT1[3]	PASS0_CH_TR_IN[3]	TCPWM0 Group #1 Counter #09 (PWM0_M_9) to SAR0 ch#3
4:23	TCPWM0_16_TR_OUT1[0:19]	PASS0_CH_TR_IN[4:23]	TCPWM0 Group #0 Counter #00 through 19 (PWM0_0 to PWM0_19) to SAR0 ch#4 through SAR0 ch#23
24	TCPWM0_16M_TR_OUT1[4]	PASS0_CH_TR_IN[32]	TCPWM0 Group #1 Counter #01 (PWM0_M_1) to SAR1 ch#0
25	TCPWM0_16M_TR_OUT1[5]	PASS0_CH_TR_IN[33]	TCPWM0 Group #1 Counter #04 (PWM0_M_4) to SAR1 ch#1
26	TCPWM0_16M_TR_OUT1[6]	PASS0_CH_TR_IN[34]	TCPWM0 Group #1 Counter #07 (PWM0_M_7) to SAR1 ch#2
27	TCPWM0_16M_TR_OUT1[7]	PASS0_CH_TR_IN[35]	TCPWM0 Group #1 Counter #10 (PWM0_M_10) to SAR1 ch#3
28:55	TCPWM0_16_TR_OUT1[20:47]	PASS0_CH_TR_IN[36:63]	TCPWM0 Group #0 Counter #20 through 47 (PWM0_20 to PWM0_47) to SAR1 ch#4 through SAR1 ch#31
56	TCPWM0_16M_TR_OUT1[8]	PASS0_CH_TR_IN[64]	TCPWM0 Group #1 Counter #02 (PWM0_M_2) to SAR2 ch#0
57	TCPWM0_16M_TR_OUT1[9]	PASS0_CH_TR_IN[65]	TCPWM0 Group #1 Counter #05 (PWM0_M_5) to SAR2 ch#1
58	TCPWM0_16M_TR_OUT1[10]	PASS0_CH_TR_IN[66]	TCPWM0 Group #1 Counter #08 (PWM0_M_8) to SAR2 ch#2
59	TCPWM0_16M_TR_OUT1[11]	PASS0_CH_TR_IN[67]	TCPWM0 Group #1 Counter #11 (PWM0_M_11) to SAR2 ch#3
60:63	TCPWM0_16_TR_OUT1[48:51]	PASS0_CH_TR_IN[68:71]	TCPWM0 Group #0 Counter #48 through 51 (PWM0_48 to PWM0_51) to SAR2 ch#4 through SAR2 ch#7
MUX Group 2: PASS SARx to P-DMA0 direct connect
0:23	PASS0_CH_DONE_TR_OUT[0:23]	PDMA0_TR_IN[25:48]	PASS SAR0 [0:23] to P-DMA0 direct connect
24:55	PASS0_CH_DONE_TR_OUT[32:63]	PDMA0_TR_IN[49:80]	PASS SAR1 [0:31] to P-DMA0 direct connect
56:63	PASS0_CH_DONE_TR_OUT[64:71]	PDMA0_TR_IN[81:88]	PASS SAR2 [0:7] to P-DMA0 direct connect
MUX Group 3: PASS SARx to TCPWM0 direct connect
0	PASS0_CH_RANGEVIO_TR_OUT[0]	TCPWM0_16M_ONE_CNT_TR_IN[0]	SAR0 ch#0 ³³ ,range violation to TCPWM0 Group #1 Counter #00 trig=4
1	PASS0_CH_RANGEVIO_TR_OUT[1]	TCPWM0_16M_ONE_CNT_TR_IN[3]	SAR0 ch#1, range violation to TCPWM0 Group #1 Counter #03 trig=4
2	PASS0_CH_RANGEVIO_TR_OUT[2]	TCPWM0_16M_ONE_CNT_TR_IN[6]	SAR0 ch#2, range violation to TCPWM0 Group #1 Counter #06 trig=4
3	PASS0_CH_RANGEVIO_TR_OUT[3]	TCPWM0_16M_ONE_CNT_TR_IN[9]	SAR0 ch#3, range violation to TCPWM0 Group #1 Counter #09 trig=4
4	PASS0_CH_RANGEVIO_TR_OUT[4]	TCPWM0_16_ONE_CNT_TR_IN[0]	SAR0 ch#4, range violation to TCPWM0 Group #0 Counter #00 trig=4
5	PASS0_CH_RANGEVIO_TR_OUT[5]	TCPWM0_16_ONE_CNT_TR_IN[1]	SAR0 ch#5, range violation to TCPWM0 Group #0 Counter #01 trig=4
6	PASS0_CH_RANGEVIO_TR_OUT[6]	TCPWM0_16_ONE_CNT_TR_IN[2]	SAR0 ch#6, range violation to TCPWM0 Group #0 Counter #02 trig=4
7	PASS0_CH_RANGEVIO_TR_OUT[7]	TCPWM0_16_ONE_CNT_TR_IN[3]	SAR0 ch#7, range violation to TCPWM0 Group #0 Counter #03 trig=4
8	PASS0_CH_RANGEVIO_TR_OUT[8]	TCPWM0_16_ONE_CNT_TR_IN[4]	SAR0 ch#8, range violation to TCPWM0 Group #0 Counter #04 trig=4
9	PASS0_CH_RANGEVIO_TR_OUT[9]	TCPWM0_16_ONE_CNT_TR_IN[5]	SAR0 ch#9, range violation to TCPWM0 Group #0 Counter #05 trig=4
10	PASS0_CH_RANGEVIO_TR_OUT[10]	TCPWM0_16_ONE_CNT_TR_IN[6]	SAR0 ch#10, range violation to TCPWM0 Group #0 Counter #06 trig=4
11	PASS0_CH_RANGEVIO_TR_OUT[11]	TCPWM0_16_ONE_CNT_TR_IN[7]	SAR0 ch#11, range violation to TCPWM0 Group #0 Counter #07 trig=4
12	PASS0_CH_RANGEVIO_TR_OUT[12]	TCPWM0_16_ONE_CNT_TR_IN[8]	SAR0 ch#12, range violation to TCPWM0 Group #0 Counter #08 trig=4
13	PASS0_CH_RANGEVIO_TR_OUT[13]	TCPWM0_16_ONE_CNT_TR_IN[9]	SAR0 ch#13, range violation to TCPWM0 Group #0 Counter #09 trig=4
14	PASS0_CH_RANGEVIO_TR_OUT[14]	TCPWM0_16_ONE_CNT_TR_IN[10]	SAR0 ch#14, range violation to TCPWM0 Group #0 Counter #10 trig=4
15	PASS0_CH_RANGEVIO_TR_OUT[15]	TCPWM0_16_ONE_CNT_TR_IN[11]	SAR0 ch#15, range violation to TCPWM0 Group #0 Counter #11 trig=4
16	PASS0_CH_RANGEVIO_TR_OUT[16]	TCPWM0_16_ONE_CNT_TR_IN[12]	SAR0 ch#16, range violation to TCPWM0 Group #0 Counter #12 trig=4
17	PASS0_CH_RANGEVIO_TR_OUT[17]	TCPWM0_16_ONE_CNT_TR_IN[13]	SAR0 ch#17, range violation to TCPWM0 Group #0 Counter #13 trig=4
18	PASS0_CH_RANGEVIO_TR_OUT[18]	TCPWM0_16_ONE_CNT_TR_IN[14]	SAR0 ch#18, range violation to TCPWM0 Group #0 Counter #14 trig=4
19	PASS0_CH_RANGEVIO_TR_OUT[19]	TCPWM0_16_ONE_CNT_TR_IN[15]	SAR0 ch#19, range violation to TCPWM0 Group #0 Counter #15 trig=4
20	PASS0_CH_RANGEVIO_TR_OUT[20]	TCPWM0_16_ONE_CNT_TR_IN[16]	SAR0 ch#20, range violation to TCPWM0 Group #0 Counter #16 trig=4
21	PASS0_CH_RANGEVIO_TR_OUT[21]	TCPWM0_16_ONE_CNT_TR_IN[17]	SAR0 ch#21, range violation to TCPWM0 Group #0 Counter #17 trig=4
22	PASS0_CH_RANGEVIO_TR_OUT[22]	TCPWM0_16_ONE_CNT_TR_IN[18]	SAR0 ch#22, range violation to TCPWM0 Group #0 Counter #18 trig=4
23	PASS0_CH_RANGEVIO_TR_OUT[23]	TCPWM0_16_ONE_CNT_TR_IN[19]	SAR0 ch#23, range violation to TCPWM0 Group #0 Counter #19 trig=4
24	PASS0_CH_RANGEVIO_TR_OUT[32]	TCPWM0_16M_ONE_CNT_TR_IN[1]	SAR1 ch#0, range violation to TCPWM0 Group #1 Counter #01 trig=4
25	PASS0_CH_RANGEVIO_TR_OUT[33]	TCPWM0_16M_ONE_CNT_TR_IN[4]	SAR1 ch#1, range violation to TCPWM0 Group #1 Counter #04 trig=4
26	PASS0_CH_RANGEVIO_TR_OUT[34]	TCPWM0_16M_ONE_CNT_TR_IN[7]	SAR1 ch#2, range violation to TCPWM0 Group #1 Counter #07 trig=4
27	PASS0_CH_RANGEVIO_TR_OUT[35]	TCPWM0_16M_ONE_CNT_TR_IN[10]	SAR1 ch#3, range violation to TCPWM0 Group #1 Counter #10 trig=4
28	PASS0_CH_RANGEVIO_TR_OUT[36]	TCPWM0_16_ONE_CNT_TR_IN[20]	SAR1 ch#4, range violation to TCPWM0 Group #0 Counter #20 trig=4
29	PASS0_CH_RANGEVIO_TR_OUT[37]	TCPWM0_16_ONE_CNT_TR_IN[21]	SAR1 ch#5, range violation to TCPWM0 Group #0 Counter #21 trig=4
30	PASS0_CH_RANGEVIO_TR_OUT[38]	TCPWM0_16_ONE_CNT_TR_IN[22]	SAR1 ch#6, range violation to TCPWM0 Group #0 Counter #22 trig=4
31	PASS0_CH_RANGEVIO_TR_OUT[39]	TCPWM0_16_ONE_CNT_TR_IN[23]	SAR1 ch#7, range violation to TCPWM0 Group #0 Counter #23 trig=4
32	PASS0_CH_RANGEVIO_TR_OUT[40]	TCPWM0_16_ONE_CNT_TR_IN[24]	SAR1 ch#8, range violation to TCPWM0 Group #0 Counter #24 trig=4
33	PASS0_CH_RANGEVIO_TR_OUT[41]	TCPWM0_16_ONE_CNT_TR_IN[25]	SAR1 ch#9, range violation to TCPWM0 Group #0 Counter #25 trig=4
34	PASS0_CH_RANGEVIO_TR_OUT[42]	TCPWM0_16_ONE_CNT_TR_IN[26]	SAR1 ch#10, range violation to TCPWM0 Group #0 Counter #26 trig=4
35	PASS0_CH_RANGEVIO_TR_OUT[43]	TCPWM0_16_ONE_CNT_TR_IN[27]	SAR1 ch#11, range violation to TCPWM0 Group #0 Counter #27 trig=4
36	PASS0_CH_RANGEVIO_TR_OUT[44]	TCPWM0_16_ONE_CNT_TR_IN[28]	SAR1 ch#12, range violation to TCPWM0 Group #0 Counter #28 trig=4
37	PASS0_CH_RANGEVIO_TR_OUT[45]	TCPWM0_16_ONE_CNT_TR_IN[29]	SAR1 ch#13, range violation to TCPWM0 Group #0 Counter #29 trig=4
38	PASS0_CH_RANGEVIO_TR_OUT[46]	TCPWM0_16_ONE_CNT_TR_IN[30]	SAR1 ch#14, range violation to TCPWM0 Group #0 Counter #30 trig=4
39	PASS0_CH_RANGEVIO_TR_OUT[47]	TCPWM0_16_ONE_CNT_TR_IN[31]	SAR1 ch#15, range violation to TCPWM0 Group #0 Counter #31 trig=4
40	PASS0_CH_RANGEVIO_TR_OUT[48]	TCPWM0_16_ONE_CNT_TR_IN[32]	SAR1 ch#16, range violation to TCPWM0 Group #0 Counter #32 trig=4
41	PASS0_CH_RANGEVIO_TR_OUT[49]	TCPWM0_16_ONE_CNT_TR_IN[33]	SAR1 ch#17, range violation to TCPWM0 Group #0 Counter #33 trig=4
42	PASS0_CH_RANGEVIO_TR_OUT[50]	TCPWM0_16_ONE_CNT_TR_IN[34]	SAR1 ch#18, range violation to TCPWM0 Group #0 Counter #34 trig=4
43	PASS0_CH_RANGEVIO_TR_OUT[51]	TCPWM0_16_ONE_CNT_TR_IN[35]	SAR1 ch#19, range violation to TCPWM0 Group #0 Counter #35 trig=4
44	PASS0_CH_RANGEVIO_TR_OUT[52]	TCPWM0_16_ONE_CNT_TR_IN[36]	SAR1 ch#20, range violation to TCPWM0 Group #0 Counter #36 trig=4
45	PASS0_CH_RANGEVIO_TR_OUT[53]	TCPWM0_16_ONE_CNT_TR_IN[37]	SAR1 ch#21, range violation to TCPWM0 Group #0 Counter #37 trig=4
46	PASS0_CH_RANGEVIO_TR_OUT[54]	TCPWM0_16_ONE_CNT_TR_IN[38]	SAR1 ch#22, range violation to TCPWM0 Group #0 Counter #38 trig=4
47	PASS0_CH_RANGEVIO_TR_OUT[55]	TCPWM0_16_ONE_CNT_TR_IN[39]	SAR1 ch#23, range violation to TCPWM0 Group #0 Counter #39 trig=4
48	PASS0_CH_RANGEVIO_TR_OUT[56]	TCPWM0_16_ONE_CNT_TR_IN[40]	SAR1 ch#24, range violation to TCPWM0 Group #0 Counter #40 trig=4
49	PASS0_CH_RANGEVIO_TR_OUT[57]	TCPWM0_16_ONE_CNT_TR_IN[41]	SAR1 ch#25, range violation to TCPWM0 Group #0 Counter #41 trig=4
50	PASS0_CH_RANGEVIO_TR_OUT[58]	TCPWM0_16_ONE_CNT_TR_IN[42]	SAR1 ch#26, range violation to TCPWM0 Group #0 Counter #42 trig=4
51	PASS0_CH_RANGEVIO_TR_OUT[59]	TCPWM0_16_ONE_CNT_TR_IN[43]	SAR1 ch#27, range violation to TCPWM0 Group #0 Counter #43 trig=4
52	PASS0_CH_RANGEVIO_TR_OUT[60]	TCPWM0_16_ONE_CNT_TR_IN[44]	SAR1 ch#28, range violation to TCPWM0 Group #0 Counter #44 trig=4
53	PASS0_CH_RANGEVIO_TR_OUT[61]	TCPWM0_16_ONE_CNT_TR_IN[45]	SAR1 ch#29, range violation to TCPWM0 Group #0 Counter #45 trig=4
54	PASS0_CH_RANGEVIO_TR_OUT[62]	TCPWM0_16_ONE_CNT_TR_IN[46]	SAR1 ch#30, range violation to TCPWM0 Group #0 Counter #46 trig=4
55	PASS0_CH_RANGEVIO_TR_OUT[63]	TCPWM0_16_ONE_CNT_TR_IN[47]	SAR1 ch#31, range violation to TCPWM0 Group #0 Counter #47 trig=4
56	PASS0_CH_RANGEVIO_TR_OUT[64]	TCPWM0_16M_ONE_CNT_TR_IN[2]	SAR2 ch#0, range violation to TCPWM0 Group #1 Counter #02 trig=4
57	PASS0_CH_RANGEVIO_TR_OUT[65]	TCPWM0_16M_ONE_CNT_TR_IN[5]	SAR2 ch#1, range violation to TCPWM0 Group #1 Counter #05 trig=4
58	PASS0_CH_RANGEVIO_TR_OUT[66]	TCPWM0_16M_ONE_CNT_TR_IN[8]	SAR2 ch#2, range violation to TCPWM0 Group #1 Counter #08 trig=4
59	PASS0_CH_RANGEVIO_TR_OUT[67]	TCPWM0_16M_ONE_CNT_TR_IN[11]	SAR2 ch#3, range violation to TCPWM0 Group #1 Counter #11 trig=4
60	PASS0_CH_RANGEVIO_TR_OUT[68]	TCPWM0_16_ONE_CNT_TR_IN[48]	SAR2 ch#4, range violation to TCPWM0 Group #0 Counter #48 trig=4
61	PASS0_CH_RANGEVIO_TR_OUT[69]	TCPWM0_16_ONE_CNT_TR_IN[49]	SAR2 ch#5, range violation to TCPWM0 Group #0 Counter #49 trig=4
62	PASS0_CH_RANGEVIO_TR_OUT[70]	TCPWM0_16_ONE_CNT_TR_IN[50]	SAR2 ch#6, range violation to TCPWM0 Group #0 Counter #50 trig=4
63	PASS0_CH_RANGEVIO_TR_OUT[71]	TCPWM0_16_ONE_CNT_TR_IN[51]	SAR2 ch#7, range violation to TCPWM0 Group #0 Counter #51 trig=4
MUX Group 4: CAN0 to P-DMA0 Triggers
0	CAN0_DBG_TR_OUT[0]	PDMA0_TR_IN[16]	CAN0, Channel #0 P-DMA0 trigger
1	CAN0_FIFO0_TR_OUT[0]	PDMA0_TR_IN[17]	CAN0, Channel #0 FIFO0 trigger
2	CAN0_FIFO1_TR_OUT[0]	PDMA0_TR_IN[18]	CAN0, Channel #0 FIFO1 trigger
3	CAN0_DBG_TR_OUT[1]	PDMA0_TR_IN[19]	CAN0, Channel #1 P-DMA0 trigger
4	CAN0_FIFO0_TR_OUT[1]	PDMA0_TR_IN[20]	CAN0, Channel #1 FIFO0 trigger
5	CAN0_FIFO1_TR_OUT[1]	PDMA0_TR_IN[21]	CAN0, Channel #1 FIFO1 trigger
6	CAN0_DBG_TR_OUT[2]	PDMA0_TR_IN[22]	CAN0, Channel #2 P-DMA0 trigger
7	CAN0_FIFO0_TR_OUT[2]	PDMA0_TR_IN[23]	CAN0, Channel #2 FIFO0 trigger
8	CAN0_FIFO1_TR_OUT[2]	PDMA0_TR_IN[24]	CAN0, Channel #2 FIFO1 trigger
MUX Group 5: CAN1 to P-DMA1 triggers
0	CAN1_DBG_TR_OUT[0]	PDMA1_TR_IN[24]	CAN1, Channel #0 P-DMA01 trigger
1	CAN1_FIFO0_TR_OUT[0]	PDMA1_TR_IN[25]	CAN1, Channel #0 FIFO0 trigger
2	CAN1_FIFO1_TR_OUT[0]	PDMA1_TR_IN[26]	CAN1, Channel #0 FIFO1 trigger
3	CAN1_DBG_TR_OUT[1]	PDMA1_TR_IN[27]	CAN1, Channel #1 P-DMA1 trigger
4	CAN1_FIFO0_TR_OUT[1]	PDMA1_TR_IN[28]	CAN1, Channel #1 FIFO0 trigger
5	CAN1_FIFO1_TR_OUT[1]	PDMA1_TR_IN[29]	CAN1, Channel #1 FIFO1 trigger
6	CAN1_DBG_TR_OUT[2]	PDMA1_TR_IN[30]	CAN1, Channel #2 P-DMA1 trigger
7	CAN1_FIFO0_TR_OUT[2]	PDMA1_TR_IN[31]	CAN1, Channel #2 FIFO0 trigger
8	CAN1_FIFO1_TR_OUT[2]	PDMA1_TR_IN[32]	CAN1, Channel #2 FIFO1 trigger
MUX Group 6: Acknowledge triggers from P-DMA0 to CAN0
0	PDMA0_TR_OUT[16]	CAN0_DBG_TR_ACK[0]	CAN0, Channel #0 P-DMA0 acknowledge
1	PDMA0_TR_OUT[19]	CAN0_DBG_TR_ACK[1]	CAN0, Channel #1 P-DMA0 acknowledge
2	PDMA0_TR_OUT[22]	CAN0_DBG_TR_ACK[2]	CAN0, Channel #2 P-DMA0 acknowledge
MUX Group 7: Acknowledge triggers from P-DMA1 to CAN1
0	PDMA1_TR_OUT[24]	CAN1_DBG_TR_ACK[0]	CAN1, Channel #0 P-DMA1 acknowledge
1	PDMA1_TR_OUT[27]	CAN1_DBG_TR_ACK[1]	CAN1, Channel #1 P-DMA1 acknowledge
2	PDMA1_TR_OUT[30]	CAN1_DBG_TR_ACK[2]	CAN1, Channel #2 P-DMA1 acknowledge
MUX Group 8: SCBx to P-DMA1 Triggers
0	SCB0_TX_TR_OUT	PDMA1_TR_IN[8]	SCB0 TX to P-DMA1 Trigger
1	SCB0_RX_TR_OUT	PDMA1_TR_IN[9]	SCB0 RX to P-DMA1 Trigger
2	SCB1_TX_TR_OUT	PDMA1_TR_IN[10]	SCB1 TX to P-DMA1 Trigger
3	SCB1_RX_TR_OUT	PDMA1_TR_IN[11]	SCB1 RX to P-DMA1 Trigger
4	SCB2_TX_TR_OUT	PDMA1_TR_IN[12]	SCB2 TX to P-DMA1 Trigger
5	SCB2_RX_TR_OUT	PDMA1_TR_IN[13]	SCB2 RX to P-DMA1 Trigger
6	SCB3_TX_TR_OUT	PDMA1_TR_IN[14]	SCB3 TX to P-DMA1 Trigger
7	SCB3_RX_TR_OUT	PDMA1_TR_IN[15]	SCB3 RX to P-DMA1 Trigger
8	SCB4_TX_TR_OUT	PDMA1_TR_IN[16]	SCB4 TX to P-DMA1 Trigger
9	SCB4_RX_TR_OUT	PDMA1_TR_IN[17]	SCB4 RX to P-DMA1 Trigger
10	SCB5_TX_TR_OUT	PDMA1_TR_IN[18]	SCB5 TX to P-DMA1 Trigger
11	SCB5_RX_TR_OUT	PDMA1_TR_IN[19]	SCB5 RX to P-DMA1 Trigger
12	SCB6_TX_TR_OUT	PDMA1_TR_IN[20]	SCB6 TX to P-DMA1 Trigger
13	SCB6_RX_TR_OUT	PDMA1_TR_IN[21]	SCB6 RX to P-DMA1 Trigger
14	SCB7_TX_TR_OUT	PDMA1_TR_IN[22]	SCB7 TX to P-DMA1 Trigger
15	SCB7_RX_TR_OUT	PDMA1_TR_IN[23]	SCB7 RX to P-DMA1 Trigger

Peripheral clocks

Table 23.
Peripheral clock assignments
Output	Destination	Description
0	PCLK_CPUSS_CLOCK_TRACE_IN	Trace clock
1	PCLK_SMARTIO12_CLOCK	SMART I/O #12
2	PCLK_SMARTIO13_CLOCK	SMART I/O #13
3	PCLK_SMARTIO14_CLOCK	SMART I/O #14
4	PCLK_SMARTIO15_CLOCK	SMART I/O #15
5	PCLK_SMARTIO16_CLOCK	SMART I/O #16
6	PCLK_CANFD0_CLOCK_CAN0	CAN0, Channel #0
7	PCLK_CANFD0_CLOCK_CAN1	CAN0, Channel #1
8	PCLK_CANFD0_CLOCK_CAN2	CAN0, Channel #2
9	PCLK_CANFD1_CLOCK_CAN0	CAN1, Channel #0
10	PCLK_CANFD1_CLOCK_CAN1	CAN1, Channel #1
11	PCLK_CANFD1_CLOCK_CAN2	CAN1, Channel #2
12	PCLK_LIN0_CLOCK_CH_EN0	LIN0, Channel #0
13	PCLK_LIN0_CLOCK_CH_EN1	LIN0, Channel #1
14	PCLK_LIN0_CLOCK_CH_EN2	LIN0, Channel #2
15	PCLK_LIN0_CLOCK_CH_EN3	LIN0, Channel #3
16	PCLK_LIN0_CLOCK_CH_EN4	LIN0, Channel #4
17	PCLK_LIN0_CLOCK_CH_EN5	LIN0, Channel #5
18	PCLK_LIN0_CLOCK_CH_EN6	LIN0, Channel #6
19	PCLK_LIN0_CLOCK_CH_EN7	LIN0, Channel #7
20	PCLK_SCB0_CLOCK	SCB0
21	PCLK_SCB1_CLOCK	SCB1
22	PCLK_SCB2_CLOCK	SCB2
23	PCLK_SCB3_CLOCK	SCB3
24	PCLK_SCB4_CLOCK	SCB4
25	PCLK_SCB5_CLOCK	SCB5
26	PCLK_SCB6_CLOCK	SCB6
27	PCLK_SCB7_CLOCK	SCB7
28	PCLK_PASS0_CLOCK_SAR0	SAR0
29	PCLK_PASS0_CLOCK_SAR1	SAR1
30	PCLK_PASS0_CLOCK_SAR2	SAR2
31	PCLK_TCPWM0_CLOCKS0	TCPWM0 Group #0, Counter #0
32	PCLK_TCPWM0_CLOCKS1	TCPWM0 Group #0, Counter #1
33	PCLK_TCPWM0_CLOCKS2	TCPWM0 Group #0, Counter #2
34	PCLK_TCPWM0_CLOCKS3	TCPWM0 Group #0, Counter #3
35	PCLK_TCPWM0_CLOCKS4	TCPWM0 Group #0, Counter #4
36	PCLK_TCPWM0_CLOCKS5	TCPWM0 Group #0, Counter #5
37	PCLK_TCPWM0_CLOCKS6	TCPWM0 Group #0, Counter #6
38	PCLK_TCPWM0_CLOCKS7	TCPWM0 Group #0, Counter #7
39	PCLK_TCPWM0_CLOCKS8	TCPWM0 Group #0, Counter #8
40	PCLK_TCPWM0_CLOCKS9	TCPWM0 Group #0, Counter #9
41	PCLK_TCPWM0_CLOCKS10	TCPWM0 Group #0, Counter #10
42	PCLK_TCPWM0_CLOCKS11	TCPWM0 Group #0, Counter #11
43	PCLK_TCPWM0_CLOCKS12	TCPWM0 Group #0, Counter #12
44	PCLK_TCPWM0_CLOCKS13	TCPWM0 Group #0, Counter #13
45	PCLK_TCPWM0_CLOCKS14	TCPWM0 Group #0, Counter #14
46	PCLK_TCPWM0_CLOCKS15	TCPWM0 Group #0, Counter #15
47	PCLK_TCPWM0_CLOCKS16	TCPWM0 Group #0, Counter #16
48	PCLK_TCPWM0_CLOCKS17	TCPWM0 Group #0, Counter #17
49	PCLK_TCPWM0_CLOCKS18	TCPWM0 Group #0, Counter #18
50	PCLK_TCPWM0_CLOCKS19	TCPWM0 Group #0, Counter #19
51	PCLK_TCPWM0_CLOCKS20	TCPWM0 Group #0, Counter #20
52	PCLK_TCPWM0_CLOCKS21	TCPWM0 Group #0, Counter #21
53	PCLK_TCPWM0_CLOCKS22	TCPWM0 Group #0, Counter #22
54	PCLK_TCPWM0_CLOCKS23	TCPWM0 Group #0, Counter #23
55	PCLK_TCPWM0_CLOCKS24	TCPWM0 Group #0, Counter #24
56	PCLK_TCPWM0_CLOCKS25	TCPWM0 Group #0, Counter #25
57	PCLK_TCPWM0_CLOCKS26	TCPWM0 Group #0, Counter #26
58	PCLK_TCPWM0_CLOCKS27	TCPWM0 Group #0, Counter #27
59	PCLK_TCPWM0_CLOCKS28	TCPWM0 Group #0, Counter #28
60	PCLK_TCPWM0_CLOCKS29	TCPWM0 Group #0, Counter #29
61	PCLK_TCPWM0_CLOCKS30	TCPWM0 Group #0, Counter #30
62	PCLK_TCPWM0_CLOCKS31	TCPWM0 Group #0, Counter #31
63	PCLK_TCPWM0_CLOCKS32	TCPWM0 Group #0, Counter #32
64	PCLK_TCPWM0_CLOCKS33	TCPWM0 Group #0, Counter #33
65	PCLK_TCPWM0_CLOCKS34	TCPWM0 Group #0, Counter #34
66	PCLK_TCPWM0_CLOCKS35	TCPWM0 Group #0, Counter #35
67	PCLK_TCPWM0_CLOCKS36	TCPWM0 Group #0, Counter #36
68	PCLK_TCPWM0_CLOCKS37	TCPWM0 Group #0, Counter #37
69	PCLK_TCPWM0_CLOCKS38	TCPWM0 Group #0, Counter #38
70	PCLK_TCPWM0_CLOCKS39	TCPWM0 Group #0, Counter #39
71	PCLK_TCPWM0_CLOCKS40	TCPWM0 Group #0, Counter #40
72	PCLK_TCPWM0_CLOCKS41	TCPWM0 Group #0, Counter #41
73	PCLK_TCPWM0_CLOCKS42	TCPWM0 Group #0, Counter #42
74	PCLK_TCPWM0_CLOCKS43	TCPWM0 Group #0, Counter #43
75	PCLK_TCPWM0_CLOCKS44	TCPWM0 Group #0, Counter #44
76	PCLK_TCPWM0_CLOCKS45	TCPWM0 Group #0, Counter #45
77	PCLK_TCPWM0_CLOCKS46	TCPWM0 Group #0, Counter #46
78	PCLK_TCPWM0_CLOCKS47	TCPWM0 Group #0, Counter #47
79	PCLK_TCPWM0_CLOCKS48	TCPWM0 Group #0, Counter #48
80	PCLK_TCPWM0_CLOCKS49	TCPWM0 Group #0, Counter #49
81	PCLK_TCPWM0_CLOCKS50	TCPWM0 Group #0, Counter #50
82	PCLK_TCPWM0_CLOCKS51	TCPWM0 Group #0, Counter #51
83	PCLK_TCPWM0_CLOCKS52	TCPWM0 Group #0, Counter #52
84	PCLK_TCPWM0_CLOCKS53	TCPWM0 Group #0, Counter #53
85	PCLK_TCPWM0_CLOCKS54	TCPWM0 Group #0, Counter #54
86	PCLK_TCPWM0_CLOCKS55	TCPWM0 Group #0, Counter #55
87	PCLK_TCPWM0_CLOCKS56	TCPWM0 Group #0, Counter #56
88	PCLK_TCPWM0_CLOCKS57	TCPWM0 Group #0, Counter #57
89	PCLK_TCPWM0_CLOCKS58	TCPWM0 Group #0, Counter #58
90	PCLK_TCPWM0_CLOCKS59	TCPWM0 Group #0, Counter #59
91	PCLK_TCPWM0_CLOCKS60	TCPWM0 Group #0, Counter #60
92	PCLK_TCPWM0_CLOCKS61	TCPWM0 Group #0, Counter #61
93	PCLK_TCPWM0_CLOCKS62	TCPWM0 Group #0, Counter #62
94	PCLK_TCPWM0_CLOCKS256	TCPWM0 Group #1, Counter #0
95	PCLK_TCPWM0_CLOCKS257	TCPWM0 Group #1, Counter #1
96	PCLK_TCPWM0_CLOCKS258	TCPWM0 Group #1, Counter #2
97	PCLK_TCPWM0_CLOCKS259	TCPWM0 Group #1, Counter #3
98	PCLK_TCPWM0_CLOCKS260	TCPWM0 Group #1, Counter #4
99	PCLK_TCPWM0_CLOCKS261	TCPWM0 Group #1, Counter #5
100	PCLK_TCPWM0_CLOCKS262	TCPWM0 Group #1, Counter #6
101	PCLK_TCPWM0_CLOCKS263	TCPWM0 Group #1, Counter #7
102	PCLK_TCPWM0_CLOCKS264	TCPWM0 Group #1, Counter #8
103	PCLK_TCPWM0_CLOCKS265	TCPWM0 Group #1, Counter #9
104	PCLK_TCPWM0_CLOCKS266	TCPWM0 Group #1, Counter #10
105	PCLK_TCPWM0_CLOCKS267	TCPWM0 Group #1, Counter #11
106	PCLK_TCPWM0_CLOCKS512	TCPWM0 Group #2, Counter #0
107	PCLK_TCPWM0_CLOCKS513	TCPWM0 Group #2, Counter #1
108	PCLK_TCPWM0_CLOCKS514	TCPWM0 Group #2, Counter #2
109	PCLK_TCPWM0_CLOCKS515	TCPWM0 Group #2, Counter #3

Faults

Table 24.
Fault Assignments
Fault	Source	Description
0	CPUSS_MPU_VIO_0	CM0+ SMPU violation DATA0[31:0]: Violating address. DATA1[0]: User read. DATA1[1]: User write. DATA1[2]: User execute. DATA1[3]: Privileged read. DATA1[4]: Privileged write. DATA1[5]: Privileged execute. DATA1[6]: Non-secure. DATA1[11:8]: Master identifier. DATA1[15:12]: Protection context identifier. DATA1[31]: '0' MPU violation; '1': SMPU violation.
1	CPUSS_MPU_VIO_1	Crypto SMPU violation. See CPUSS_MPU_VIO_0 description.
2	CPUSS_MPU_VIO_2	P-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
3	CPUSS_MPU_VIO_3	P-DMA1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
4	CPUSS_MPU_VIO_4	M-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
15	CPUSS_MPU_VIO_15	Test Controller MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
16	CPUSS_MPU_VIO_16	CM4 system bus AHB-Lite interface MPU violation. See CPUSS_MPU_VIO_0 description.
17	CPUSS_MPU_VIO_17	CM4 code bus AHB-Lite interface MPU violation for non flash controller accesses. See CPUSS_MPU_VIO_0 description.
18	CPUSS_MPU_VIO_18	CM4 code bus AHB-Lite interface MPU violation for flash controller accesses. See CPUSS_MPU_VIO_0 description.
26	PERI_PERI_C_ECC	Peripheral protection SRAM correctable ECC violation DATA0[10:0]: Violating address. DATA1[7:0]: Syndrome of SRAM word.
27	PERI_PERI_NC_ECC	Peripheral protection SRAM non-correctable ECC violation
28	PERI_MS_VIO_0	CM0+ Peripheral Master Interface PPU violation DATA0[31:0]: Violating address. DATA1[0]: User read. DATA1[1]: User write. DATA1[2]: User execute. DATA1[3]: Privileged read. DATA1[4]: Privileged write. DATA1[5]: Privileged execute. DATA1[6]: Non-secure. DATA1[11:8]: Master identifier. DATA1[15:12]: Protection context identifier. DATA1[31:28]: “0”: master interface, PPU violation, “1': timeout detected, “2”: bus error, other: undefined.
29	PERI_MS_VIO_1	CM4 Peripheral Master Interface PPU violation. See PERI_MS_VIO_0 description.
30	PERI_MS_VIO_2	P-DMA0 Peripheral Master Interface PPU violation. See PERI_MS_VIO_0 description.
31	PERI_MS_VIO_3	P-DMA1 Peripheral Master Interface PPU violation. See PERI_MS_VIO_0 description.
32	PERI_GROUP_VIO_0	Peripheral Group #0 violation. DATA0[31:0]: Violating address. DATA1[0]: User read. DATA1[1]: User write. DATA1[2]: User execute. DATA1[3]: Privileged read. DATA1[4]: Privileged write. DATA1[5]: Privileged execute. DATA1[6]: Non-secure. DATA1[11:8]: Master identifier. DATA1[15:12]: Protection context identifier. DATA1[31:28]: “0”: decoder or peripheral bus error, other: undefined.
33	PERI_GROUP_VIO_1	Peripheral Group #1 violation. See PERI_GROUP_VIO_0 description.
34	PERI_GROUP_VIO_2	Peripheral Group #2 violation. See PERI_GROUP_VIO_0 description.
35	PERI_GROUP_VIO_3	Peripheral Group #3 violation. See PERI_GROUP_VIO_0 description.
37	PERI_GROUP_VIO_5	Peripheral Group #5 violation. See PERI_GROUP_VIO_0 description.
38	PERI_GROUP_VIO_6	Peripheral Group #6 violation. See PERI_GROUP_VIO_0 description.
41	PERI_GROUP_VIO_9	Peripheral Group #9 violation. See PERI_GROUP_VIO_0 description.
48	CPUSS_FLASHC_MAIN_BUS_ERROR	Flash controller main flash bus error FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system address. FAULT_DATA1[11:8]: Master identifier.
49	CPUSS_FLASHC_MAIN_C_ECC	Flash controller main flash correctable ECC violation DATA[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system address. DATA1[7:0]: Syndrome of 64-bit word (at address offset 0x00). DATA1[15:8]: Syndrome of 64-bit word (at address offset 0x08). DATA1[23:16]: Syndrome of 64-bit word (at address offset 0x10). DATA1[31:24]: Syndrome of 64-bit word (at address offset 0x18).
50	CPUSS_FLASHC_MAIN_NC_ECC	Flash controller main flash non-correctable ECC violation. See CPUSS_FLASHC_MAIN_C_ECC description.
51	CPUSS_FLASHC_WORK_BUS_ERROR	Flash controller work-flash bus error. See CPUSS_FLASHC_MAIN_BUS_ERR description.
52	CPUSS_FLASHC_WORK_C_ECC	Flash controller work flash correctable ECC violation. DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system address. DATA1[6:0]: Syndrome of 32-bit word.
53	CPUSS_FLASHC_WORK_NC_ECC	Flash controller work-flash non-correctable ECC violation. See CPUSS_FLASHC_WORK_C_ECC description.
54	CPUSS_FLASHC_CM0_CA_C_ECC	Flash controller CM0+ cache correctable ECC violation. DATA0[26:0]: Violating address. DATA1[6:0]: Syndrome of 32-bit SRAM word (at address offset 0x0). DATA1[14:8]: Syndrome of 32-bit SRAM word (at address offset 0x4). DATA1[22:16]: Syndrome of 32-bit SRAM word (at address offset 0x8). DATA1[30:24]: Syndrome of 32-bit SRAM word (at address offset 0xc).
55	CPUSS_FLASHC_CM0_CA_NC_ECC	Flash controller CM0+ cache non-correctable ECC violation. See CPUSS_FLASHC_CM0_CA_C_ECC description.
56	CPUSS_FLASHC_CM4_CA_C_ECC	Flash controller CM4 cache correctable ECC violation. See CPUSS_FLASHC_CM0_CA_C_ECC description.
57	CPUSS_FLASHC_CM4_CA_NC_ECC	Flash controller CM4 cache non-correctable ECC violation. See CPUSS_FLASHC_CM0_CA_C_ECC description.
58	CPUSS_RAMC0_C_ECC	System memory controller 0 correctable ECC violation: DATA0[31:0]: Violating address. DATA1[6:0]: Syndrome of 32-bit SRAM code word.
59	CPUSS_RAMC0_NC_ECC	System memory controller 0 non-correctable ECC violation. See CPUSS_RAMC0_C_ECC description.
60	CPUSS_RAMC1_C_ECC	System memory controller 1 correctable ECC violation. See CPUSS_RAMC0_C_ECC description.
61	CPUSS_RAMC1_NC_ECC	System memory controller 1 non-correctable ECC violation. See CPUSS_RAMC0_C_ECC description.
64	CPUSS_CRYPTO_C_ECC	Crypto memory correctable ECC violation. DATA0[31:0]: Violating address. DATA1[6:0]: Syndrome of Least Significant 32-bit SRAM. DATA1[14:8]: Syndrome of Most Significant 32-bit SRAM.
65	CPUSS_CRYPTO_NC_ECC	Crypto memory non-correctable ECC violation. See CPUSS_CRYPTO_C_ECC description.
70	CPUSS_DW0_C_ECC	P-DMA0 memory correctable ECC violation: DATA0[11:0]: Violating DW SRAM address (word address, assuming byte addressable). DATA1[6:0]: Syndrome of 32-bit SRAM code word.
71	CPUSS_DW0_NC_ECC	P-DMA0 memory non-correctable ECC violation. See CPUSS_DW0_C_ECC description.
72	CPUSS_DW1_C_ECC	P-DMA1 memory correctable ECC violation. See CPUSS_DW0_C_ECC description.
73	CPUSS_DW1_NC_ECC	P-DMA1 memory non-correctable ECC violation. See CPUSS_DW0_C_ECC description.
74	CPUSS_FM_SRAM_C_ECC	Flash code storage SRAM memory correctable ECC violation: DATA0[15:0]: Address location in the eCT Flash SRAM. DATA1[6:0]: Syndrome of 32-bit SRAM word.
75	CPUSS_FM_SRAM_NC_ECC	Flash code storage SRAM memory non-correctable ECC violation: See CPUSS_FM_SRAMC_C_ECC description.
80	CANFD_0_CAN_C_ECC	CAN0 message buffer correctable ECC violation: DATA0[15:0]: Violating address. DATA0[22:16]: ECC violating data[38:32] from MRAM. DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F DATA1[31:0]: ECC violating data[31:0] from MRAM.
81	CANFD_0_CAN_NC_ECC	CAN0 message buffer non-correctable ECC violation: DATA0[15:0]: Violating address. DATA0[22:16]: ECC violating data[38:32] from MRAM (not for Address Error). DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F DATA0[30]: Write access, only possible for Address Error DATA0[31]: Address Error: a CAN channel did an MRAM access above MRAM_SIZE DATA1[31:0]: ECC violating data[31:0] from MRAM (not for Address Error).
82	CANFD_1_CAN_C_ECC	CAN1 message buffer correctable ECC violation. See CANFD_0_CAN_C_ECC description.
83	CANFD_1_CAN_NC_ECC	CAN1 message buffer non-correctable ECC violation. See CANFD_0_CAN_NC_ECC description.
90	SRSS_FAULT_CSV	Consolidated fault output for clock supervisors. Multiple CSV can detect a violation at the same time. DATA0[15:0]: CLK_HF* root CSV violation flags. DATA0[24]: CLK_REF CSV violation flag (reference clock for CLK_HF CSVs) DATA0[25]: CLK_LF CSV violation flag DATA0[26]: CLK_HVILO CSV violation flag
91	SRSS_FAULT_SSV	Consolidated fault output for supply supervisors. Multiple CSV can detect a violation at the same time. DATA0[0]: BOD on VDDA DATA[1]: OVD on VDDA DATA[16]: LVD/HVD #1 DATA0[17]: LVD/HVD #2
92	SRSS_FAULT_MCWDT0	Fault output for MCWDT0 (all sub-counters) Multiple counters can detect a violation at the same time. DATA0[0]: MCWDT sub counter 0 LOWER_LIMIT DATA0[1]: MCWDT sub counter 0 UPPER_LIMIT DATA0[2]: MCWDT sub counter 1 LOWER_LIMIT DATA0[3]: MCWDT sub counter 1 UPPER_LIMIT
93	SRSS_FAULT_MCWDT1	Fault output for MCWDT1 (all sub-counters). See SRSS_FAULT_MCWDT0 description.

Peripheral Protection Unit Fixed Structure Pairs

Protection pair is a pair PPU structures, a master and a slave structure. The master structure protects the slave structure, and the slave structure protects resources such as peripheral registers, or the peripheral itself.

Table 25.
PPU Fixed Structure Pairs
Pair No.	PPU Fixed Structure Pair	Address	Size	Description
0	PERI_MS_PPU_FX_PERI_MAIN	0x40000000	0x00002000	Peripheral Interconnect main
1	PERI_MS_PPU_FX_PERI_SECURE	0x40002000	0x00000004	Peripheral interconnect secure
2	PERI_MS_PPU_FX_PERI_GR0_GROUP	0x40004010	0x00000004	Peripheral Group #0 main
3	PERI_MS_PPU_FX_PERI_GR1_GROUP	0x40004030	0x00000004	Peripheral Group #1 main
4	PERI_MS_PPU_FX_PERI_GR2_GROUP	0x40004050	0x00000004	Peripheral Group #2 main
5	PERI_MS_PPU_FX_PERI_GR3_GROUP	0x40004060	0x00000020	Peripheral Group #3 main
6	PERI_MS_PPU_FX_PERI_GR5_GROUP	0x400040A0	0x00000020	Peripheral Group #5 main
7	PERI_MS_PPU_FX_PERI_GR6_GROUP	0x400040C0	0x00000020	Peripheral Group #6 main
8	PERI_MS_PPU_FX_PERI_GR9_GROUP	0x40004120	0x00000020	Peripheral Group #9 main
9	PERI_MS_PPU_FX_PERI_TR	0x40008000	0x00008000	Peripheral trigger multiplexer
10	PERI_MS_PPU_FX_CRYPTO_MAIN	0x40100000	0x00000400	Crypto main
11	PERI_MS_PPU_FX_CRYPTO_CRYPTO	0x40101000	0x00000800	Crypto MMIO (Memory Mapped I/O)
12	PERI_MS_PPU_FX_CRYPTO_BOOT	0x40102000	0x00000100	Crypto boot
13	PERI_MS_PPU_FX_CRYPTO_KEY0	0x40102100	0x00000004	Crypto Key #0
14	PERI_MS_PPU_FX_CRYPTO_KEY1	0x40102120	0x00000004	Crypto Key #1
15	PERI_MS_PPU_FX_CRYPTO_BUF	0x40108000	0x00002000	Crypto buffer
16	PERI_MS_PPU_FX_CPUSS_CM4	0x40200000	0x00000400	CM4 CPU core
17	PERI_MS_PPU_FX_CPUSS_CM0	0x40201000	0x00001000	CM0+ CPU core
18	PERI_MS_PPU_FX_CPUSS_BOOT	0x40202000	0x00000200	CPUSS boot
19	PERI_MS_PPU_FX_CPUSS_CM0_INT	0x40208000	0x00000800	CPUSS CM0+ interrupts
20	PERI_MS_PPU_FX_CPUSS_CM4_INT	0x4020A000	0x00000800	CPUSS CM4 interrupts
21	PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN	0x40210000	0x00000100	CPUSS Fault Structure #0 main
22	PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN	0x40210100	0x00000100	CPUSS Fault Structure #1 main
23	PERI_MS_PPU_FX_FAULT_STRUCT2_MAIN	0x40210200	0x00000100	CPUSS Fault Structure #2 main
24	PERI_MS_PPU_FX_FAULT_STRUCT3_MAIN	0x40210300	0x00000100	CPUSS Fault Structure #3 main
25	PERI_MS_PPU_FX_IPC_STRUCT0_IPC	0x40220000	0x00000020	CPUSS IPC Structure #0
26	PERI_MS_PPU_FX_IPC_STRUCT1_IPC	0x40220020	0x00000020	CPUSS IPC Structure #1
27	PERI_MS_PPU_FX_IPC_STRUCT2_IPC	0x40220040	0x00000020	CPUSS IPC Structure #2
28	PERI_MS_PPU_FX_IPC_STRUCT3_IPC	0x40220060	0x00000020	CPUSS IPC Structure #3
29	PERI_MS_PPU_FX_IPC_STRUCT4_IPC	0x40220080	0x00000020	CPUSS IPC Structure #4
30	PERI_MS_PPU_FX_IPC_STRUCT5_IPC	0x402200A0	0x00000020	CPUSS IPC Structure #5
31	PERI_MS_PPU_FX_IPC_STRUCT6_IPC	0x402200C0	0x00000020	CPUSS IPC Structure #6
32	PERI_MS_PPU_FX_IPC_STRUCT7_IPC	0x402200E0	0x00000020	CPUSS IPC Structure #7
33	PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR	0x40221000	0x00000010	CPUSS IPC Interrupt Structure #0
34	PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR	0x40221020	0x00000010	CPUSS IPC Interrupt Structure #1
35	PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR	0x40221040	0x00000010	CPUSS IPC Interrupt Structure #2
36	PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR	0x40221060	0x00000010	CPUSS IPC Interrupt Structure #3
37	PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR	0x40221080	0x00000010	CPUSS IPC Interrupt Structure #4
38	PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR	0x402210A0	0x00000010	CPUSS IPC Interrupt Structure #5
39	PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR	0x402210C0	0x00000010	CPUSS IPC Interrupt Structure #6
40	PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR	0x402210E0	0x00000010	CPUSS IPC Interrupt Structure #7
41	PERI_MS_PPU_FX_PROT_SMPU_MAIN	0x40230000	0x00000040	Peripheral protection SMPU main
42	PERI_MS_PPU_FX_PROT_MPU0_MAIN	0x40234000	0x00000004	Peripheral protection MPU #0 main
43	PERI_MS_PPU_FX_PROT_MPU14_MAIN	0x40237800	0x00000004	Peripheral protection MPU #14 main
44	PERI_MS_PPU_FX_PROT_MPU15_MAIN	0x40237C00	0x00000400	Peripheral protection MPU #15 main
45	PERI_MS_PPU_FX_FLASHC_MAIN	0x40240000	0x00000008	Flash controller main
46	PERI_MS_PPU_FX_FLASHC_CMD	0x40240008	0x00000004	Flash controller command
47	PERI_MS_PPU_FX_FLASHC_DFT	0x40240200	0x00000100	Flash controller tests
48	PERI_MS_PPU_FX_FLASHC_CM0	0x40240400	0x00000080	Flash controller CM0+
49	PERI_MS_PPU_FX_FLASHC_CM4	0x40240480	0x00000080	Flash controller CM4
50	PERI_MS_PPU_FX_FLASHC_CRYPTO	0x40240500	0x00000004	Flash controller Crypto
51	PERI_MS_PPU_FX_FLASHC_DW0	0x40240580	0x00000004	Flash controller P-DMA0
52	PERI_MS_PPU_FX_FLASHC_DW1	0x40240600	0x00000004	Flash controller P-DMA1
53	PERI_MS_PPU_FX_FLASHC_DMAC	0x40240680	0x00000004	Flash controller M-DMA0
54	PERI_MS_PPU_FX_FLASHC_FlashMgmt ³⁴	0x4024F000	0x00000080	Flash management
55	PERI_MS_PPU_FX_FLASHC_MainSafety	0x4024F400	0x00000008	Flash controller code-flash safety
56	PERI_MS_PPU_FX_FLASHC_WorkSafety	0x4024F500	0x00000004	Flash controller work-flash safety
57	PERI_MS_PPU_FX_SRSS_GENERAL	0x40260000	0x00000400	SRSS General
58	PERI_MS_PPU_FX_SRSS_MAIN	0x40261000	0x00001000	SRSS main
59	PERI_MS_PPU_FX_SRSS_SECURE	0x40262000	0x00002000	SRSS secure
60	PERI_MS_PPU_FX_MCWDT0_CONFIG	0x40268000	0x00000080	MCWDT #0 configuration
61	PERI_MS_PPU_FX_MCWDT1_CONFIG	0x40268100	0x00000080	MCWDT #1 configuration
62	PERI_MS_PPU_FX_MCWDT0_MAIN	0x40268080	0x00000040	MCWDT #0 main
63	PERI_MS_PPU_FX_MCWDT1_MAIN	0x40268180	0x00000040	MCWDT #1 main
64	PERI_MS_PPU_FX_WDT_CONFIG	0x4026C000	0x00000020	System WDT configuration
65	PERI_MS_PPU_FX_WDT_MAIN	0x4026C040	0x00000020	System WDT main
66	PERI_MS_PPU_FX_BACKUP_BACKUP	0x40270000	0x00010000	SRSS backup
67	PERI_MS_PPU_FX_DW0_DW	0x40280000	0x00000100	P-DMA0 main
68	PERI_MS_PPU_FX_DW1_DW	0x40290000	0x00000100	P-DMA1 main
69	PERI_MS_PPU_FX_DW0_DW_CRC	0x40280100	0x00000080	P-DMA0 CRC
70	PERI_MS_PPU_FX_DW1_DW_CRC	0x40290100	0x00000080	P-DMA1 CRC
71	PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH	0x40288000	0x00000040	P-DMA0 Channel #0
72	PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH	0x40288040	0x00000040	P-DMA0 Channel #1
73	PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH	0x40288080	0x00000040	P-DMA0 Channel #2
74	PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH	0x402880C0	0x00000040	P-DMA0 Channel #3
75	PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH	0x40288100	0x00000040	P-DMA0 Channel #4
76	PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH	0x40288140	0x00000040	P-DMA0 Channel #5
77	PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH	0x40288180	0x00000040	P-DMA0 Channel #6
78	PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH	0x402881C0	0x00000040	P-DMA0 Channel #7
79	PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH	0x40288200	0x00000040	P-DMA0 Channel #8
80	PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH	0x40288240	0x00000040	P-DMA0 Channel #9
81	PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH	0x40288280	0x00000040	P-DMA0 Channel #10
82	PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH	0x402882C0	0x00000040	P-DMA0 Channel #11
83	PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH	0x40288300	0x00000040	P-DMA0 Channel #12
84	PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH	0x40288340	0x00000040	P-DMA0 Channel #13
85	PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH	0x40288380	0x00000040	P-DMA0 Channel #14
86	PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH	0x402883C0	0x00000040	P-DMA0 Channel #15
87	PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH	0x40288400	0x00000040	P-DMA0 Channel #16
88	PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH	0x40288440	0x00000040	P-DMA0 Channel #17
89	PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH	0x40288480	0x00000040	P-DMA0 Channel #18
90	PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH	0x402884C0	0x00000040	P-DMA0 Channel #19
91	PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH	0x40288500	0x00000040	P-DMA0 Channel #20
92	PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH	0x40288540	0x00000040	P-DMA0 Channel #21
93	PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH	0x40288580	0x00000040	P-DMA0 Channel #22
94	PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH	0x402885C0	0x00000040	P-DMA0 Channel #23
95	PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH	0x40288600	0x00000040	P-DMA0 Channel #24
96	PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH	0x40288640	0x00000040	P-DMA0 Channel #25
97	PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH	0x40288680	0x00000040	P-DMA0 Channel #26
98	PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH	0x402886C0	0x00000040	P-DMA0 Channel #27
99	PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH	0x40288700	0x00000040	P-DMA0 Channel #28
100	PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH	0x40288740	0x00000040	P-DMA0 Channel #29
101	PERI_MS_PPU_FX_DW0_CH_STRUCT30_CH	0x40288780	0x00000040	P-DMA0 Channel #30
102	PERI_MS_PPU_FX_DW0_CH_STRUCT31_CH	0x402887C0	0x00000040	P-DMA0 Channel #31
103	PERI_MS_PPU_FX_DW0_CH_STRUCT32_CH	0x40288800	0x00000040	P-DMA0 Channel #32
104	PERI_MS_PPU_FX_DW0_CH_STRUCT33_CH	0x40288840	0x00000040	P-DMA0 Channel #33
105	PERI_MS_PPU_FX_DW0_CH_STRUCT34_CH	0x40288880	0x00000040	P-DMA0 Channel #34
106	PERI_MS_PPU_FX_DW0_CH_STRUCT35_CH	0x402888C0	0x00000040	P-DMA0 Channel #35
107	PERI_MS_PPU_FX_DW0_CH_STRUCT36_CH	0x40288900	0x00000040	P-DMA0 Channel #36
108	PERI_MS_PPU_FX_DW0_CH_STRUCT37_CH	0x40288940	0x00000040	P-DMA0 Channel #37
109	PERI_MS_PPU_FX_DW0_CH_STRUCT38_CH	0x40288980	0x00000040	P-DMA0 Channel #38
110	PERI_MS_PPU_FX_DW0_CH_STRUCT39_CH	0x402889C0	0x00000040	P-DMA0 Channel #39
111	PERI_MS_PPU_FX_DW0_CH_STRUCT40_CH	0x40288A00	0x00000040	P-DMA0 Channel #40
112	PERI_MS_PPU_FX_DW0_CH_STRUCT41_CH	0x40288A40	0x00000040	P-DMA0 Channel #41
113	PERI_MS_PPU_FX_DW0_CH_STRUCT42_CH	0x40288A80	0x00000040	P-DMA0 Channel #42
114	PERI_MS_PPU_FX_DW0_CH_STRUCT43_CH	0x40288AC0	0x00000040	P-DMA0 Channel #43
115	PERI_MS_PPU_FX_DW0_CH_STRUCT44_CH	0x40288B00	0x00000040	P-DMA0 Channel #44
116	PERI_MS_PPU_FX_DW0_CH_STRUCT45_CH	0x40288B40	0x00000040	P-DMA0 Channel #45
117	PERI_MS_PPU_FX_DW0_CH_STRUCT46_CH	0x40288B80	0x00000040	P-DMA0 Channel #46
118	PERI_MS_PPU_FX_DW0_CH_STRUCT47_CH	0x40288BC0	0x00000040	P-DMA0 Channel #47
119	PERI_MS_PPU_FX_DW0_CH_STRUCT48_CH	0x40288C00	0x00000040	P-DMA0 Channel #48
120	PERI_MS_PPU_FX_DW0_CH_STRUCT49_CH	0x40288C40	0x00000040	P-DMA0 Channel #49
121	PERI_MS_PPU_FX_DW0_CH_STRUCT50_CH	0x40288C80	0x00000040	P-DMA0 Channel #50
122	PERI_MS_PPU_FX_DW0_CH_STRUCT51_CH	0x40288CC0	0x00000040	P-DMA0 Channel #51
123	PERI_MS_PPU_FX_DW0_CH_STRUCT52_CH	0x40288D00	0x00000040	P-DMA0 Channel #52
124	PERI_MS_PPU_FX_DW0_CH_STRUCT53_CH	0x40288D40	0x00000040	P-DMA0 Channel #53
125	PERI_MS_PPU_FX_DW0_CH_STRUCT54_CH	0x40288D80	0x00000040	P-DMA0 Channel #54
126	PERI_MS_PPU_FX_DW0_CH_STRUCT55_CH	0x40288DC0	0x00000040	P-DMA0 Channel #55
127	PERI_MS_PPU_FX_DW0_CH_STRUCT56_CH	0x40288E00	0x00000040	P-DMA0 Channel #56
128	PERI_MS_PPU_FX_DW0_CH_STRUCT57_CH	0x40288E40	0x00000040	P-DMA0 Channel #57
129	PERI_MS_PPU_FX_DW0_CH_STRUCT58_CH	0x40288E80	0x00000040	P-DMA0 Channel #58
130	PERI_MS_PPU_FX_DW0_CH_STRUCT59_CH	0x40288EC0	0x00000040	P-DMA0 Channel #59
131	PERI_MS_PPU_FX_DW0_CH_STRUCT60_CH	0x40288F00	0x00000040	P-DMA0 Channel #60
132	PERI_MS_PPU_FX_DW0_CH_STRUCT61_CH	0x40288F40	0x00000040	P-DMA0 Channel #61
133	PERI_MS_PPU_FX_DW0_CH_STRUCT62_CH	0x40288F80	0x00000040	P-DMA0 Channel #62
134	PERI_MS_PPU_FX_DW0_CH_STRUCT63_CH	0x40288FC0	0x00000040	P-DMA0 Channel #63
135	PERI_MS_PPU_FX_DW0_CH_STRUCT64_CH	0x40289000	0x00000040	P-DMA0 Channel #64
136	PERI_MS_PPU_FX_DW0_CH_STRUCT65_CH	0x40289040	0x00000040	P-DMA0 Channel #65
137	PERI_MS_PPU_FX_DW0_CH_STRUCT66_CH	0x40289080	0x00000040	P-DMA0 Channel #66
138	PERI_MS_PPU_FX_DW0_CH_STRUCT67_CH	0x402890C0	0x00000040	P-DMA0 Channel #67
139	PERI_MS_PPU_FX_DW0_CH_STRUCT68_CH	0x40289100	0x00000040	P-DMA0 Channel #68
140	PERI_MS_PPU_FX_DW0_CH_STRUCT69_CH	0x40289140	0x00000040	P-DMA0 Channel #69
141	PERI_MS_PPU_FX_DW0_CH_STRUCT70_CH	0x40289180	0x00000040	P-DMA0 Channel #70
142	PERI_MS_PPU_FX_DW0_CH_STRUCT71_CH	0x402891C0	0x00000040	P-DMA0 Channel #71
143	PERI_MS_PPU_FX_DW0_CH_STRUCT72_CH	0x40289200	0x00000040	P-DMA0 Channel #72
144	PERI_MS_PPU_FX_DW0_CH_STRUCT73_CH	0x40289240	0x00000040	P-DMA0 Channel #73
145	PERI_MS_PPU_FX_DW0_CH_STRUCT74_CH	0x40289280	0x00000040	P-DMA0 Channel #74
146	PERI_MS_PPU_FX_DW0_CH_STRUCT75_CH	0x402892C0	0x00000040	P-DMA0 Channel #75
147	PERI_MS_PPU_FX_DW0_CH_STRUCT76_CH	0x40289300	0x00000040	P-DMA0 Channel #76
148	PERI_MS_PPU_FX_DW0_CH_STRUCT77_CH	0x40289340	0x00000040	P-DMA0 Channel #77
149	PERI_MS_PPU_FX_DW0_CH_STRUCT78_CH	0x40289380	0x00000040	P-DMA0 Channel #78
150	PERI_MS_PPU_FX_DW0_CH_STRUCT79_CH	0x402893C0	0x00000040	P-DMA0 Channel #79
151	PERI_MS_PPU_FX_DW0_CH_STRUCT80_CH	0x40289400	0x00000040	P-DMA0 Channel #80
152	PERI_MS_PPU_FX_DW0_CH_STRUCT81_CH	0x40289440	0x00000040	P-DMA0 Channel #81
153	PERI_MS_PPU_FX_DW0_CH_STRUCT82_CH	0x40289480	0x00000040	P-DMA0 Channel #82
154	PERI_MS_PPU_FX_DW0_CH_STRUCT83_CH	0x402894C0	0x00000040	P-DMA0 Channel #83
155	PERI_MS_PPU_FX_DW0_CH_STRUCT84_CH	0x40289500	0x00000040	P-DMA0 Channel #84
156	PERI_MS_PPU_FX_DW0_CH_STRUCT85_CH	0x40289540	0x00000040	P-DMA0 Channel #85
157	PERI_MS_PPU_FX_DW0_CH_STRUCT86_CH	0x40289580	0x00000040	P-DMA0 Channel #86
158	PERI_MS_PPU_FX_DW0_CH_STRUCT87_CH	0x402895C0	0x00000040	P-DMA0 Channel #87
159	PERI_MS_PPU_FX_DW0_CH_STRUCT88_CH	0x40289600	0x00000040	P-DMA0 Channel #88
160	PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH	0x40298000	0x00000040	P-DMA1 Channel #0
161	PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH	0x40298040	0x00000040	P-DMA1 Channel #1
162	PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH	0x40298080	0x00000040	P-DMA1 Channel #2
163	PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH	0x402980C0	0x00000040	P-DMA1 Channel #3
164	PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH	0x40298100	0x00000040	P-DMA1 Channel #4
165	PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH	0x40298140	0x00000040	P-DMA1 Channel #5
166	PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH	0x40298180	0x00000040	P-DMA1 Channel #6
167	PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH	0x402981C0	0x00000040	P-DMA1 Channel #7
168	PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH	0x40298200	0x00000040	P-DMA1 Channel #8
169	PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH	0x40298240	0x00000040	P-DMA1 Channel #9
170	PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH	0x40298280	0x00000040	P-DMA1 Channel #10
171	PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH	0x402982C0	0x00000040	P-DMA1 Channel #11
172	PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH	0x40298300	0x00000040	P-DMA1 Channel #12
173	PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH	0x40298340	0x00000040	P-DMA1 Channel #13
174	PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH	0x40298380	0x00000040	P-DMA1 Channel #14
175	PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH	0x402983C0	0x00000040	P-DMA1 Channel #15
176	PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH	0x40298400	0x00000040	P-DMA1 Channel #16
177	PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH	0x40298440	0x00000040	P-DMA1 Channel #17
178	PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH	0x40298480	0x00000040	P-DMA1 Channel #18
179	PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH	0x402984C0	0x00000040	P-DMA1 Channel #19
180	PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH	0x40298500	0x00000040	P-DMA1 Channel #20
181	PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH	0x40298540	0x00000040	P-DMA1 Channel #21
182	PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH	0x40298580	0x00000040	P-DMA1 Channel #22
183	PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH	0x402985C0	0x00000040	P-DMA1 Channel #23
184	PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH	0x40298600	0x00000040	P-DMA1 Channel #24
185	PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH	0x40298640	0x00000040	P-DMA1 Channel #25
186	PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH	0x40298680	0x00000040	P-DMA1 Channel #26
187	PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH	0x402986C0	0x00000040	P-DMA1 Channel #27
188	PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH	0x40298700	0x00000040	P-DMA1 Channel #28
189	PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH	0x40298740	0x00000040	P-DMA1 Channel #29
190	PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH	0x40298780	0x00000040	P-DMA1 Channel #30
191	PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH	0x402987C0	0x00000040	P-DMA1 Channel #31
192	PERI_MS_PPU_FX_DW1_CH_STRUCT32_CH	0x40298800	0x00000040	P-DMA1 Channel #32
193	PERI_MS_PPU_FX_DMAC_TOP	0x402A0000	0x00000010	M-DMA0 main
194	PERI_MS_PPU_FX_DMAC_CH0_CH	0x402A1000	0x00000100	M-DMA0 Channel #0
195	PERI_MS_PPU_FX_DMAC_CH1_CH	0x402A1100	0x00000100	M-DMA0 Channel #1
196	PERI_MS_PPU_FX_DMAC_CH2_CH	0x402A1200	0x00000100	M-DMA0 Channel #2
197	PERI_MS_PPU_FX_DMAC_CH3_CH	0x402A1300	0x00000100	M-DMA0 Channel #3
198	PERI_MS_PPU_FX_EFUSE_CTL	0x402C0000	0x00000200	EFUSE control
199	PERI_MS_PPU_FX_EFUSE_DATA	0x402C0800	0x00000200	EFUSE data
200	PERI_MS_PPU_FX_BIST	0x402F0000	0x00001000	Built-in self test
201	PERI_MS_PPU_FX_HSIOM_PRT0_PRT	0x40300000	0x00000008	HSIOm Port #0
202	PERI_MS_PPU_FX_HSIOM_PRT1_PRT	0x40300010	0x00000008	HSIOm Port #1
203	PERI_MS_PPU_FX_HSIOM_PRT2_PRT	0x40300020	0x00000008	HSIOm Port #2
204	PERI_MS_PPU_FX_HSIOM_PRT3_PRT	0x40300030	0x00000008	HSIOm Port #3
205	PERI_MS_PPU_FX_HSIOM_PRT4_PRT	0x40300040	0x00000008	HSIOm Port #4
206	PERI_MS_PPU_FX_HSIOM_PRT5_PRT	0x40300050	0x00000008	HSIOm Port #5
207	PERI_MS_PPU_FX_HSIOM_PRT6_PRT	0x40300060	0x00000008	HSIOm Port #6
208	PERI_MS_PPU_FX_HSIOM_PRT7_PRT	0x40300070	0x00000008	HSIOm Port #7
209	PERI_MS_PPU_FX_HSIOM_PRT8_PRT	0x40300080	0x00000008	HSIOm Port #8
210	PERI_MS_PPU_FX_HSIOM_PRT9_PRT	0x40300090	0x00000008	HSIOm Port #9
211	PERI_MS_PPU_FX_HSIOM_PRT10_PRT	0x403000A0	0x00000008	HSIOm Port #10
212	PERI_MS_PPU_FX_HSIOM_PRT11_PRT	0x403000B0	0x00000008	HSIOm Port #11
213	PERI_MS_PPU_FX_HSIOM_PRT12_PRT	0x403000C0	0x00000008	HSIOm Port #12
214	PERI_MS_PPU_FX_HSIOM_PRT13_PRT	0x403000D0	0x00000008	HSIOm Port #13
215	PERI_MS_PPU_FX_HSIOM_PRT14_PRT	0x403000E0	0x00000008	HSIOm Port #14
216	PERI_MS_PPU_FX_HSIOM_PRT15_PRT	0x403000F0	0x00000008	HSIOm Port #15
217	PERI_MS_PPU_FX_HSIOM_PRT16_PRT	0x40300100	0x00000008	HSIOm Port #16
218	PERI_MS_PPU_FX_HSIOM_PRT17_PRT	0x40300110	0x00000008	HSIOm Port #17
219	PERI_MS_PPU_FX_HSIOM_PRT18_PRT	0x40300120	0x00000008	HSIOm Port #18
220	PERI_MS_PPU_FX_HSIOM_PRT19_PRT	0x40300130	0x00000008	HSIOm Port #19
221	PERI_MS_PPU_FX_HSIOM_PRT20_PRT	0x40300140	0x00000008	HSIOm Port #20
222	PERI_MS_PPU_FX_HSIOM_PRT21_PRT	0x40300150	0x00000008	HSIOm Port #21
223	PERI_MS_PPU_FX_HSIOM_PRT22_PRT	0x40300160	0x00000008	HSIOm Port #22
224	PERI_MS_PPU_FX_HSIOM_PRT23_PRT	0x40300170	0x00000008	HSIOm Port #23
225	PERI_MS_PPU_FX_HSIOM_AMUX	0x40302000	0x00000010	HSIOm Analog multiplexer
226	PERI_MS_PPU_FX_HSIOM_MON	0x40302200	0x00000010	HSIOm monitor
227	PERI_MS_PPU_FX_HSIOM_ALTJTAG	0x40302240	0x00000004	HSIOm Alternate JTAG
228	PERI_MS_PPU_FX_GPIO_PRT0_PRT	0x40310000	0x00000040	GPIO_ENH Port #0
229	PERI_MS_PPU_FX_GPIO_PRT1_PRT	0x40310080	0x00000040	GPIO_STD Port #1
230	PERI_MS_PPU_FX_GPIO_PRT2_PRT	0x40310100	0x00000040	GPIO_STD Port #2
231	PERI_MS_PPU_FX_GPIO_PRT3_PRT	0x40310180	0x00000040	GPIO_STD Port #3
232	PERI_MS_PPU_FX_GPIO_PRT4_PRT	0x40310200	0x00000040	GPIO_STD Port #4
233	PERI_MS_PPU_FX_GPIO_PRT5_PRT	0x40310280	0x00000040	GPIO_STD Port #5
234	PERI_MS_PPU_FX_GPIO_PRT6_PRT	0x40310300	0x00000040	GPIO_STD Port #6
235	PERI_MS_PPU_FX_GPIO_PRT7_PRT	0x40310380	0x00000040	GPIO_STD Port #7
236	PERI_MS_PPU_FX_GPIO_PRT8_PRT	0x40310400	0x00000040	GPIO_STD Port #8
237	PERI_MS_PPU_FX_GPIO_PRT9_PRT	0x40310480	0x00000040	GPIO_STD Port #9
238	PERI_MS_PPU_FX_GPIO_PRT10_PRT	0x40310500	0x00000040	GPIO_STD Port #10
239	PERI_MS_PPU_FX_GPIO_PRT11_PRT	0x40310580	0x00000040	GPIO_STD Port #11
240	PERI_MS_PPU_FX_GPIO_PRT12_PRT	0x40310600	0x00000040	GPIO_STD Port #12
241	PERI_MS_PPU_FX_GPIO_PRT13_PRT	0x40310680	0x00000040	GPIO_STD Port #13
242	PERI_MS_PPU_FX_GPIO_PRT14_PRT	0x40310700	0x00000040	GPIO_STD Port #14
243	PERI_MS_PPU_FX_GPIO_PRT15_PRT	0x40310780	0x00000040	GPIO_STD Port #15
244	PERI_MS_PPU_FX_GPIO_PRT16_PRT	0x40310800	0x00000040	GPIO_STD Port #16
245	PERI_MS_PPU_FX_GPIO_PRT17_PRT	0x40310880	0x00000040	GPIO_STD Port #17
246	PERI_MS_PPU_FX_GPIO_PRT18_PRT	0x40310900	0x00000040	GPIO_STD Port #18
247	PERI_MS_PPU_FX_GPIO_PRT19_PRT	0x40310980	0x00000040	GPIO_STD Port #19
248	PERI_MS_PPU_FX_GPIO_PRT20_PRT	0x40310A00	0x00000040	GPIO_STD Port #20
249	PERI_MS_PPU_FX_GPIO_PRT21_PRT	0x40310A80	0x00000040	GPIO_STD Port #21
250	PERI_MS_PPU_FX_GPIO_PRT22_PRT	0x40310B00	0x00000040	GPIO_STD Port #22
251	PERI_MS_PPU_FX_GPIO_PRT23_PRT	0x40310B80	0x00000040	GPIO_STD Port #23
252	PERI_MS_PPU_FX_GPIO_PRT0_CFG	0x40310040	0x00000020	GPIO_ENH Port #0 configuration
253	PERI_MS_PPU_FX_GPIO_PRT1_CFG	0x403100C0	0x00000020	GPIO_STD Port #1 configuration
254	PERI_MS_PPU_FX_GPIO_PRT2_CFG	0x40310140	0x00000020	GPIO_STD Port #2 configuration
255	PERI_MS_PPU_FX_GPIO_PRT3_CFG	0x403101C0	0x00000020	GPIO_STD Port #3 configuration
256	PERI_MS_PPU_FX_GPIO_PRT4_CFG	0x40310240	0x00000020	GPIO_STD Port #4 configuration
257	PERI_MS_PPU_FX_GPIO_PRT5_CFG	0x403102C0	0x00000020	GPIO_STD Port #5 configuration
258	PERI_MS_PPU_FX_GPIO_PRT6_CFG	0x40310340	0x00000020	GPIO_STD Port #6 configuration
259	PERI_MS_PPU_FX_GPIO_PRT7_CFG	0x403103C0	0x00000020	GPIO_STD Port #7 configuration
260	PERI_MS_PPU_FX_GPIO_PRT8_CFG	0x40310440	0x00000020	GPIO_STD Port #8 configuration
261	PERI_MS_PPU_FX_GPIO_PRT9_CFG	0x403104C0	0x00000020	GPIO_STD Port #9 configuration
262	PERI_MS_PPU_FX_GPIO_PRT10_CFG	0x40310540	0x00000020	GPIO_STD Port #10 configuration
263	PERI_MS_PPU_FX_GPIO_PRT11_CFG	0x403105C0	0x00000020	GPIO_STD Port #11 configuration
264	PERI_MS_PPU_FX_GPIO_PRT12_CFG	0x40310640	0x00000020	GPIO_STD Port #12 configuration
265	PERI_MS_PPU_FX_GPIO_PRT13_CFG	0x403106C0	0x00000020	GPIO_STD Port #13 configuration
266	PERI_MS_PPU_FX_GPIO_PRT14_CFG	0x40310740	0x00000020	GPIO_STD Port #14 configuration
267	PERI_MS_PPU_FX_GPIO_PRT15_CFG	0x403107C0	0x00000020	GPIO_STD Port #15 configuration
268	PERI_MS_PPU_FX_GPIO_PRT16_CFG	0x40310840	0x00000020	GPIO_STD Port #16 configuration
269	PERI_MS_PPU_FX_GPIO_PRT17_CFG	0x403108C0	0x00000020	GPIO_STD Port #17 configuration
270	PERI_MS_PPU_FX_GPIO_PRT18_CFG	0x40310940	0x00000020	GPIO_STD Port #18 configuration
271	PERI_MS_PPU_FX_GPIO_PRT19_CFG	0x403109C0	0x00000020	GPIO_STD Port #19 configuration
272	PERI_MS_PPU_FX_GPIO_PRT20_CFG	0x40310A40	0x00000020	GPIO_STD Port #20 configuration
273	PERI_MS_PPU_FX_GPIO_PRT21_CFG	0x40310AC0	0x00000020	GPIO_STD Port #21 configuration
274	PERI_MS_PPU_FX_GPIO_PRT22_CFG	0x40310B40	0x00000020	GPIO_STD Port #22 configuration
275	PERI_MS_PPU_FX_GPIO_PRT23_CFG	0x40310BC0	0x00000020	GPIO_STD Port #23 configuration
276	PERI_MS_PPU_FX_GPIO_GPIO	0x40314000	0x00000040	GPIO main
277	PERI_MS_PPU_FX_GPIO_TEST	0x40315000	0x00000008	GPIO test
278	PERI_MS_PPU_FX_SMARTIO_PRT12_PRT	0x40320C00	0x00000100	SMART I/O #12
279	PERI_MS_PPU_FX_SMARTIO_PRT13_PRT	0x40320D00	0x00000100	SMART I/O #13
280	PERI_MS_PPU_FX_SMARTIO_PRT14_PRT	0x40320E00	0x00000100	SMART I/O #14
281	PERI_MS_PPU_FX_SMARTIO_PRT15_PRT	0x40320F00	0x00000100	SMART I/O #15
282	PERI_MS_PPU_FX_SMARTIO_PRT17_PRT	0x40321100	0x00000100	SMART I/O #17
283	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT	0x40380000	0x00000080	TCPWM0 Group #0, Counter #0
284	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT	0x40380080	0x00000080	TCPWM0 Group #0, Counter #1
285	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT	0x40380100	0x00000080	TCPWM0 Group #0, Counter #2
286	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT	0x40380180	0x00000080	TCPWM0 Group #0, Counter #3
287	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT4_CNT	0x40380200	0x00000080	TCPWM0 Group #0, Counter #4
288	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT5_CNT	0x40380280	0x00000080	TCPWM0 Group #0, Counter #5
289	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT6_CNT	0x40380300	0x00000080	TCPWM0 Group #0, Counter #6
290	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT7_CNT	0x40380380	0x00000080	TCPWM0 Group #0, Counter #7
291	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT8_CNT	0x40380400	0x00000080	TCPWM0 Group #0, Counter #8
292	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT9_CNT	0x40380480	0x00000080	TCPWM0 Group #0, Counter #9
293	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT10_CNT	0x40380500	0x00000080	TCPWM0 Group #0, Counter #10
294	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT11_CNT	0x40380580	0x00000080	TCPWM0 Group #0, Counter #11
295	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT12_CNT	0x40380600	0x00000080	TCPWM0 Group #0, Counter #12
296	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT13_CNT	0x40380680	0x00000080	TCPWM0 Group #0, Counter #13
297	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT14_CNT	0x40380700	0x00000080	TCPWM0 Group #0, Counter #14
298	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT15_CNT	0x40380780	0x00000080	TCPWM0 Group #0, Counter #15
299	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT16_CNT	0x40380800	0x00000080	TCPWM0 Group #0, Counter #16
300	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT17_CNT	0x40380880	0x00000080	TCPWM0 Group #0, Counter #17
301	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT18_CNT	0x40380900	0x00000080	TCPWM0 Group #0, Counter #18
302	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT19_CNT	0x40380980	0x00000080	TCPWM0 Group #0, Counter #19
303	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT20_CNT	0x40380A00	0x00000080	TCPWM0 Group #0, Counter #20
304	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT21_CNT	0x40380A80	0x00000080	TCPWM0 Group #0, Counter #21
305	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT22_CNT	0x40380B00	0x00000080	TCPWM0 Group #0, Counter #22
306	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT23_CNT	0x40380B80	0x00000080	TCPWM0 Group #0, Counter #23
307	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT24_CNT	0x40380C00	0x00000080	TCPWM0 Group #0, Counter #24
308	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT25_CNT	0x40380C80	0x00000080	TCPWM0 Group #0, Counter #25
309	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT26_CNT	0x40380D00	0x00000080	TCPWM0 Group #0, Counter #26
310	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT27_CNT	0x40380D80	0x00000080	TCPWM0 Group #0, Counter #27
311	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT28_CNT	0x40380E00	0x00000080	TCPWM0 Group #0, Counter #28
312	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT29_CNT	0x40380E80	0x00000080	TCPWM0 Group #0, Counter #29
313	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT30_CNT	0x40380F00	0x00000080	TCPWM0 Group #0, Counter #30
314	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT31_CNT	0x40380F80	0x00000080	TCPWM0 Group #0, Counter #31
315	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT32_CNT	0x40381000	0x00000080	TCPWM0 Group #0, Counter #32
316	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT33_CNT	0x40381080	0x00000080	TCPWM0 Group #0, Counter #33
317	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT34_CNT	0x40381100	0x00000080	TCPWM0 Group #0, Counter #34
318	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT35_CNT	0x40381180	0x00000080	TCPWM0 Group #0, Counter #35
319	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT36_CNT	0x40381200	0x00000080	TCPWM0 Group #0, Counter #36
320	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT37_CNT	0x40381280	0x00000080	TCPWM0 Group #0, Counter #37
321	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT38_CNT	0x40381300	0x00000080	TCPWM0 Group #0, Counter #38
322	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT39_CNT	0x40381380	0x00000080	TCPWM0 Group #0, Counter #39
323	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT40_CNT	0x40381400	0x00000080	TCPWM0 Group #0, Counter #40
324	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT41_CNT	0x40381480	0x00000080	TCPWM0 Group #0, Counter #41
325	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT42_CNT	0x40381500	0x00000080	TCPWM0 Group #0, Counter #42
326	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT43_CNT	0x40381580	0x00000080	TCPWM0 Group #0, Counter #43
327	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT44_CNT	0x40381600	0x00000080	TCPWM0 Group #0, Counter #44
328	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT45_CNT	0x40381680	0x00000080	TCPWM0 Group #0, Counter #45
329	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT46_CNT	0x40381700	0x00000080	TCPWM0 Group #0, Counter #46
330	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT47_CNT	0x40381780	0x00000080	TCPWM0 Group #0, Counter #47
331	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT48_CNT	0x40381800	0x00000080	TCPWM0 Group #0, Counter #48
332	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT49_CNT	0x40381880	0x00000080	TCPWM0 Group #0, Counter #49
333	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT50_CNT	0x40381900	0x00000080	TCPWM0 Group #0, Counter #50
334	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT51_CNT	0x40381980	0x00000080	TCPWM0 Group #0, Counter #51
335	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT52_CNT	0x40381A00	0x00000080	TCPWM0 Group #0, Counter #52
336	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT53_CNT	0x40381A80	0x00000080	TCPWM0 Group #0, Counter #53
337	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT54_CNT	0x40381B00	0x00000080	TCPWM0 Group #0, Counter #54
338	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT55_CNT	0x40381B80	0x00000080	TCPWM0 Group #0, Counter #55
339	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT56_CNT	0x40381C00	0x00000080	TCPWM0 Group #0, Counter #56
340	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT57_CNT	0x40381C80	0x00000080	TCPWM0 Group #0, Counter #57
341	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT58_CNT	0x40381D00	0x00000080	TCPWM0 Group #0, Counter #58
342	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT59_CNT	0x40381D80	0x00000080	TCPWM0 Group #0, Counter #59
343	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT60_CNT	0x40381E00	0x00000080	TCPWM0 Group #0, Counter #60
344	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT61_CNT	0x40381E80	0x00000080	TCPWM0 Group #0, Counter #61
345	PERI_MS_PPU_FX_TCPWM0_GRP0_CNT62_CNT	0x40381F00	0x00000080	TCPWM0 Group #0, Counter #62
346	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT	0x40388000	0x00000080	TCPWM0 Group #1, Counter #0
347	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT	0x40388080	0x00000080	TCPWM0 Group #1, Counter #1
348	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT	0x40388100	0x00000080	TCPWM0 Group #1, Counter #2
349	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT	0x40388180	0x00000080	TCPWM0 Group #1, Counter #3
350	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT	0x40388200	0x00000080	TCPWM0 Group #1, Counter #4
351	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT	0x40388280	0x00000080	TCPWM0 Group #1, Counter #5
352	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT	0x40388300	0x00000080	TCPWM0 Group #1, Counter #6
353	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT	0x40388380	0x00000080	TCPWM0 Group #1, Counter #7
354	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT8_CNT	0x40388400	0x00000080	TCPWM0 Group #1, Counter #8
355	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT9_CNT	0x40388480	0x00000080	TCPWM0 Group #1, Counter #9
356	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT10_CNT	0x40388500	0x00000080	TCPWM0 Group #1, Counter #10
357	PERI_MS_PPU_FX_TCPWM0_GRP1_CNT11_CNT	0x40388580	0x00000080	TCPWM0 Group #1, Counter #11
358	PERI_MS_PPU_FX_TCPWM0_GRP2_CNT0_CNT	0x40390000	0x00000080	TCPWM0 Group #2, Counter #0
359	PERI_MS_PPU_FX_TCPWM0_GRP2_CNT1_CNT	0x40390080	0x00000080	TCPWM0 Group #2, Counter #1
360	PERI_MS_PPU_FX_TCPWM0_GRP2_CNT2_CNT	0x40390100	0x00000080	TCPWM0 Group #2, Counter #2
361	PERI_MS_PPU_FX_TCPWM0_GRP2_CNT3_CNT	0x40390180	0x00000080	TCPWM0 Group #2, Counter #3
362	PERI_MS_PPU_FX_EVTGEN0	0x403F0000	0x00001000	Event generator #0
363	PERI_MS_PPU_FX_LIN0_MAIN	0x40500000	0x00000008	LIN0, main
364	PERI_MS_PPU_FX_LIN0_CH0_CH	0x40508000	0x00000100	LIN0, Channel #0
365	PERI_MS_PPU_FX_LIN0_CH1_CH	0x40508100	0x00000100	LIN0, Channel #1
366	PERI_MS_PPU_FX_LIN0_CH2_CH	0x40508200	0x00000100	LIN0, Channel #2
367	PERI_MS_PPU_FX_LIN0_CH3_CH	0x40508300	0x00000100	LIN0, Channel #3
368	PERI_MS_PPU_FX_LIN0_CH4_CH	0x40508400	0x00000100	LIN0, Channel #4
369	PERI_MS_PPU_FX_LIN0_CH5_CH	0x40508500	0x00000100	LIN0, Channel #5
370	PERI_MS_PPU_FX_LIN0_CH6_CH	0x40508600	0x00000100	LIN0, Channel #6
371	PERI_MS_PPU_FX_LIN0_CH7_CH	0x40508700	0x00000100	LIN0, Channel #7
372	PERI_MS_PPU_FX_CANFD0_CH0_CH	0x40520000	0x00000200	CAN0, Channel #0
373	PERI_MS_PPU_FX_CANFD0_CH1_CH	0x40520200	0x00000200	CAN0, Channel #1
374	PERI_MS_PPU_FX_CANFD0_CH2_CH	0x40520400	0x00000200	CAN0, Channel #2
375	PERI_MS_PPU_FX_CANFD1_CH0_CH	0x40540000	0x00000200	CAN1, Channel #0
376	PERI_MS_PPU_FX_CANFD1_CH1_CH	0x40540200	0x00000200	CAN1, Channel #1
377	PERI_MS_PPU_FX_CANFD1_CH2_CH	0x40540400	0x00000200	CAN1, Channel #2
378	PERI_MS_PPU_FX_CANFD0_MAIN	0x40521000	0x00000100	CAN0 main
379	PERI_MS_PPU_FX_CANFD1_MAIN	0x40541000	0x00000100	CAN1 main
380	PERI_MS_PPU_FX_CANFD0_BUF	0x40530000	0x00010000	CAN0 buffer
381	PERI_MS_PPU_FX_CANFD1_BUF	0x40550000	0x00010000	CAN1 buffer
382	PERI_MS_PPU_FX_SCB0	0x40600000	0x00010000	SCB0
383	PERI_MS_PPU_FX_SCB1	0x40610000	0x00010000	SCB1
384	PERI_MS_PPU_FX_SCB2	0x40620000	0x00010000	SCB2
385	PERI_MS_PPU_FX_SCB3	0x40630000	0x00010000	SCB3
386	PERI_MS_PPU_FX_SCB4	0x40640000	0x00010000	SCB4
387	PERI_MS_PPU_FX_SCB5	0x40650000	0x00010000	SCB5
388	PERI_MS_PPU_FX_SCB6	0x40660000	0x00010000	SCB6
389	PERI_MS_PPU_FX_SCB7	0x40670000	0x00010000	SCB7
390	PERI_MS_PPU_FX_PASS0_SAR0_SAR	0x40900000	0x00000400	PASS SAR0
391	PERI_MS_PPU_FX_PASS0_SAR1_SAR	0x40901000	0x00000400	PASS SAR1
392	PERI_MS_PPU_FX_PASS0_SAR2_SAR	0x40902000	0x00000400	PASS SAR2
393	PERI_MS_PPU_FX_PASS0_SAR0_CH0_CH	0x40900800	0x00000040	SAR0, Channel #0
394	PERI_MS_PPU_FX_PASS0_SAR0_CH1_CH	0x40900840	0x00000040	SAR0, Channel #1
395	PERI_MS_PPU_FX_PASS0_SAR0_CH2_CH	0x40900880	0x00000040	SAR0, Channel #2
396	PERI_MS_PPU_FX_PASS0_SAR0_CH3_CH	0x409008C0	0x00000040	SAR0, Channel #3
397	PERI_MS_PPU_FX_PASS0_SAR0_CH4_CH	0x40900900	0x00000040	SAR0, Channel #4
398	PERI_MS_PPU_FX_PASS0_SAR0_CH5_CH	0x40900940	0x00000040	SAR0, Channel #5
399	PERI_MS_PPU_FX_PASS0_SAR0_CH6_CH	0x40900980	0x00000040	SAR0, Channel #6
400	PERI_MS_PPU_FX_PASS0_SAR0_CH7_CH	0x409009C0	0x00000040	SAR0, Channel #7
401	PERI_MS_PPU_FX_PASS0_SAR0_CH8_CH	0x40900A00	0x00000040	SAR0, Channel #8
402	PERI_MS_PPU_FX_PASS0_SAR0_CH9_CH	0x40900A40	0x00000040	SAR0, Channel #9
403	PERI_MS_PPU_FX_PASS0_SAR0_CH10_CH	0x40900A80	0x00000040	SAR0, Channel #10
404	PERI_MS_PPU_FX_PASS0_SAR0_CH11_CH	0x40900AC0	0x00000040	SAR0, Channel #11
405	PERI_MS_PPU_FX_PASS0_SAR0_CH12_CH	0x40900B00	0x00000040	SAR0, Channel #12
406	PERI_MS_PPU_FX_PASS0_SAR0_CH13_CH	0x40900B40	0x00000040	SAR0, Channel #13
407	PERI_MS_PPU_FX_PASS0_SAR0_CH14_CH	0x40900B80	0x00000040	SAR0, Channel #14
408	PERI_MS_PPU_FX_PASS0_SAR0_CH15_CH	0x40900BC0	0x00000040	SAR0, Channel #15
409	PERI_MS_PPU_FX_PASS0_SAR0_CH16_CH	0x40900C00	0x00000040	SAR0, Channel #16
410	PERI_MS_PPU_FX_PASS0_SAR0_CH17_CH	0x40900C40	0x00000040	SAR0, Channel #17
411	PERI_MS_PPU_FX_PASS0_SAR0_CH18_CH	0x40900C80	0x00000040	SAR0, Channel #18
412	PERI_MS_PPU_FX_PASS0_SAR0_CH19_CH	0x40900CC0	0x00000040	SAR0, Channel #19
413	PERI_MS_PPU_FX_PASS0_SAR0_CH20_CH	0x40900D00	0x00000040	SAR0, Channel #20
414	PERI_MS_PPU_FX_PASS0_SAR0_CH21_CH	0x40900D40	0x00000040	SAR0, Channel #21
415	PERI_MS_PPU_FX_PASS0_SAR0_CH22_CH	0x40900D80	0x00000040	SAR0, Channel #22
416	PERI_MS_PPU_FX_PASS0_SAR0_CH23_CH	0x40900DC0	0x00000040	SAR0, Channel #23
417	PERI_MS_PPU_FX_PASS0_SAR1_CH0_CH	0x40901800	0x00000040	SAR1, Channel #0
418	PERI_MS_PPU_FX_PASS0_SAR1_CH1_CH	0x40901840	0x00000040	SAR1, Channel #1
419	PERI_MS_PPU_FX_PASS0_SAR1_CH2_CH	0x40901880	0x00000040	SAR1, Channel #2
420	PERI_MS_PPU_FX_PASS0_SAR1_CH3_CH	0x409018C0	0x00000040	SAR1, Channel #3
421	PERI_MS_PPU_FX_PASS0_SAR1_CH4_CH	0x40901900	0x00000040	SAR1, Channel #4
422	PERI_MS_PPU_FX_PASS0_SAR1_CH5_CH	0x40901940	0x00000040	SAR1, Channel #5
423	PERI_MS_PPU_FX_PASS0_SAR1_CH6_CH	0x40901980	0x00000040	SAR1, Channel #6
424	PERI_MS_PPU_FX_PASS0_SAR1_CH7_CH	0x409019C0	0x00000040	SAR1, Channel #7
425	PERI_MS_PPU_FX_PASS0_SAR1_CH8_CH	0x40901A00	0x00000040	SAR1, Channel #8
426	PERI_MS_PPU_FX_PASS0_SAR1_CH9_CH	0x40901A40	0x00000040	SAR1, Channel #9
427	PERI_MS_PPU_FX_PASS0_SAR1_CH10_CH	0x40901A80	0x00000040	SAR1, Channel #10
428	PERI_MS_PPU_FX_PASS0_SAR1_CH11_CH	0x40901AC0	0x00000040	SAR1, Channel #11
429	PERI_MS_PPU_FX_PASS0_SAR1_CH12_CH	0x40901B00	0x00000040	SAR1, Channel #12
430	PERI_MS_PPU_FX_PASS0_SAR1_CH13_CH	0x40901B40	0x00000040	SAR1, Channel #13
431	PERI_MS_PPU_FX_PASS0_SAR1_CH14_CH	0x40901B80	0x00000040	SAR1, Channel #14
432	PERI_MS_PPU_FX_PASS0_SAR1_CH15_CH	0x40901BC0	0x00000040	SAR1, Channel #15
433	PERI_MS_PPU_FX_PASS0_SAR1_CH16_CH	0x40901C00	0x00000040	SAR1, Channel #16
434	PERI_MS_PPU_FX_PASS0_SAR1_CH17_CH	0x40901C40	0x00000040	SAR1, Channel #17
435	PERI_MS_PPU_FX_PASS0_SAR1_CH18_CH	0x40901C80	0x00000040	SAR1, Channel #18
436	PERI_MS_PPU_FX_PASS0_SAR1_CH19_CH	0x40901CC0	0x00000040	SAR1, Channel #19
437	PERI_MS_PPU_FX_PASS0_SAR1_CH20_CH	0x40901D00	0x00000040	SAR1, Channel #20
438	PERI_MS_PPU_FX_PASS0_SAR1_CH21_CH	0x40901D40	0x00000040	SAR1, Channel #21
439	PERI_MS_PPU_FX_PASS0_SAR1_CH22_CH	0x40901D80	0x00000040	SAR1, Channel #22
440	PERI_MS_PPU_FX_PASS0_SAR1_CH23_CH	0x40901DC0	0x00000040	SAR1, Channel #23
441	PERI_MS_PPU_FX_PASS0_SAR1_CH24_CH	0x40901E00	0x00000040	SAR1, Channel #24
442	PERI_MS_PPU_FX_PASS0_SAR1_CH25_CH	0x40901E40	0x00000040	SAR1, Channel #25
443	PERI_MS_PPU_FX_PASS0_SAR1_CH26_CH	0x40901E80	0x00000040	SAR1, Channel #26
444	PERI_MS_PPU_FX_PASS0_SAR1_CH27_CH	0x40901EC0	0x00000040	SAR1, Channel #27
445	PERI_MS_PPU_FX_PASS0_SAR1_CH28_CH	0x40901F00	0x00000040	SAR1, Channel #28
446	PERI_MS_PPU_FX_PASS0_SAR1_CH29_CH	0x40901F40	0x00000040	SAR1, Channel #29
447	PERI_MS_PPU_FX_PASS0_SAR1_CH30_CH	0x40901F80	0x00000040	SAR1, Channel #30
448	PERI_MS_PPU_FX_PASS0_SAR1_CH31_CH	0x40901FC0	0x00000040	SAR1, Channel #31
449	PERI_MS_PPU_FX_PASS0_SAR2_CH0_CH	0x40902800	0x00000040	SAR2, Channel #0
450	PERI_MS_PPU_FX_PASS0_SAR2_CH1_CH	0x40902840	0x00000040	SAR2, Channel #1
451	PERI_MS_PPU_FX_PASS0_SAR2_CH2_CH	0x40902880	0x00000040	SAR2, Channel #2
452	PERI_MS_PPU_FX_PASS0_SAR2_CH3_CH	0x409028C0	0x00000040	SAR2, Channel #3
453	PERI_MS_PPU_FX_PASS0_SAR2_CH4_CH	0x40902900	0x00000040	SAR2, Channel #4
454	PERI_MS_PPU_FX_PASS0_SAR2_CH5_CH	0x40902940	0x00000040	SAR2, Channel #5
455	PERI_MS_PPU_FX_PASS0_SAR2_CH6_CH	0x40902980	0x00000040	SAR2, Channel #6
456	PERI_MS_PPU_FX_PASS0_SAR2_CH7_CH	0x409029C0	0x00000040	SAR2, Channel #7
457	PERI_MS_PPU_FX_PASS0_TOP	0x409F0000	0x00001000	PASS0 SAR main

Bus masters

The Arbiter (part of flash controller) performs priority-based arbitration based on the master identifier. Each bus master has a dedicated 4-bit master identifier. This master identifier is used for bus arbitration and IPC functionality.

Table 26.
Bus masters for access and protection control
ID No.	Master ID	Description
0	CPUSS_MS_ID_CM0	Master ID for CM0+
1	CPUSS_MS_ID_CRYPTO	Master ID for Crypto
2	CPUSS_MS_ID_DW0	Master ID for P-DMA 0
3	CPUSS_MS_ID_DW1	Master ID for P-DMA 1
4	CPUSS_MS_ID_DMAC	Master ID for M-DMA0
14	CPUSS_MS_ID_CM4	Master ID for CM4
15	CPUSS_MS_ID_TC	Master ID for DAP Tap Controller

Miscellaneous configuration

Table 27.
Miscellaneous configuration for CYT2B7 devices
Sl. No.	Configuration	Number/Instances	Description
0	SRSS_NUM_CLKPATH	4	Number of clock paths. One for each of FLL, PLL, Direct and CSV
1	SRSS_NUM_HFROOT	3	Number of CLK_HFs present
2	PERI_PC_NR	8	Number of protection contexts
3	PERI_CLOCK_NR	110	Number of programmable clocks (outputs)
4	PERI_DIV_8_NR	32	Number of divide-by-8 clock dividers
5	PERI_DIV_16_NR	16	Number of divide-by-16 clock dividers
6	PERI_DIV_24_5_NR	8	Number of divide-by-24.5 clock dividers
7	CPUSS_CM0P_MPU_NR	8	Number of MPU regions in CM0+
8	CPUSS_CM4_MPU_NR	8	Number of MPU regions in CM4
9	CPUSS_CRYPTO_BUFF_SIZE	2048	Number of 32-bit words in the IP internal memory buffer (to allow for a 256-B, 512-B, 1-KB, 2-KB, 4-KB, 8-KB, 16-KB, and 32-KB memory buffer)
10	CPUSS_FAULT_FAULT_NR	4	Number of fault structures
11	CPUSS_IPC_IPC_NR	8	Number of IPC structures 0 - Reserved for CM0+ access 1 - Reserved for CM4 access 2 - Reserved for DAP access Remaining for user purposes
12	SCBx_EZ_DATA_NR	256	Number of EZ memory bytes. This memory is used in EZ mode, CMD_RESP mode and FIFO mode. Note: Only SCB0 supports CMD_RESP mode
13	CPUSS_PROT_SMPU_STRUCT_NR	16	Number of SMPU protection structures
14	TCPWM_TR_ONE_CNT_NR	3	Number of input triggers per counter, routed to one counter
15	TCPWM_TR_ALL_CNT_NR	27	Number of input triggers routed to all counters, based on the pin package
16	TCPWM_GRP_NR	3	Number of TCPWM0 counter groups
17	TCPWM_GRP_NR0_GRP_GRP_CNT_NR	63	Number of counters per TCPWM0 Group #0
18	TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH	16	Counter width in number of bits per TCPWM0 Group #0
19	TCPWM_GRP_NR1_GRP_GRP_CNT_NR	12	Number of counters per TCPWM0 Group #1
20	TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH	16	Counter width in number of bits per TCPWM0 Group #1
21	TCPWM_GRP_NR2_GRP_GRP_CNT_NR	4	Number of counters per TCPWM0 Group #2
22	TCPWM_GRP_NR2_CNT_GRP_CNT_WIDTH	32	Counter width in number of bits per TCPWM0 Group #2
23	CANFD0_MRAM_SIZE/CANFD1_MRAM_SIZE	24	Message RAM size in KB shared by all the channels
24	EVTGEN_COMP_STRUCT_NR	11	Number of Event Generator comparator structures

Development support

CYT2B7 has a rich set of documentation, programming tools, and online resources to assist during the development process. Visit www.infineon.com to find out more.

Documentation

A suite of documentation supports CYT2B7 to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents.

Software user guide

A step-by-step guide for using the sample driver library along with third-party IDEs such as IAR EWARM and GHS Multi.

Technical reference manual

The Technical Reference Manual (TRM) contains all the technical detail needed to use a CYT2B7 device, including a complete description of all registers. The TRM is available in the documentation section at www.infineon.com .

Tools

CYT2B7 is supported on third-party development tool ecosystems such as IAR and GHS. CYT2B7 is also supported by Infineon programming utilities for programming, erasing, or reading using Infineon’s MiniProg4 or Segger J-link. More details are available in the documentation section at www.infineon.com .

Electrical specifications

Absolute maximum ratings

Use of this device under conditions outside the min and max limits listed in Table 28 may cause permanent damage to the device. Exposure to conditions within the limits of Table 28 but beyond those of normal operation for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When operated under conditions within the limits of Table 28 but beyond those of normal operation, the device may not operate to specification.

Power considerations

The average chip-junction temperature, T _J , in °C, may be calculated using the below equation:

T _J = T _A + (P _D x θ _JA )

Where:

T _A is the ambient temperature in °C.

θ _JA is the package junction-to-ambient thermal resistance, in °C/W.

P _D is the sum of P _INT and P _IO (P _D = P _INT + P _IO).

P _INT is the chip internal power. (P _INT = V _DDD × I _DD + V _DDA × I _A)

P _IO represents the power dissipation on input and output pins; user determined.

For most applications, P _IO < P _INT and may be neglected.

On the other hand, P _IO may be significant if the device is configured to continuously drive external modules and/or memories.

Table 28.
Absolute maximum ratings
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID10	V _{DDD_ABS}	V _DDD power supply voltage	V _SSD – 0.3	–	V _SSD + 6.0	V	For ports 0, 1, 2, 3, 4, 5, 16, 17, 18, 19, 20, 21, 22, 23
SID10B	V _{DDIO_1_ABS}	V _{DDIO_1} power supply voltage ³⁵	V _SSD – 0.3	–	V _SSD + 6.0	V	V _{DDIO_1} ≥ V _DDD For ports 6, 7, 8, 9
SID10C1	V _{DDIO_2_ABS}	V _{DDIO_2} power supply voltage ³⁵	V _SSD – 0.3	–	V _SSD + 6.0	V	For ports 10, 11, 12, 13, 14, 15
SID11	V _{DDA_ABS}	V _DDA analog power supply voltage ³⁵	V _SSA – 0.3	–	V _SSA + 6.0	V	V _{DDIO_2} = V _DDA
SID12	V _{REFH_ABS}	Analog reference voltage, HIGH ³⁵	V _SSA – 0.3	–	V _SSA + 6.0	V	V _REFH ≤V _DDA + 0.3 V
SID12A	V _{REFL_ABS}	Analog reference voltage, LOW ³⁵	V _SSA – 0.3	–	V _SSA + 0.3	V
SID15A	V _{I0_ABS0}	Input voltage ³⁵	V _SSD – 0.5	–	V _DDD + 0.5	V	For ports 0, 1, 2, 3, 4, 5, 16, 17, 18, 19, 20, 21, 22, 23
SID15B	V _{I1_ABS1}	Input voltage ³⁵	V _SSD – 0.5	–	V _{DDIO_1} + 0.5	V	For ports 6, 7, 8, 9 ³⁶
SID15C	V _{I2_ABS2}	Input voltage ³⁵	V _SSD – 0.5	–	V _{DDIO_2} + 0.5	V	For ports 10, 11, 12, 13, 14, 15
SID16	V _{IA_ABS}	Analog input voltage ³⁵	V _SSA – 0.3	–	V _DDA + 0.3	V
SID17A	V _{O0_ABS0}	Output voltage ³⁵	V _SSD – 0.3	–	V _DDD + 0.3	V	For ports 0, 1, 2, 3, 4, 5, 16, 17, 18, 19, 20, 21, 22, 23
SID17B	V _{O1_ABS1}	Output voltage ³⁵	V _SSD – 0.3	–	V _{DDIO_1} + 0.3	V	For ports 6, 7, 8, 9 ³⁶
SID17C	V _{O2_ABS2}	Output voltage ³⁵	V _SSD – 0.3	–	V _{DDIO_2} + 0.3	V	For ports 10, 11, 12, 13, 14, 15
SID18	I _{CLAMP_ABS}	Maximum clamp current , , ³⁹	–5	–	5	mA
SID18A	I _{CLAMP_SUPPLY_POS_ABS}	Maximum positive clamp current per I/O supply pin. Limit applies to I/O supply pin closest to the B+ injected current	–	–	10	mA	+B injected DC currents are not allowed for Ports 11 and 21 .
SID18B	I _{CLAMP_SUPPLY_NEG_ABS}	Maximum negative clamp current per I/O ground pin. Limit applies to I/O supply pin closest to the B+ injected current ⁴⁰	–	–	10	mA	+B injected DC currents are not allowed for Ports 11 and 21 .
SID18C	I _{CLAMP_TOTAL_POS_ABS}	Maximum positive clamp current per I/O supply, if not limited by the per supply pin (based on SID18A).	–	–	50	mA
SID18D	I _{CLAMP_TOTAL_NEG_ABS}	Maximum negative clamp current per I/O ground, if not limited by the per supply pin (based on SID18B).	–	–	50	mA
SID20A	I _{OL1A_ABS}	LOW-level maximum output current	–	–	6	mA	For GPIO_STD, configured for drive_sel<1:0>= 0b0X
SID20B	I _{OL1B_ABS}	LOW-level maximum output current ⁴¹	–	–	2	mA	For GPIO_STD, configured for drive_sel<1:0>= 0b10
SID20C	I _{OL1C_ABS}	LOW-level maximum output current ⁴¹	–	–	1	mA	For GPIO_STD, configured for drive_sel<1:0>= 0b11
SID21A	I _{OL2A_ABS}	LOW-level maximum output current ⁴¹	–	–	6	mA	For GPIO_ENH, configured for drive_sel<1:0>= 0b0X
SID21B	I _{OL2B_ABS}	LOW-level maximum output current ⁴¹	–	–	2	mA	For GPIO_ENH, configured for drive_sel<1:0>= 0b10
SID21C	I _{OL2C_ABS}	LOW-level maximum output current ⁴¹	–	–	1	mA	For GPIO_ENH, configured for drive_sel<1:0>= 0b11
SID26A	∑I _{OL_ABS_GPIO}	LOW-level total output current ⁴¹	–	–	50	mA
SID27A	I _{OH1A_ABS}	HIGH-level maximum output current ⁴¹	–	–	–5	mA	For GPIO_STD, configured for drive_sel<1:0>= 0b0X
SID27B	I _{OH1B_ABS}	HIGH-level maximum output current ⁴¹	–	–	–2	mA	For GPIO_STD, configured for drive_sel<1:0>= 0b10
SID27C	I _{OH1C_ABS}	HIGH-level maximum output current ⁴¹	–	–	–1	mA	For GPIO_STD, configured for drive_sel<1:0>= 0b11
SID28A	I _{OH2A_ABS}	HIGH-level maximum output current ⁴¹	–	–	–5	mA	For GPIO_ENH, configured for drive_sel<1:0>= 0b0X
SID28B	I _{OH2B_ABS}	HIGH-level maximum output current ⁴¹	–	–	–2	mA	For GPIO_ENH, configured for drive_sel<1:0>= 0b10
SID28C	I _{OH2C_ABS}	HIGH-level maximum output current ⁴¹	–	–	–1	mA	For GPIO_ENH, configured for drive_sel<1:0 ≥ 0b11
SID33A	∑I _{OH_ABS_GPIO}	HIGH-level total output current ⁴²	–	–	–50	mA
SID34	P _D	Power dissipation	–	–	1000	mW	T _J should not exceed 150°C
SID35	T _A	Ambient temperature	–40	–	105	°C	For S-grade devices
SID36	T _A	Ambient temperature	–40	–	125	°C	For E-grade devices
SID37	T _STG	Storage temperature	–55	–	150	°C
SID38	T _J	Operating Junction temperature	–40	–	150	°C
SID39A	V _{ESD_HBM}	Electrostatic discharge human body model	2000	–	–	V
SID39B1	V _{ESD_CDM1}	Electrostatic discharge charged device model for corner pins	750	–	–	V
SID39B2	V _{ESD_CDM2}	Electrostatic discharge charged device model for all other pins	500	–	–	V
SID39C	I _LU	The maximum pin current the device can tolerate before triggering a latch-up	–100	–	100	mA

Figure 15.
Example of a recommended circuit
⁴³

Warning:

Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current, or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

Recommended operating conditions

Table 29.
Device-level specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit
SID40	V _DDD , V _DDA , V _{DDIO_1} , V _{DDIO_2} ,	Power supply voltage ⁴⁴	2 ⁴⁵	–	5.5 ⁴⁶	V
SID40A	V _{DDIO_1_EFP}	Power supply voltage for eFuse programming ⁴⁷	3	–	5.5	V
SID41	C _S1	Smoothing capacitor ⁴⁸ , ⁴⁹	3.76	–	11	µF

Smoothing capacitor should be placed as close as possible to the V _CCD pin.

DC specifications

Table 30.DC specifications, CPU current and transition time specifications.All specifications are valid for –40°C ≤ T_A ≤ 125°C and for 2.7 V to 5.5 V except where noted.
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID49C1A	I _{DD1_CM04_8_1A}	LP Active mode (CM4 and CM0+ at 8 MHz, all peripherals are disabled)	–	4	9	mA	CM0+ and CM4 clocked at 8 MHz with IMO. All peripherals are disabled. No I/O toggling. TYP: T _A = 25°C, V _DDD = 5.0 V, process typ (TT), CM0+ and CM4 executing Dhrystone from flash with cache enabled MAX: T _A = 25°C, V _DDD = 5.5 V, process worst (FF), CM0+ and CM4 executing Dhrystone from flash with cache enabled.
SID49CA	I _{DD1_CM04_8A}	LP Active mode (CM4 and CM0+ at 8 MHz, all peripherals are enabled)	–	5	51	mA	CM0+ and CM4 clocked at 8 MHz with IMO. All peripherals are enabled. No I/O toggling. M-DMA transferring data from code + work flash, P-DMA chains with maximum trigger activity. TYP: T _A = 25°C, V _DDD = 5.0 V, process typ (TT), CM0+ and CM4 executing Dhrystone from flash with cache enabled MAX: T _A = 125°C, V _DDD = 5.5 V, process worst (FF), CM0+ and CM4 executing max_power.c from flash with cache enabled.
SID49E1	I _{DD1_F160_1M}	Active mode (CM4 at 160 MHz, CM0+ at 80 MHz, all peripherals are enabled)	–	39	102	mA	PLL enabled at 160 MHz with ECO reference. All peripherals are enabled. No I/O toggling. M-DMA transferring data from code + work flash, P-DMA chains with maximum trigger activity. TYP: T _A = 25°C, V _DDD = 5.0 V, process typ (TT), CM4 and CM0+ executing Dhrystone from flash with cache enabled. MAX: T _A = 125°C, V _DDD = 5.5 V, process worst (FF), CM4 and CM0+ executing max_power.c from flash with cache enabled
SID53A1	I _{DD2_8_1}	All CPUs in Sleep mode	–	3	46	mA	PLL disabled, CM4 and CM0+ are sleeping at 8 MHz with IMO. All peripherals, peripheral clocks, interrupts, CSV, DMA, FLL, ECO are disabled. No I/O toggling. Typ: T _A = 25°C, V _DDD = 5.0 V, process typ (TT) Max: T _A = 125°C, V _DDD = 5.5 V, process worst (FF)
SID56A	I _{DD_CWU2}	Average current for cyclic wake-up operation This is the average current for the specified LP Active mode and DeepSleep mode (RTC, WDT, and Event generator operating).	–	46	136	µA	V _DDD = 5.5 V, T _A = 25°C, 64-KB SRAM, ILO0 operation in DeepSleep, Smart I/O operations with ILO0, CM0+, CM4: Retained TYP: process typ (TT) MAX: process worst (FF) This average current is achieved under the following conditions. MCU repetitively goes from DeepSleep to LP Active with a period of 32 ms. One of the I/Os is toggled using Smart I/O to activate an external sensor connected to an analog input of A/D in DeepSleep After 200 µs delay, the CM4 wakes up by event generator trigger to LP Active mode with IMO and A/D conversion is triggered by software. Group A/D conversion is performed on 5 channels with the sampling time of 1 µs each. Once the group A/D conversion is finished, and the results fit in the window of the range comparator, the I/O is toggled back by software to de-activate the sensor and the CM4 goes back to DeepSleep.
SID59A	I _{DD_DS64B}	64-KB SRAM retention, ILO0 operation in DeepSleep mode	–	35	130	µA	DeepSleep Mode (RTC, WDT, and event generator operating, all other peripherals are off except for retention registers), T _A = 25°C, CM0+, CM4: Retained Typ: V _DDD = 5.0 V, process typ (TT) Max: V _DDD = 5.5 V, process worst (FF)
SID61A	I _{DD_DS64D}	64-KB SRAM retention, ILO0 operation in DeepSleep mode	–	0.9	3.5	mA	DeepSleep Mode steady state at T _A = 125°C (RTC, WDT, and event generator operating, all other peripherals are off except for retention registers),CM0+, CM4: Retained Typ: V _DDD = 5.0 V, process typ (TT) Max: V _DDD = 5.5 V, process worst (FF)
Hibernate Mode
SID62	I _{DD_HIB1}	Hibernate Mode	–	5	–	µA	ILO0/WDT operating. All other peripherals, and all CPUs are off. T _A = 25°C, V _DDD = 5.5 V, process typ (TT)
SID62A	I _{DD_HIB2}	Hibernate Mode	–	–	130	µA	ILO0/WDT operating. All other peripherals, and all CPUs are off. T _A = 125°C, V _DDD = 5.5 V, process worst (FF)
Power mode transition times
SID65	t _{ACT_DS}	Power down time from Active to DeepSleep	–	–	2.5	µs	When the IMO is already running and all HFCLK roots are at least 8 MHz. HFCLK roots that are slower than this will require additional time to turn off.
SID63	t _{DS_ACT}	DeepSleep to Active transition time (IMO clock, SRAM execution)	–	–	10	µs	When using the 8-MHz IMO. Measured from wakeup interrupt during DeepSleep until wakeup.
SID63C	t _{DS_ACT}	DeepSleep to Active transition time (IMO clock, flash execution)	–	–	20 ⁵⁰	µs	When using the 8-MHz IMO. Measured from wakeup interrupt during DeepSleep until flash execution.
SID63A	t _{DS_ACT_FLL}	DeepSleep to Active transition time (FLL clock, SRAM execution)	–	–	15 ⁵⁰	µs	When using the FLL to generate 96 MHz from the 8-MHz IMO. Measured from wakeup interrupt during DeepSleep until the FLL locks.
SID63D	t _{DS_ACT_FLL1}	DeepSleep to Active transition time (FLL clock, flash execution)	–	–	21.5 ⁵⁰	µs	When using the FLL to generate 96 MHz from the 8-MHz IMO. Measured from wakeup interrupt during DeepSleep until flash execution.
SID63B	t _{DS_ACT_PLL}	DeepSleep to Active transition time (PLL clock, SRAM or flash execution)	–	–	60 ⁵⁰	µs	When using the PLL to generate 96 MHz from the 8-MHz IMO. Measured from wakeup interrupt during DeepSleep until the PLL locks.
SID68	t _{HVR_ACT}	Release time from HV reset (POR, BOD, OVD, OCD, WDT, Hibernate wakeup, or XRES_L) release until CM0+ begins executing ROM boot	–	–	265	µs	Without boot runtime. Guaranteed by design
SID68A	t _{LVR_ACT}	Release time from LV reset (Fault, Internal system reset, MCWDT, or CSV) during Active/Sleep until CM0+ begins executing ROM boot	–	–	10	µs	Without boot runtime. Guaranteed by design
SID68B	t _{LVR_DS}	Release time from LV reset (Fault, or MCWDT) during DeepSleep until CM0+ begins executing ROM boot	–	–	15	µs	Without boot runtime. Guaranteed by design
SID80A	t _{RB_N}	ROM boot startup time or wakeup time from hibernate in NORMAL protection state	–	–	1800	µs	Guaranteed by Design, CM0+ clocked at 100 MHz (Flash boot version 3.1.0.556 and later)
SID80B	t _{RB_S}	ROM boot startup time or wakeup time from hibernate in SECURE protection state	–	–	2740	µs	Guaranteed by Design, CM0+ clocked at 100 MHz (Flash boot version 3.1.0.556 and later)
SID81A	t _FB	Flash boot startup time or wakeup time from hibernate in NORMAL/SECURE protection state	–	–	80	µs	Guaranteed by Design, TOC2_FLAGS=0x2CF, CM0+ clocked at 100 MHz (Flash boot version 3.1.0.556 and later), Listen window = 0 ms
SID81B	t _{FB_A}	Flash boot with app authentication time in NORMAL/SECURE protection state	–	–	5000	µs	Guaranteed by Design, TOC2_FLAGS=0x24F, CM0+ clocked at 100 MHz (Flash boot version 3.1.0.556 and later), Listen window = 0 ms, Public key exponent e = 0x010001, App size is 64 KB with the last 256 bytes being a digital signature in RSASSA-PKCS1-v1.5 Valid for RSA-2048.
SID80A_2	t _{RB_N_2}	ROM boot startup time or wakeup time from hibernate in NORMAL protection state	–	–	2930	µs	Guaranteed by Design, CM0+ clocked at 50 MHz (Flash boot version earlier than 3.1.0.556)
SID80B_2	t _{RB_S_2}	ROM boot startup time or wakeup time from hibernate in SECURE protection state	–	–	4680	µs	Guaranteed by Design, CM0+ clocked at 50 MHz (Flash boot version earlier than 3.1.0.556)
SID81A_2	t _{FB_2}	Flash boot startup time or wakeup time from hibernate in NORMAL/SECURE protection state	–	–	200	µs	Guaranteed by Design, TOC2_FLAGS=0x2CF, CM0+ clocked at 50 MHz (Flash boot version earlier than 3.1.0.556), Listen window = 0 ms
SID81B_2	t _{FB_A_2}	Flash boot with app authentication time in NORMAL/SECURE protection state	–	–	10000	µs	Guaranteed by Design, TOC2_FLAGS=0x24F, CM0+ clocked at 50 MHz (Flash boot version earlier than 3.1.0.556), Listen window = 0 ms, Public key exponent e = 0x010001, App size is 64 KB with the last 256 bytes being a digital signature in RSASSA-PKCS1-v1.5 Valid for RSA-2048.
Regulator specifications
SID600	V _CCD	Core supply voltage	1.05	1.1	1.15	V
SID601	I _{DD_ACT}	Regulator operating current in Active/Sleep mode	–	80	150	µA	Guaranteed by design
SID602	I _{DD_DPSLP}	Regulator operating current in DeepSleep mode	–	1.5	20	µA	Guaranteed by design
SID604	I _OUT	Available regulator output current for operation	–	–	150	mA	Without triggering OVD
SID603	I _RUSH	In-rush current	–	–	375	mA	Average V _DDD current until C _s1 (connected to V _CCD pin) is charged after Active regulator is turned on

Reset specifications

All specifications are valid for –40°C ≤ T _A ≤ 125°C and for 2.7 V to 5.5 V except where noted.

Table 31.
XRES_L reset
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
XRES_L DC specifications
SID73	I _{DD_XRES}	I _DD when XRES_L asserted	–	–	0.9	mA	T _A = 125°C, V _DDD = 5.5 V, process worst (FF)
SID74	V _IH	Input voltage HIGH threshold	0.7 × V _DDD	–	–	V	CMOS input
SID75	V _IL	Input voltage LOW threshold	–	–	0.3 × V _DDD	V	CMOS input
SID76	R _PULLUP	Pull-up resistor	7	–	20	kΩ
SID77	C _IN	Input capacitance	–	–	5	pF
SID78	V _HYSXRES	Input voltage hysteresis	0.05 × V _DDD	–	–	V
XRES_L AC specifications
SID70	t _{XRES_ACT}	XRES_L release to Active transition time	–	–	265	µs	Without boot runtime. Guaranteed by design
SID71	t _{XRES_PW}	XRES_L pulse width	5	–	–	µs
SID72	t _{XRES_FT}	Pulse suppression width	100	–	–	ns

I/O

All specifications are valid for –40°C ≤ T _A ≤ 125°C and for 2.7 V to 5.5 V except where noted.

Table 32.
I/O specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
GPIO_STD Specifications for ports P1 through P23
SID650	V _{OL1_GPIO_STD}	Output voltage LOW level	–	–	0.6	V	I _OL = 6 mA drive_sel<1:0> = 0b0X, 4.5 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} ≤ 5.5 V
SID650C	V _{OL1C_GPIO_STD}	Output voltage LOW level	–	–	0.4	V	I _OL = 5 mA drive_sel<1:0> = 0b0X, 4.5 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} ≤ 5.5 V
SID651	V _{OL2_GPIO_STD}	Output voltage LOW level	–	–	0.4	V	I _OL = 2 mA drive_sel<1:0> = 0b0X, 2.7 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} < 4.5 V
SID652	V _{OL3_GPIO_STD}	Output voltage LOW level	–	–	0.4	V	I _OL = 1 mA drive_sel<1:0> = 0b10, 2.7 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} < 4.5 V
SID652C	V _{OL3C_GPIO_STD}	Output voltage LOW level	–	–	0.4	V	I _OL = 2 mA drive_sel<1:0> = 0b10, 4.5 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} ≤ 5.5 V
SID653	V _{OL4_GPIO_STD}	Output voltage LOW level	–	–	0.4	V	I _OL = 0.5 mA drive_sel<1:0> = 0b11, 2.7 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} < 4.5 V
SID653C	V _{OL4C_GPIO_STD}	Output voltage LOW level	–	–	0.4	V	I _OL = 1 mA drive_sel<1:0> = 0b11, 4.5 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} ≤ 5.5 V
SID654	V _{OH1_GPIO_STD}	Output voltage HIGH level	(V _DDD or V _{DDIO_1} or V _{DDIO_2)} – 0.5	–	–	V	I _OH = –2 mA drive_sel<1:0> = 0b0X, 2.7 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} < 4.5 V
SID655	V _{OH2_GPIO_STD}	Output voltage HIGH level	(V _DDD or V _{DDIO_1} or V _{DDIO_2)} – 0.5	–	–	V	I _OH = –5 mA drive_sel<1:0> = 0b0X, 4.5 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} ≤ 5.5 V
SID656	V _{OH3_GPIO_STD}	Output voltage HIGH level	(V _DDD or V _{DDIO_1} or V _{DDIO_2)} – 0.5	–	–	V	I _OH = –1 mA drive_sel<1:0> = 0b10, 2.7 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} < 4.5 V
SID656C	V _{OH3C_GPIO_STD}	Output voltage HIGH level	(V _DDD or V _{DDIO_1} or V _{DDIO_2)} – 0.5	–	–	V	I _OH = –2 mA drive_sel<1:0> = 0b10, 4.5 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} ≤ 5.5 V
SID657	V _{OH4_GPIO_STD}	Output voltage HIGH level	(V _DDD or V _{DDIO_1} or V _{DDIO_2)} – 0.5	–	–	V	I _OH = –0.5 mA drive_sel<1:0> = 0b11, 2.7 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} < 4.5 V
SID657C	V _{OH4C_GPIO_STD}	Output voltage HIGH level	(V _DDD or V _{DDIO_1} or V _{DDIO_2)} – 0.5	–	–	V	I _OH = –1 mA drive_sel<1:0> = 0b11, 4.5 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} ≤ 5.5 V
SID658	R _{PD_GPIO_STD}	Pull-down resistance	25	50	100	kΩ
SID659	R _{PU_GPIO_STD}	Pull-up resistance	25	50	100	kΩ
SID660	V _{IH_CMOS_GPIO_STD}	Input voltage HIGH threshold in CMOS mode	0.7 × (V _DDD or V _{DDIO_1} or V _{DDIO_2)}	–	–	V
SID661	V _{IH_TTL_GPIO_STD}	Input voltage HIGH threshold in TTL mode	2.0	–	–	V
SID662	V _{IH_AUTO_GPIO_STD}	Input voltage HIGH threshold in AUTO mode	0.8 × (V _DDD or V _{DDIO_1} or V _{DDIO_2)}	–	–	V
SID663	V _{IL_CMOS_GPIO_STD}	Input voltage LOW threshold in CMOS mode	–	–	0.3 × (V _DDD or V _{DDIO_1} or V _{DDIO_2)}	V
SID664	V _{IL_TTL_GPIO_STD}	Input voltage LOW threshold in TTL mode	–	–	0.8	V
SID665	V _{IL_AUTO_GPIO_STD}	Input voltage LOW threshold in AUTO mode	–	–	0.5 × (V _DDD or V _{DDIO_1} or V _{DDIO_2} ₎	V
SID666	V _{HYST_CMOS_GPIO_STD}	Hysteresis in CMOS mode	0.05 × (V _DDD or V _{DDIO_1} or V _{DDIO_2)}	–	–	V
SID668	V _{HYST_AUTO_GPIO_STD}	Hysteresis in AUTO mode	0.05 × (V _DDD or V _{DDIO_1} or V _{DDIO_2)}	–	–	V
SID669	C _{in_GPIO_STD}	Input pin capacitance	–	–	5	pF	For 10 MHz and 100 MHz
SID670	I _{IL_GPIO_STD}	Input leakage current	–250	0.02	250	nA	For GPIO_STD except P21.0, P21.1, P21.2, P21.3, P21.4, P23.3, P23.4. V _{DDIO_1} = V _{DDIO_2} = V _DDD = V _DDA = 5.5 V, V _SSD < V _I < V _DDD , V _{DDIO_1} , V _{DDIO_2} –40°C ≤ TA ≤125°C TYP: T _A = 25°C, V _{DDIO_1} = V _{DDIO_2} = V _DDD = V _DDA = 5.0 V
SID670C	I _{IL_GPIO_STD_B}	Input leakage current	–700	0.02	700	nA	Only for P21.0, P21.1, P21.2, P21.3, P21.4, P23.3, P23.4. V _{DDIO_1} = V _{DDIO_2} = V _DDD = V _DDA = 5.5 V, V _SSD < V _I < V _DDD , V _{DDIO_1} , V _{DDIO_2} –40°C ≤ TA ≤125°C TYP: T _A = 25°C, V _{DDIO_1} = V _{DDIO_2} = V _DDD = V _DDA = 5.0 V
SID671	t _R or t _F (fast) _{_20_0_GPIO_STD}	Rise time or fall time (10% to 90% of V _DDIO )	1	–	10	ns	20-pF load, drive_sel<1:0> = 0b00
SID672	t _R or t _F (fast) _{_50_0_GPIO_STD}	Rise time or fall time (10% to 90% of V _DDIO )	1	–	20	ns	50-pF load, drive_sel<1:0> = 0b00
SID673	t _R or t _F (fast) _{_20_1_GPIO_STD}	Rise time or fall time (10% to 90% of V _DDIO )	1	–	20	ns	20-pF load, drive_sel<1:0> = 0b01, guaranteed by design
SID674	t _R or t _F (fast) _{_10_2_GPIO_STD}	Rise time or fall time (10% to 90% of V _DDIO )	1	–	20	ns	10-pF load, drive_sel<1:0> = 0b10, guaranteed by design
SID675	t _R or t _F (fast) _{_6_3_GPIO_STD}	Rise time or fall time (10% to 90% of V _DDIO )	1	–	20	ns	6-pF load, drive_sel<1:0> = 0b11, guaranteed by design
SID676	t _F (fast) _{_100_GPIO_STD}	Fall time (30% to 70% of V _DDIO )	0.35	–	250	ns	10-pF to 400-pF load, RPU = 767 Ω, drive_sel<1:0>= 0b00, Freq = 100 kHz
SID677	t _F (fast) _{_400_GPIO_STD}	Fall time (30% to 70% of V _DDIO )	0.35	–	250	ns	10-pF to 400-pF load, RPU = 350 Ω, drive_sel<1:0>= 0b00, Freq = 400 kHz
SID678	f _{IN_GPIO_STD}	Input frequency	–	–	100	MHz
SID679	f _{OUT_GPIO_STD0H}	Output frequency	–	–	50	MHz	20-pF load, drive_sel<1:0>= 00, 4.5 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} ≤ 5.5 V
SID680	f _{OUT_GPIO_STD0L}	Output frequency	–	–	32	MHz	20-pF load, drive_sel<1:0>= 00, 2.7 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} < 4.5 V
SID681	f _{OUT_GPIO_STD1H}	Output frequency	–	–	25	MHz	20-pF load, drive_sel<1:0>= 01, 4.5 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} ≤ 5.5 V
SID682	f _{OUT_GPIO_STD1L}	Output frequency	–	–	15	MHz	20-pF load, drive_sel<1:0>= 01, 2.7 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} < 4.5 V
SID683	f _{OUT_GPIO_STD2H}	Output frequency	–	–	25	MHz	10-pF load, drive_sel<1:0>= 10, 4.5 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} ≤ 5.5 V
SID684	f _{OUT_GPIO_STD2L}	Output frequency	–	–	15	MHz	10-pF load, drive_sel<1:0>= 10, 2.7 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} < 4.5 V
SID685	f _{OUT_GPIO_STD3H}	Output frequency	–	–	15	MHz	6-pF load, drive_sel<1:0>= 11, 4.5 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} ≤ 5.5 V
SID686	f _{OUT_GPIO_STD3L}	Output frequency	–	–	10	MHz	6-pF load, drive_sel<1:0>= 11, 2.7 V ≤ V _DDD or V _{DDIO_1} or V _{DDIO_2} < 4.5 V
GPIO_ENH specifications only for P0
SID650A	V _{OL1_GPIO_ENH}	Output voltage LOW level	–	–	0.6	V	I _OL = 6 mA drive_sel<1:0> = 0b0X, 2.7 V ≤ V _DDD ≤ 5.5 V
SID650D	V _{OL1D_GPIO_ENH}	Output voltage LOW level	–	–	0.4	V	I _OL = 5 mA drive_sel<1:0> = 0b0X, 4.5 V ≤ V _DDD ≤ 5.5 V
SID651A	V _{OL2_GPIO_ENH}	Output voltage LOW level	–	–	0.4	V	I _OL = 2 mA, 3 mA drive_sel<1:0> = 0b0X, 2.7 V ≤ V _DDD < 4.5 V
SID652A	V _{OL3_GPIO_ENH}	Output voltage LOW level	–	–	0.4	V	I _OL = 1 mA drive_sel<1:0> = 0b10, 2.7 V ≤ V _DDD < 4.5 V
SID652D	V _{OL3D_GPIO_ENH}	Output voltage LOW level	–	–	0.4	V	I _OL = 2 mA drive_sel<1:0> = 0b10, 4.5 V ≤ V _DDD ≤ 5.5 V
SID653A	V _{OL4_GPIO_ENH}	Output voltage LOW level	–	–	0.4	V	I _OL = 0.5 mA drive_sel<1:0> = 0b11, 2.7 V ≤ V _DDD < 4.5 V
SID653D	V _{OL4D_GPIO_ENH}	Output voltage LOW level	–	–	0.4	V	I _OL = 1 mA drive_sel<1:0> = 0b11, 4.5 V ≤ V _DDD ≤ 5.5 V
SID654A	V _{OH1_GPIO_ENH}	Output voltage HIGH level	V _DDD – 0.5	–	–	V	I _OL = –2 mA drive_sel<1:0> = 0b0X, 2.7 V ≤ V _DDD < 4.5 V
SID655A	V _{OH2_GPIO_ENH}	Output voltage HIGH level	V _DDD – 0.5	–	–	V	I _OL = –5 mA drive_sel<1:0> = 0b0X, 4.5 V ≤ V _DDD ≤ 5.5 V
SID656A	V _{OH3_GPIO_ENH}	Output voltage HIGH level	V _DDD – 0.5	–	–	V	I _OL = –1 mA drive_sel<1:0> = 0b10, 2.7 V ≤ V _DDD < 4.5 V
SID656D	V _{OH3D_GPIO_ENH}	Output voltage HIGH level	V _DDD – 0.5	–	–	V	I _OL = –2 mA drive_sel<1:0> = 0b10, 4.5 V ≤ V _DDD ≤ 5.5 V
SID657A	V _{OH4_GPIO_ENH}	Output voltage HIGH level	V _DDD – 0.5	–	–	V	I _OL = –0.5 mA drive_sel<1:0> = 0b11, 2.7 V ≤ V _DDD < 4.5 V
SID657D	V _{OH4D_GPIO_ENH}	Output voltage HIGH level	V _DDD – 0.5	–	–	V	I _OL = –1 mA drive_sel<1:0> = 0b11, 4.5 V ≤ V _DDD ≤ 5.5 V
SID658A	R _{PD_GPIO_ENH}	Pull-down resistance	25	50	100	kΩ
SID659A	R _{PU_GPIO_ENH}	Pull-up resistance	25	50	100	kΩ
SID660A	V _{IH_CMOS_GPIO_ENH}	Input voltage HIGH threshold in CMOS mode	0.7 × V _DDD	–	–	V
SID661A	V _{IH_TTL_GPIO_ENH}	Input voltage HIGH threshold in TTL mode	2	–	–	V
SID662A	V _{IH_AUTO_GPIO_ENH}	Input voltage HIGH threshold in AUTO mode	0.8 × V _DDD	–	–	V
SID663A	V _{IL_CMOS_GPIO_ENH}	Input voltage LOW threshold in CMOS mode	–	–	0.3 × V _DDD	V
SID664A	V _{IL_TTL_GPIO_ENH}	Input voltage LOW threshold in TTL mode	–	–	0.8	V
SID665A	V _{IL_AUTO_GPIO_ENH}	Input voltage LOW threshold in AUTO mode	–	–	0.5 × V _DDD	V
SID666A	V _{HYST_CMOS_GPIO_ENH}	Hysteresis in CMOS mode	0.05 × V _DDD	–	–	V
SID668A	V _{HYST_AUTO_GPIO_ENH}	Hysteresis in AUTO mode	0.05 × V _DDD	–	–	V
SID669A	C _{in_GPIO_ENH}	Input pin capacitance	–	–	5	pF	For 10 MHz and 100 MHz
SID670A	I _{IL_GPIO_ENH}	Input leakage current	–350	0.055	350	nA	V _DDD = V _DDA = 5.5 V, V _SSD < V _I < V _DDD , –40°C ≤ T _A ≤ 125°C TYP: T _A = 25°C, V _DDD = V _DDA = 5.0 V
SID671A	t _R or t _F (fast) _{_20_0_GPIO_ENH}	Rise time or fall time (10% to 90% of V _DDIO )	1	–	10	ns	20-pF load, drive_sel<1:0> = 0b00, slow = 0
SID672A	t _R or t _F (fast) _{_50_0_GPIO_ENH}	Rise time or fall time (10% to 90% of V _DDIO )	1	–	20	ns	50-pF load, drive_sel<1:0> = 0b00, slow = 0
SID673A	t _R or t _F (fast) _{_20_1_GPIO_ENH}	Rise time or fall time (10% to 90% of V _DDIO )	1	–	20	ns	20-pF load, drive_sel<1:0> = 0b01, slow = 0, guaranteed by design
SID674A	t _R or t _F (fast) _{_10_2_GPIO_ENH}	Rise time or fall time (10% to 90% of V _DDIO )	1	–	20	ns	10-pF load, drive_sel<1:0> = 0b10, slow = 0, guaranteed by design
SID675A	t _R or t _F (fast) _{_6_3_GPIO_ENH}	Rise time or fall time (10% to 90% of V _DDIO )	1	–	20	ns	6-pF load, drive_sel<1:0> = 0b11, slow = 0, guaranteed by design
SID676A	t _{F_I ² C} (slow) _{_GPIO_ENH}	Fall time (30% to 70% of V _DDIO )	20 × (V _DDD / 5.5)	–	250	ns	10-pF to 400-pF load, drive_sel<1:0> = 0b00, slow = 1, minimum R _PU = 400 Ω
SID677A	t _R or t _F (slow) _{_20_GPIO_ENH}	Rise time or fall time (10% to 90% of V _DDIO )	20 × (V _DDD / 5.5)	–	160	ns	20-pF load, drive_sel<1:0> = 0b00, slow = 1, output frequency = 1 MHz
SID678A	t _R or t _F (slow) _{_400_GPIO_ENH}	Rise time or fall time (10% to 90% of V _DDIO )	20 × (V _DDD / 5.5)	–	250	ns	400-pF load, drive_sel<1:0> = 0b00, slow = 1, output frequency = 400 kHz
SID679A	f _{IN_GPIO_ENH}	Input frequency	–	–	100	MHz
SID680A	f _{OUT_GPIO_ENH0H}	Output frequency	–	–	50	MHz	20-pF load, drive_sel<1:0>= 0b00, 4.5 V ≤ V _DDD ≤ 5.5 V
SID681A	f _{OUT_GPIO_ENH0L}	Output frequency	–	–	32	MHz	20-pF load, drive_sel<1:0>= 0b00, 2.7 V ≤ V _DDD < 4.5 V
SID682A	f _{OUT_GPIO_ENH1H}	Output frequency	–	–	25	MHz	20-pF load, drive_sel<1:0>= 0b01, 4.5 V ≤ V _DDD ≤ 5.5 V
SID683A	f _{OUT_GPIO_ENH1L}	Output frequency	–	–	15	MHz	20-pF load, drive_sel<1:0>= 0b01, 2.7 V ≤ V _DDD < 4.5 V
SID684A	f _{OUT_GPIO_ENH2H}	Output frequency	–	–	25	MHz	10-pF load, drive_sel<1:0>= 0b10, 4.5 V ≤ V _DDD ≤ 5.5 V
SID685A	f _{OUT_GPIO_ENH2L}	Output frequency	–	–	15	MHz	10-pF load, drive_sel<1:0>= 0b10, 2.7 V ≤ V _DDD < 4.5 V
SID686A	f _{OUT_GPIO_ENH3H}	Output frequency	–	–	15	MHz	6-pF load, drive_sel<1:0>= 0b11, 4.5 V ≤ V _DDD ≤ 5.5 V
SID687A	f _{OUT_GPIO_ENH3L}	Output frequency	–	–	10	MHz	6-pF load, drive_sel<1:0>= 0b11, 2.7 V ≤ V _DDD < 4.5 V
GPIO input specifications
SID98	t _FT	Analog glitch filter (pulse suppression width)	–	–	50 ⁵¹	ns	One filter per port group
SID99	t _INT	Minimum pulse width for GPIO interrupt	160	–	–	ns

Analog peripherals

All specifications are valid for –40°C ≤ T _A ≤ 125°C and for 2.7 V to 5.5 V except where noted.

SAR ADC

Figure 18.
ADC characteristics and error definitions

Table 33.
12-Bit SAR ADC DC specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID100	A_RES	SAR ADC resolution	–	–	12	bits
SID101	A_V _INS	Input voltage range	V _REFL	–	V _REFH	V
SID102	A_V _REFH	V _REFH voltage range	2.7	–	V _DDA	V	ADC performance degrades when high reference is higher than supply
SID102A	A_V _DDA ⁵²	V _DDA voltage range	2.7	–	5.5	V
SID103	A_V _REFL	V _REFL voltage range	V _SSA	–	V _SSA	V	ADC performance degrades when low reference is lower than ground
SID103A	V _{band_gap}	Internal band gap reference voltage	0.882	0.9	0.918	V
SID19A	CLAMP_COUPLING_RATIO_POS	Ratio of current collected on a pin to the positive current injected into a neighboring pin	–	–	0.25	%
SID19B	CLAMP_COUPLING_RATIO_NEG	Ratio of current collected on a pin to the negative current injected into a neighboring pin	–	–	1.2	%
SID19C	R _{CLAMP_INTERNAL}	Internal pin resistance to current collection point	–	–	50	Ω

Calculating the impact of neighboring pins

The three ADC specifications based on SID19A, SID19B, and SID19C, can be used to calculate the pin leakage and resulting ADC offset caused by injection current using the below formula:

I _LEAK = I _INJECTED × CLAMP_COUPLING_RATIO

V _ERROR = I _LEAK × (R _{CLAMP_INTERNAL} + R _SOURCE )

Code Error = V _ERROR × 2 ¹² / V _REF

Where:

I _INJECTED is the injected current in mA.

I _LEAK is the calculated leakage current in mA.

V _ERROR is the voltage error calculated due to leakage currents in V.

V _REF is the ADC reference voltage in V.

Figure 19.
Integral and differential linearity errors

Figure 20.
ADC equivalent circuit for analog input

Table 34.
SAR ADC AC specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID104	V _ZT	Zero transition voltage	–20	–	20	mV	V _DDA = 2.7 V to 5.5 V, –40°C ≤ T _A ≤ 125°C before offset adjustment
SID105	V _FST	Full-scale transition voltage	–20	–	20	mV	V _DDA = 2.7 V to 5.5 V, –40°C ≤ T _A ≤ 125°C before offset adjustment
SID114	f _{ADC_4P5}	ADC operating frequency	2	–	26.67	MHz	4.5 V ≤ V _DDA ≤ 5.5 V
SID114A	f _{ADC_2P7}	ADC operating frequency	2	–	13.34	MHz	2.7 V ≤ V _DDA < 4.5 V
SID113	t _{S_4P5}	Analog input sample time for channels of own SARMUX	412	–	–	ns	4.5 V ≤ V _DDA ≤ 5.5 V Guaranteed by design
SID113A	t _{S_2P7}	Analog input sample time for channels of own SARMUX	600	–	–	ns	2.7 V ≤ V _DDA < 4.5 V Guaranteed by design
SID113B	t _{S_DR_4P5}	Analog input sample time when input is from diagnostic reference	2	–	–	µs	4.5 V ≤ V _DDA ≤ 5.5 V Guaranteed by design
SID113C	t _{S_DR_2P7}	Analog input sample time when input is from diagnostic reference	2.5	–	–	µs	2.7 V ≤ V _DDA < 4.5 V Guaranteed by design
SID113D	t _{S_TS}	Analog input sample time for temperature sensor	3	–	–	µs	2.7 V ≤ V _DDA ≤ 5.5 V Guaranteed by design
SID113E	t _{S_4P5_A}	Analog input sample time for channels of another SARMUXn (n=1,2)	824	–	–	ns	4.5 V ≤ V _DDA ≤ 5.5 V When ADC0 borrows the SARMUX of another ADC, guaranteed by design
SID113F	t _{S_2P7_A}	Analog input sample time for channels of another SARMUXn (n=1,2)	1648	–	–	ns	2.7V ≤ V _DDA ≤ 4.5 V When ADC0 borrows the SARMUX of another ADC, guaranteed by design
SID106	t _{ST_4P5}	ADC max throughput (samples per second) when using the SARMUX of own ADC	–	–	1	Msps	4.5 V ≤ V _DDA ≤ 5.5 V, 80 MHz/3 = 26.67 MHz, 11 sampling cycles, 15 conversion cycles
SID106A	t _{ST_2P7}	ADC max throughput (samples per second) when using the SARMUX of own ADC	–	–	0.5	Msps	2.7 V ≤ V _DDA < 4.5 V 80 MHz/6 = 13.3 MHz, 11 sampling cycles, 15 conversion cycles
SID106B	t _{ST_4P5_A}	ADC0 max throughput (samples per second) when borrowing the SARMUXn of another ADC (n=1,2)	–	–	0.5	Msps	4.5 V ≤ V _DDA ≤ 5.5 V, 80 MHz/6 = 13.3 MHz, 11 sampling cycles, 15 conversion cycles
SID106C	t _{ST_2P7_A}	ADC0 max throughput (samples per second) when borrowing the SARMUXn of another ADC (n=1,2)	–	–	0.25	Msps	2.7V ≤ VDDA < 4.5 V, 80 MHz/12 = 6.67 MHz, 11 sampling cycles, 15 conversion cycles
SID107	C _VIN	ADC input sampling capacitance	–	–	4.8	pF	Guaranteed by design
SID108	R _VIN1	Input path ON resistance (4.5 V to 5.5 V)	–	–	9.4	kΩ	Guaranteed by design
SID108A	R _VIN2	Input path ON resistance (2.7 V to 4.5 V)	–	–	13.9	kΩ	Guaranteed by design
SID108B	R _DREF1	Diagnostic path ON resistance (4.5 V to 5.5 V)	–	–	40	kΩ	Guaranteed by design
SID108C	R _DREF2	Diagnostic path ON resistance (2.7 V to 4.5 V)	–	–	50	kΩ	Guaranteed by design
SID119	ACC_RLAD	Diagnostic reference resistor ladder accuracy	–4	–	4	%
SID109	A_TE	Total error	–5	–	5	LSb	VDDA = V _REF H = 2.7 V to 5.5 V, V _REF L = V _SSA –40°C ≤ T _A ≤ 125°C Total error after offset and gain adjustment at 12 bit resolution mode
SID109A	A_TEB	Total error	–12	–	12	LSb	VDDA = V _REF H = 2.7 V to 5.5 V, V _REF L = V _SSA –40°C ≤ T _A ≤ 125°C Total error before offset and gain adjustment at 12 bit resolution mode
SID110	A_INL	Integral nonlinearity	–2.5	–	2.5	LSb	V _DDA = 2.7 V to 5.5 V, –40°C ≤ T _A ≤ 125°C
SID111	A_DNL	Differential nonlinearity	–0.99	–	1.9	LSb	V _DDA = 2.7 V to 5.5 V, –40°C ≤ T _A ≤ 125°C
SID112	A_CE	Channel-to-channel variation (for channels connected to same ADC)	–1	–	1	LSb	V _DDA = 2.7 V to 5.5 V, –40°C ≤ T _A ≤ 125°C
SID115	I _AIC	Analog input leakage current	–350	70	350	nA	When input pad is selected for conversion
SID116	I _DIAGREF	Diagnostic reference current	–	–	70	µA
SID117	I _VDDA	Analog power supply current while ADC is operating	–	360	550	µA	Per enabled ADC
SID117A	I _{VDDA_DS}	Analog power supply current while ADC is not operating	–	–	21	µA	Per enabled ADC
SID118	I _{V _REF}	Analog reference voltage current while ADC is operating	–	360	550	µA	Per enabled ADC
SID118A	I _{V _REF _LEAK}	Analog reference voltage current while ADC is not operating	–	1.8	5	µA	Per enabled ADC

Temperature sensor

Table 35.
Temperature sensor specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID201	TSENSACC2	Temperature sensor accuracy 2	–5	–	5	°C	–40°C ≤ T _J ≤ 150°C This spec is valid when using ADC[0] (V _{DDIO_1} ), ADC[1] (V _{DDIO_2} ) or ADC[2] (V _DDD ) with the following conditions: a. 3.0 V ≤ V _DDD , V _{DDIO_1} or V _{DDIO_2} = V _DDA = V _REFH ≤ 3.6 V or b. 4.5 V ≤ V _DDD , V _{DDIO_1} or V _{DDIO_2} = V _DDA = V _REFH ≤ 5.5 V
SID201A	TSENSACC3	Temperature sensor accuracy 3	–10	–	10	°C	–40°C ≤ T _J ≤ 150°C This spec is valid when using ADC[0] (V _{DDIO_1} ) or ADC[2] (V _DDD ) with the following condition: 2.7 V ≤ V _DDD or V _{DDIO_1} ≤ 5.5 V and 2.7 V ≤ V _DDA = V _REFH ≤ 5.5 V and 0.8 × V _DDA < V _DDD or V _{DDIO_1}

Voltage divider accuracy

Table 36.
Voltage divider accuracy
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID202	V _MONDIV	Uncorrected monitor voltage divider accuracy (measured by ADC), compared to ideal supply/2	–20	2	20	%	Any HV supply pad within 2.7-V–5.5-V operating range

AC specifications

Unless otherwise noted, the timings are defined with the guidelines mentioned in the Figure 21 .

Digital peripherals

All specifications are valid for –40°C ≤ T _A ≤ 125°C and for 2.7 V to 5.5 V except where noted.

Table 37.
Timer/counter/PWM (TCPWM) specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID120	f _C	TCPWM operating frequency	–	–	100	MHz	f _C = peripheral clock
SID121	t _PWMENEXT	Input trigger pulse width for all trigger events	2/f _C	–	–	ns	Trigger Events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
SID122	t _PWMEXT	Output trigger pulse widths	2/f _C	–	–	ns	Minimum possible width of Overflow, Underflow, and Counter = Compare (CC) value trigger outputs
SID123	t _CRES	Resolution of counter	1/f _C	–	–	ns	Minimum time between successive counts
SID124	t _PWMRES	PWM resolution	1/f _C	–	–	ns	Minimum pulse width of PWM output
SID125	t _QRES	Quadrature inputs resolution	2/f _C	–	–	ns	Minimum pulse width between Quadrature phase inputs.

Table 38.
Serial communication block (SCB) specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID129	f _SCB	SCB operating frequency	–	–	100	MHz
I ² C Interface-Standard-mode
SID130	f _SCL	SCL clock frequency	–	–	100	kHz
SID131	t _HD;STA	Hold time, START condition	4000	–	–	ns
SID132	t _LOW	Low period of SCL	4700	–	–	ns
SID133	t _HIGH	High period of SCL	4000	–	–	ns
SID134	t _SU;STA	Setup time for a repeated START	4700	–	–	ns
SID135	t _HD;DAT	Data hold time, for receiver	0	–	–	ns
SID136	t _SU;DAT	Data setup time	250	–	–	ns
SID138	t _F	Fall time of SCL and SDA	–	–	300	ns	Input and output
SID139	t _SU;STO	Setup time for STOP	4000	–	–	ns
SID140	t _BUF	Bus-free time between START and STOP	4700	–	–	ns
SID141	C _B	Capacitive load for each bus line	–	–	400	pF
SID142	t _VD;DAT	Time for data signal from SCL LOW to SDA output	–	–	3450	ns
SID143	t _VD;ACK	Data valid acknowledge time	–	–	3450	ns
SID144	V _OL	LOW level output voltage	0	–	0.4	V	Open-drain at 3 mA sink current
SID145	I _OL	LOW level output current	3	–	–	mA	V _OL = 0.4 V
I ² C Interface-Fast-mode
SID150	f _{SCL_F}	SCL clock frequency	–	–	400	kHz
SID151	t _{HD;STA_F}	Hold time, START condition	600	–	–	ns
SID152	t _{LOW_F}	Low period of SCL	1300	–	–	ns
SID153	t _{HIGH_F}	High period of SCL	600	–	–	ns
SID154	t _{SU;STA_F}	Setup time for a repeated START	600	–	–	ns
SID155	t _{HD;DAT_F}	Data hold time, for receiver	0	–	–	ns
SID156	t _{SU;DAT_F}	Data setup time	100	–	–	ns
SID158	t _{F_F}	Fall time of SCL and SDA	20 × (V _DDD / 5.5)	–	300	ns	Input and output, GPIO_ENH: slow mode, 400 pF load
SID158A	t _{FA_F}	Fall time of SCL and SDA	0.35	–	300	ns	Input and output GPIO_STD: drive_sel<1:0>= 0b00 MIN: 10 pF load, RPU = 35.41 kΩ MAX: 400 pF load, RPU = 350 Ω
SID159	t _{SU;STO_F}	Setup time for STOP	600	–	–	ns	Input and output
SID160	t _{BUF_F}	Bus free time between START and STOP	1300	–	–	ns
SID161	C _{B_F}	Capacitive load for each bus line	–	–	400	pF
SID162	t _{VD;DAT_F}	Time for data signal from SCL LOW to SDA output	–	–	900	ns
SID163	t _{VD;ACK_F}	Data valid acknowledge time	–	–	900	ns
SID164	t _{SP_F}	Pulse width of spikes that must be suppressed by the input filter	–	–	50	ns
SID165	V _{OL_F}	LOW level output voltage	0	–	0.4	V	Open-drain at 3 mA sink current
SID165	I _{OL_F}	LOW level output current	3	–	–	mA	V _OL = 0.4 V
SID167	I _{OL2_F}	LOW level output current	6	–	–	mA	V _OL = 0.6 V ⁵³
I ² C Interface-Fast-Plus mode
SID170	f _{SCL_FP}	SCL clock frequency	–	–	1	MHz
SID171	t _{HD;STA_FP}	Hold time, START condition	260	–	–	ns
SID172	t _{LOW_FP}	Low period of SCL	500	–	–	ns
SID173	t _{HIGH_FP}	High period of SCL	260	–	–	ns
SID174	t _{SU;STA_FP}	Setup time for a repeated START	260	–	–	ns
SID175	t _{HD;DAT_FP}	Data hold time, for receiver	0	–	–	ns
SID176	t _{SU;DAT_FP}	Data setup time	50	–	–	ns
SID178	t _{F_FP}	Fall time of SCL and SDA	20 × (V _DDD /5.5)	–	160	ns	Input and output 20-pF load GPIO_ENH: slow mode
SID179	t _{SU;STO_FP}	Setup time for STOP	260	–	–	ns	Input and output
SID180	t _{BUF_FP}	Bus free time between START and STOP	500	–	–	ns
SID181	C _{B_FP}	Capacitive load for each bus line	–	–	20	pF
SID182	t _{VD;DAT_FP}	Time for data signal from SCL LOW to SDA output	–	–	450	ns
SID183	t _{VD;ACK_FP}	Data valid acknowledge time	–	–	450	ns
SID184	t _{SP_FP}	Pulse width of spikes that must be suppressed by the input filter	–	–	50	ns
SID186	V _{OL_FP}	LOW level output voltage	0	–	0.4	V	Open-drain at 3 mA sink current
SID187	I _{OL_FP}	LOW level output current	3	–	–	mA	V _OL = 0.4 V ⁵⁴
SPI Interface Master (Full-clock mode: LATE_MISO_SAMPLE = 1) [Conditions: drive_sel<1:0>= 0x]
SID190	f _SPI	SPI operating frequency	–	–	12.5	MHz	Do not use half-clock mode: LATE_MISO_SAMPLE = 0
SID191	t _DMO	SPI Master: MOSI valid after SCLK driving edge	–	–	15	ns
SID192	t _DSI	SPI Master: MISO valid before SCLK capturing edge	40	–	–	ns
SID193	t _HMO	SPI Master: Previous MOSI data hold time	0	–	–	ns
SID194	t _{W_SCLK_H_L}	SPI SCLK pulse width HIGH or LOW	0.4 × (1/f _SPI )	0.5 × (1/f _SPI )	0.6 × (1/f _SPI )	ns
SID196	t _DHI	SPI Master: MISO hold time after SCLK capturing edge	0	–	–	ns
SID198	t _{EN_SETUP}	SSEL valid, before the first SCK capturing edge	0.5 × (1/f _SPI )	–	–	ns	Min is half clock period
SID199	t _{EN_SHOLD}	SSEL hold, after the last SCK capturing edge	0.5 × (1/f _SPI )	–	–	ns	Min is half clock period
SID195	C _{SPIM_MS}	SPI capacitive load	–	–	10	pF
SPI Interface Slave (internally clocked) [Conditions: drive_sel<1:0>= 0x]
SID205	f _{SPI_INT}	SPI operating frequency	–	–	10	MHz
SID206	t _{DMI_INT}	SPI Slave: MOSI Valid before Sclock capturing edge	5	–	–	ns
SID207	t _{DSO_INT}	SPI Slave: MISO Valid after Sclock driving edge, in the internal-clocked mode	–	–	62	ns
SID208	t _HSP	SPI Slave: Previous MISO data hold time	3	–	–	ns
SID209	t _{EN_SETUP_INT}	SPI Slave: SSEL valid to first SCK valid edge	33	–	–	ns
SID210	t _{EN_HOLD_INT}	SPI Slave Select active (LOW) from last SCLK hold	33	–	–	ns
SID211	t _{EN_SETUP_PRE}	SPI Slave: from SSEL valid, to SCK falling edge before the first data bit	20	–	–	ns
SID212	t _{EN_HOLD_PRE}	SPI Slave: from SCK falling edge before the first data bit, to SSEL invalid	20	–	–	ns
SID213	t _{EN_SETUP_CO}	SPI Slave: from SSEL valid, to SCK falling edge in the first data bit	20	–	–	ns
SID214	t _{EN_HOLD_CO}	SPI Slave: from SCK falling edge in the first data bit, to SSEL invalid	20	–	–	ns
SID215	t _{W_DIS_INT}	SPI Slave Select inactive time	40	–	–	ns
SID216	t _{W_SCLKH_INT}	SPI SCLK pulse width HIGH	20	–	–	ns
SID217	t _{W_SCLKL_INT}	SPI SCLK pulse width LOW	20	–	–	ns
SID218	t _{SIH_INT}	SPI MOSI hold from SCLK	12	–	–	ns
SID219	C _{SPIS_INT}	SPI capacitive load	–	–	10	pF
SPI Interface Slave (externally clocked) [Conditions: drive_sel<1:0>= 0x]
SID220	f _{SPI_EXT}	SPI operating frequency	–	–	12.5	MHz
SID221	t _{DMI_EXT}	SPI Slave: MOSI Valid before Sclock capturing edge	5	–	–	ns
SID222	t _{DSO_EXT}	SPI Slave: MISO Valid after Sclock driving edge, in the external-clocked mode	–	–	32	ns
SID223	t _{HSO_EXT}	SPI Slave: Previous MISO data hold time	3	–	–	ns
SID224	t _{EN_SETUP_EXT}	SPI Slave: SSEL valid to first SCK valid edge	40	–	–	ns
SID225	t _{EN_HOLD_EXT}	SPI Slave Select active (LOW) from last SCLK hold	40	–	–	ns
SID226	t _{W_DIS_EXT}	SPI Slave Select inactive time	80	–	–	ns
SID227	t _{W_SCLKH_EXT}	SPI SCLK pulse width HIGH	34	–	–	ns
SID228	t _{W_SCLKL_EXT}	SPI SCLK pulse width LOW	34	–	–	ns
SID229	t _{SIH_EXT}	SPI MOSI hold from SCLK	20	–	–	ns
SID230	C _{SPIS_EXT}	SPI capacitive load	–	–	10	pF
SID231	t _{VSS_EXT}	SPI Slave: MISO valid after SSEL falling edge (CPHA = 0)	–	–	33	ns
UART Interface
SID240	f _BPS	Data rate	–	–	10	Mbps

Figure 24.
SPI master timing diagrams with LOW clock phase

Figure 25.
SPI master timing diagrams with HIGH clock phase

Figure 26.
SPI slave timing diagrams with LOW clock phase

Figure 27.
SPI slave timing diagrams with HIGH clock phase

LIN specifications

Table 39.
LIN specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID249	f _LIN	Internal clock frequency to the LIN block	–	–	100	MHz
SID250	BR_NOM	Bit rate on the LIN bus	1	–	20	kbps	Guaranteed by design
SID250A	BR_REF	Bit rate on the LIN bus (not in standard LIN specification) for re-flashing in LIN slave mode	1	–	115.2	kbps	Guaranteed by design

CAN FD specifications

Table 40.
CAN FD specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID630	f _HCLK	System clock frequency	–	–	100	MHz	f _cclk ≤ f _hclk, Guaranteed by design
SID631	f _CCLK	CAN clock frequency	–	–	100	MHz	f _cclk ≤ f _hclk, Guaranteed by design

Memory

All specifications are valid for –40°C ≤ T _A ≤ 125°C and for 2.7 V to 5.5 V except where noted.

Table 41.
Flash DC specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID260	V _PE	Erase and program voltage	2.7	–	5.5	V

Table 42.
Flash AC specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID257	f _FO	Maximum flash memory operation frequency	–	–	100	MHz	Zero wait access to code-flash memory up to 100 MHz Zero wait access with cache hit up to 160 MHz
SID254	t _{ERS_SUS}	Maximum time from erase suspend command till erase is indeed suspend	–	–	37.5	µs
SID255	t _{ERS_RES_SUS}	Minimum time allowed from erase resume to erase suspend	250	–	–	µs	Guaranteed by design
SID258	t _{BC_WF}	Blank check time for N-bytes of work-flash	–	–	10 + 0.3 × N	µs	At 100 MHz, N ≥ 4 and multiple of 4, excludes system overhead time
SID259	t _SECTORERASE1	Sector erase time (Code-flash: 32 KB)	–	45	90	ms	Includes internal preprogramming time
SID259A	t _SECTORERASE2	Sector erase time (Code-flash: 8 KB)	–	15	30	ms	Includes internal preprogramming time
SID261	t _SECTORERASE3	Sector erase time (Work-flash, 2 KB)	–	80	160	ms	Includes internal preprogramming time
SID262	t _SECTORERASE4	Sector erase time (Work-flash, 128 bytes)	–	5	15	ms	Includes internal preprogramming time
SID263	t _WRITE1	64-bit write time (Code-flash)	–	30	60	µs	Excludes system overhead time
SID264	t _WRITE2	256-bit write time (Code-flash)	–	40	70	µs	Excludes system overhead time
SID265	t _WRITE3	4096-bit write time (Code-flash) ⁵⁵	–	320	1200	µs	Excludes system overhead time
SID266	t _WRITE4	32-bit write time (Work-flash)	–	30	60	µs	Excludes system overhead time
SID267	t _FRET1	Code-flash retention. 1000 program/erase cycles	20	–	–	years	T _A (power on and off) ≤ 85°C average
SID268	t _FRET3	Work-flash retention. 125,000 program/erase cycles	20	–	–	years	T _A (power on and off) ≤ 85°C average
SID269	t _FRET4	Work-flash retention. 250,000 program/erase cycles	10	–	–	years	T _A (power on and off) ≤ 85°C average
SID612	I _{CC_ACT2}	Program operating current (Code or Work-flash)	–	15	48	mA	V _DDD = 5 V Guaranteed by design
SID613	I _{CC_ACT3}	Erase operating current (Code or Work-flash)	–	15	48	mA	V _DDD = 5 V Guaranteed by design

System resources

All specifications are valid for –40°C ≤ T _A ≤ 125°C and for 2.7 V to 5.5 V except where noted.

Table 43.
System resources
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
Power-on-reset specifications
SID270	V _{POR_R}	V _DDD rising voltage to deassert POR	1.5	–	2.35	V	Guaranteed by design
SID276	V _{POR_F}	V _DDD falling voltage to assert POR	1.45	–	2.1	V
SID271	V _{POR_H}	Level detection hysteresis	20	–	300	mV	Guaranteed by design
SID272	t _{DLY_POR}	Delay between V _DDD rising through 2.3 V and an internal deassertion of POR	–	–	3	µs	Guaranteed by design
SID273	t _POFF	V _DDD Power off time	100	–	–	µs	V _DDD < 1.45 V
SID274	POR_RR1	V _DDD power ramp rate with robust BOD (BOD operation is guaranteed)	–	–	100	mV/µs	This ramp supports robust BOD
SID275	POR_RR2	V _DDD power ramp rate without robust BOD	–	–	1000	mV/µs	This ramp does not support robust BOD t _POFF must be satisfied
High-voltage BOD (HV BOD) specifications
SID500	V _{TR_2P7_R}	HV BOD 2.7 V rising detection point for V _DDD and V _DDA (default)	2.474	2.55	2.627	V
SID501	V _{TR_2P7_F}	HV BOD 2.7 V falling detection point for V _DDD and V _DDA (default)	2.449	2.525	2.601	V
SID502	V _{TR_3P0_R}	HV BOD 3.0 V rising detection point for V _DDD and V _DDA	2.765	2.85	2.936	V
SID503	V _{TR_3P0_F}	HV BOD 3.0 V falling detection point for V _DDD and V _DDA	2.74	2.825	2.91	V
SID505	HVBOD_RR_A	Power ramp rate: V _DDD and V _DDA (Active)	–	–	100	mV/µs
SID506	HVBOD_RR_DS	Power ramp rate: V _DDD and V _DDA (DeepSleep)	–	–	10	mV/µs
SID507	t _{DLY_ACT_HVBOD}	Active mode delay between V _DDD falling/rising through V _{TR_2P7_F/R} or V _{TR_3P0_F/R} and an internal HV BOD signal transitioning	–	–	0.5	µs	Guaranteed by design
SID507A	t _{DLY_ACT_HVBOD}	Active mode delay between V _DDA falling/rising through V _{TR_2P7_F/R} or V _{TR_3P0_F/R} and internal HV BOD signal transitioning	–	–	1	µs	Guaranteed by design
SID507B	t _{DLY_DS_HVBOD}	DeepSleep mode delay between V _DDD /V _DDA falling/rising through V _{TR_2P7_F/R} or V _{TR_3P0_F/R} and an internal HV BOD signal transitioning	–	–	4	µs	Guaranteed by design
SID508	t _{RES_HVBOD}	Response time of HV BOD, V _DDD /V _DDA supply. (For falling-then-rising supply at max ramp rate; threshold is V _{TR_2P7_F} or V _{TR_3P0_F} .)	100	–	–	ns	Guaranteed by design
Low-voltage BOD (LV BOD) specifications
SID510	V _{TR_R_LVBOD}	LV BOD rising detection point for V _CCD	0.917	0.945	0.973	V
SID511	V _{TR_F_LVBOD}	LV BOD falling detection point for V _CCD	0.892	0.92	0.948	V
SID515	t _{DLY_ACT_LVBOD}	Active delay between V _CCD falling/rising through V _{TR_R/F_LVBOD} and an internal LV BOD signal transitioning	–	–	1	µs	Guaranteed by design
SID515A	t _{DLY_DS_LVBOD}	DeepSleep mode delay between V _CCD falling/rising through V _{TR_R/F_LVBOD} and an internal LV BOD signal transitioning	–	–	12	µs	Guaranteed by design
SID516	t _{RES_LVBOD}	Response time of LV BOD. (For falling-then-rising supply at max ramp rate; threshold is V _{TR_F_LVBOD} .)	100	–	–	ns	Guaranteed by design
Low-voltage detector (LVD) DC specifications
SID520	V _{TR_2P8_F}	LVD 2.8 V falling detection point for V _DDD	Typ – 4%	2800	Typ + 4%	mV
SID521	V _{TR_2P9_F}	LVD 2.9 V falling detection point for V _DDD	Typ – 4%	2900	Typ + 4%	mV
SID522	V _{TR_3P0_F}	LVD 3.0 V falling detection point for V _DDD	Typ – 4%	3000	Typ + 4%	mV
SID523	V _{TR_3P1_F}	LVD 3.1 V falling detection point for V _DDD	Typ – 4%	3100	Typ + 4%	mV
SID524	V _{TR_3P2_F}	LVD 3.2 V falling detection point for V _DDD	Typ – 4%	3200	Typ + 4%	mV
SID525	V _{TR_3P3_F}	LVD 3.3 V falling detection point for V _DDD	Typ – 4%	3300	Typ + 4%	mV
SID526	V _{TR_3P4_F}	LVD 3.4 V falling detection point for V _DDD	Typ – 4%	3400	Typ + 4%	mV
SID527	V _{TR_3P5_F}	LVD 3.5 V falling detection point for V _DDD	Typ – 4%	3500	Typ + 4%	mV
SID528	V _{TR_3P6_F}	LVD 3.6 V falling detection point for V _DDD	Typ – 4%	3600	Typ + 4%	mV
SID529	V _{TR_3P7_F}	LVD 3.7 V falling detection point for V _DDD	Typ – 4%	3700	Typ + 4%	mV
SID530	V _{TR_3P8_F}	LVD 3.8 V falling detection point for V _DDD	Typ – 4%	3800	Typ + 4%	mV
SID531	V _{TR_3P9_F}	LVD 3.9 V falling detection point for V _DDD	Typ – 4%	3900	Typ + 4%	mV
SID532	V _{TR_4P0_F}	LVD 4.0 V falling detection point for V _DDD	Typ – 4%	4000	Typ + 4%	mV
SID533	V _{TR_4P1_F}	LVD 4.1 V falling detection point for V _DDD	Typ – 4%	4100	Typ + 4%	mV
SID534	V _{TR_4P2_F}	LVD 4.2 V falling detection point for V _DDD	Typ – 4%	4200	Typ + 4%	mV
SID535	V _{TR_4P3_F}	LVD 4.3 V falling detection point for V _DDD	Typ – 4%	4300	Typ + 4%	mV
SID536	V _{TR_4P4_F}	LVD 4.4 V falling detection point for V _DDD	Typ – 4%	4400	Typ + 4%	mV
SID537	V _{TR_4P5_F}	LVD 4.5 V falling detection point for V _DDD	Typ – 4%	4500	Typ + 4%	mV
SID538	V _{TR_4P6_F}	LVD 4.6 V falling detection point for V _DDD	Typ – 4%	4600	Typ + 4%	mV
SID539	V _{TR_4P7_F}	LVD 4.7 V falling detection point for V _DDD	Typ – 4%	4700	Typ + 4%	mV
SID540	V _{TR_4P8_F}	LVD 4.8 V falling detection point for V _DDD	Typ – 4%	4800	Typ + 4%	mV
SID541	V _{TR_4P9_F}	LVD 4.9 V falling detection point for V _DDD	Typ – 4%	4900	Typ + 4%	mV
SID542	V _{TR_5P0_F}	LVD 5.0 V falling detection point for V _DDD	Typ – 4%	5000	Typ + 4%	mV
SID543	V _{TR_5P1_F}	LVD 5.1 V falling detection point for V _DDD	Typ – 4%	5100	Typ + 4%	mV
SID544	V _{TR_5P2_F}	LVD 5.2 V falling detection point for V _DDD	Typ – 4%	5200	Typ + 4%	mV
SID545	V _{TR_5P3_F}	LVD 5.3 V falling detection point for V _DDD	Typ – 4%	5300	Typ + 4%	mV
SID546	V _{TR_2P8_R}	LVD 2.8 V rising detection point for V _DDD	Typ – 4%	2825	Typ + 4%	mV	Same as V _{TR_2P8_F} + 25 mV
SID547	V _{TR_2P9_R}	LVD 2.9 V rising detection point for V _DDD	Typ – 4%	2925	Typ + 4%	mV	Same as V _{TR_2P9_F} + 25 mV
SID548	V _{TR_3P0_R}	LVD 3.0 V rising detection point for V _DDD	Typ – 4%	3025	Typ + 4%	mV	Same as V _{TR_3P0_F} + 25 mV
SID549	V _{TR_3P1_R}	LVD 3.1 V rising detection point for V _DDD	Typ – 4%	3125	Typ + 4%	mV	Same as V _{TR_3P1_F} + 25 mV
SID550	V _{TR_3P2_R}	LVD 3.2 V rising detection point for V _DDD	Typ – 4%	3225	Typ + 4%	mV	Same as V _{TR_3P2_F} + 25 mV
SID551	V _{TR_3P3_R}	LVD 3.3 V rising detection point for V _DDD	Typ – 4%	3325	Typ + 4%	mV	Same as V _{TR_3P3_F} + 25 mV
SID552	V _{TR_3P4_R}	LVD 3.4 V rising detection point for V _DDD	Typ – 4%	3425	Typ + 4%	mV	Same as V _{TR_3P4_F} + 25 mV
SID553	V _{TR_3P5_R}	LVD 3.5 V rising detection point for V _DDD	Typ – 4%	3525	Typ + 4%	mV	Same as V _{TR_3P5_F} + 25 mV
SID554	V _{TR_3P6_R}	LVD 3.6 V rising detection point for V _DDD	Typ – 4%	3625	Typ + 4%	mV	Same as V _{TR_3P6_F} + 25 mV
SID555	V _{TR_3P7_R}	LVD 3.7 V rising detection point for V _DDD	Typ – 4%	3725	Typ + 4%	mV	Same as V _{TR_3P7_F} + 25 mV
SID556	V _{TR_3P8_R}	LVD 3.8 V rising detection point for V _DDD	Typ – 4%	3825	Typ + 4%	mV	Same as V _{TR_3P8_F} + 25 mV
SID557	V _{TR_3P9_R}	LVD 3.9 V rising detection point for V _DDD	Typ – 4%	3925	Typ + 4%	mV	Same as V _{TR_3P9_F} + 25 mV
SID558	V _{TR_4P0_R}	LVD 4.0 V rising detection point for V _DDD	Typ – 4%	4025	Typ + 4%	mV	Same as V _{TR_4P0_F} + 25 mV
SID559	V _{TR_4P1_R}	LVD 4.1 V rising detection point for V _DDD	Typ – 4%	4125	Typ + 4%	mV	Same as V _{TR_4P1_F} + 25 mV
SID560	V _{TR_4P2_R}	LVD 4.2 V rising detection point for V _DDD	Typ – 4%	4225	Typ + 4%	mV	Same as V _{TR_4P2_F} + 25 mV
SID561	V _{TR_4P3_R}	LVD 4.3 V rising detection point for V _DDD	Typ – 4%	4325	Typ + 4%	mV	Same as V _{TR_4P3_F} + 25 mV
SID562	V _{TR_4P4_R}	LVD 4.4 V rising detection point for V _DDD	Typ – 4%	4425	Typ + 4%	mV	Same as V _{TR_4P4_F} + 25 mV
SID563	V _{TR_4P5_R}	LVD 4.5 V rising detection point for V _DDD	Typ – 4%	4525	Typ + 4%	mV	Same as V _{TR_4P5_F} + 25 mV
SID564	V _{TR_4P6_R}	LVD 4.6 V rising detection point for V _DDD	Typ – 4%	4625	Typ + 4%	mV	Same as V _{TR_4P6_F} + 25 mV
SID565	V _{TR_4P7_R}	LVD 4.7 V rising detection point for V _DDD	Typ – 4%	4725	Typ + 4%	mV	Same as V _{TR_4P7_F} + 25 mV
SID566	V _{TR_4P8_R}	LVD 4.8 V rising detection point for V _DDD	Typ – 4%	4825	Typ + 4%	mV	Same as V _{TR_4P8_F} + 25 mV
SID567	V _{TR_4P9_R}	LVD 4.9 V rising detection point for V _DDD	Typ – 4%	4925	Typ + 4%	mV	Same as V _{TR_4P9_F} + 25 mV
SID568	V _{TR_5P0_R}	LVD 5.0 V rising detection point for V _DDD	Typ – 4%	5025	Typ + 4%	mV	Same as V _{TR_5P0_F} + 25 mV
SID569	V _{TR_5P1_R}	LVD 5.1 V rising detection point for V _DDD	Typ – 4%	5125	Typ + 4%	mV	Same as V _{TR_5P1_F} + 25 mV
SID570	V _{TR_5P2_R}	LVD 5.2 V rising detection point for V _DDD	Typ – 4%	5225	Typ + 4%	mV	Same as V _{TR_5P2_F} + 25 mV
SID571	V _{TR_5P3_R}	LVD 5.3 V rising detection point for V _DDD	Typ – 4%	5325	Typ + 4%	mV	Same as V _{TR_5P3_F} + 25 mV
SID573	LVD_RR_A	Power ramp rate: V _DDD (Active)	–	–	100	mV/µs
SID574	LVD_RR_DS	Power ramp rate: V _DDD (DeepSleep)	–	–	10	mV/µs
SID575	t _{DLY_ACT_LVD}	Active mode delay between V _DDD falling/rising through LVD rising/falling point and an internal LVD signal transitioning	–	–	1	µs	Guaranteed by design
SID575A	t _{DLY_DS_LVD}	DeepSleep mode delay between V _DDD falling/rising through LVD rising/falling point and an internal LVD signal rising	–	–	4	µs	Guaranteed by design
SID576	t _{RES_LVD}	Response time of LVD, V _DDD supply. LVD guaranteed to generate pulse for V _DDD pulse width greater than this. (For falling-then-rising supply at max ramp rate; pulse width is time below LVD falling point)	100	–	–	ns	Guaranteed by design
High-voltage OVD (HV OVD) specifications
SID580	V _{TR_5P0_R}	HV OVD 5.0-V rising detection point for V _DDD and V _DDA	5.049	5.205	5.361	V
SID581	V _{TR_5P0_F}	HV OVD 5.0-V falling detection point for V _DDD and V _DDA	5.025	5.18	5.335	V
SID582	V _{TR_5P5_R}	HV OVD 5.5-V rising detection point for V _DDD and V _DDA (default)	5.548	5.72	5.892	V
SID583	V _{TR_5P5_F}	HV OVD 5.5-V falling detection point for V _DDD and V _DDA (default)	5.524	5.695	5.866	V
SID585	HVOVD_RR_A	Power ramp rate: V _DDD and V _DDA (Active)	–	–	100	mV/µs
SID586	HVOVD_RR_DS	Power ramp rate: V _DDD and V _DDA (DeepSleep)	–	–	10	mV/µs
SID587	t _{DLY_ACT_HVOVD}	Active mode delay between V _DDD falling/rising through V _{TR_5P0_F/R} or V _{TR_5P5_F/R} and an internal HV OVD signal transitioning	–	–	1	µs	Guaranteed by design
SID587A	t _{DLY_ACT_HVOVD_A}	Active mode delay between V _DDA falling/rising through V _{TR_5P0_F/R} or V _{TR_5P5_F/R} and an internal HV OVD signal transitioning	–	–	1.5	µs	Guaranteed by design
SID587B	t _{DLY_DS_HVOVD}	DeepSleep mode delay between V _DDD /V _DDA falling/rising through V _{TR_5P0_F/R} or V _{TR_5P5_F/R} and an internal HV OVD signal transitioning	–	–	4	µs	Guaranteed by design
SID588	t _{RES_HVOVD}	Response time of HV OVD. (For rising-then-falling supply at max ramp rate; threshold is V _{TR_5P0_R} or V _{TR_5P5_R} .)	100	–	–	ns	Guaranteed by design
Low-voltage OVD (LV OVD) specifications
SID590	V _{TR_R_LVOVD}	LV OVD rising detection point for V _CCD	1.261	1.3	1.339	V
SID591	V _{TR_F_LVOVD}	LV OVD falling detection point for V _CCD	1.237	1.275	1.313	V
SID595	t _{DLY_ACT_LVOVD}	Active mode delay between V _CCD falling/rising through V _{TR_F/R_LVOVD} and an internal LV OVD signal transitioning	–	–	1	µs	Guaranteed by design
SID595A	t _{DLY_DS_LVOVD}	DeepSleep mode delay between V _CCD falling/rising through V _{TR_F/R_LVOVD} and an internal LV OVD signal transitioning	–	–	12	µs	Guaranteed by design
SID596	t _{RES_LVOVD}	Response time of LV OVD. (For rising-then-falling supply at max ramp rate; threshold is V _{TR_R_LVOVD} .)	100	–	–	ns	Guaranteed by design
Overcurrent detection (OCD) specifications
SID598	I _OCD	OCD range for V _CCD	156	–	315	mA	Guaranteed by design
SID599	I _{OCD_DPSLP}	OCD range in DeepSleep mode	18	–	72	mA	Guaranteed by design

Figure 28.
Device operations supply range

Figure 30.
High-voltage BOD specifications

Figure 31.
Low-voltage BOD specifications

Figure 32.
High-voltage OVD specifications

Figure 33.
Low-voltage OVD specifications

Debug

All specifications are valid for –40°C ≤ T _A ≤ 125°C and for 2.7 V to 5.5 V except where noted.

SWD

Table 44.
SWD interface specifications [Conditions: drive_sel<1:0>= 00]
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID300	f _SWDCLK	SWD clock input frequency	–	–	10	MHz	2.7 V ≤ V _DDD ≤ 5.5 V
SID301	t _{SWDI_SETUP}	SWDI setup time	0.25 × T	–	–	ns	T = 1/f _SWDCLK
SID302	t _{SWDI_HOLD}	SWDI hold time	0.25 × T	–	–	ns	T = 1/f _SWDCLK
SID303	t _{SWDO_VALID}	SWDO valid time	–	–	0.5 × T	ns	T = 1/f _SWDCLK
SID304	t _{SWDO_HOLD}	SWDO hold time	1	–	–	ns	T = 1/f _SWDCLK

JTAG

Table 45.
JTAG AC specifications [Conditions: drive_sel<1:0>= 00]
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID620	t _JCKH	TCK HIGH time	30	–	–	ns	30-pF load
SID621	t _JCKL	TCK LOW time	30	–	–	ns	30-pF load
SID622	t _JCP	TCK clock period	66.7	–	–	ns	30-pF load
SID623	t _JSU	TDI/TMS setup time	12	–	–	ns	30-pF load
SID624	t _JH	TDI/TMS hold time	12	–	–	ns	30-pF load
SID625	t _JZX	TDO High-Z to active	–	–	30	ns	30-pF load
SID626	t _JXZ	TDO active to High-Z	–	–	30	ns	30-pF load
SID627	t _JCO	TDO clock to output	–	–	30	ns	30-pF load

Trace

Table 46.
Trace specifications [Conditions: drive_sel<1:0>= 00]
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID1412A	C _TRACE	Trace capacitive load	–	–	30	pF
SID1412	t _{TRACE_CYC}	Trace clock period	40	–	–	ns	Trace clock cycle time for 25 MHz
SID1413	t _{TRACE_CLKL}	Trace clock LOW pulse width	2	–	–	ns	Clock low pulse width
SID1414	t _{TRACE_CLKH}	Trace clock HIGH pulse width	2	–	–	ns	Clock high pulse width
SID1415A	t _{TRACE_SETUP}	Trace data setup time	3	–	–	ns	Trace data setup time
SID1416A	t _{TRACE_HOLD}	Trace data hold time	2	–	–	ns	Trace data hold time

Clock specifications

All specifications are valid for –40°C ≤ T _A ≤ 125°C and for 2.7 V to 5.5 V except where noted.

The following is a basic requirement on the clock frequency dependency of the cores: Cortex®-M0+ core should run at an integer divider from the Cortex®-M4F core clock.

Example combinations are listed in the Table 47 .

Table 47.
Clock requirements
Core Cortex®-M4F Clock (MHz)	Core Cortex®-CM0+ Clock (MHz)
160	80
120	60
100	100
80	80

Table 48.
Root and intermediate clocks ⁵⁶
Clock	Max Frequency (MHz)	Description
CLK_HF0	160	Root clock for CPUSS, PERI
CLK_HF1	100	Event generator (CLK_REF), Clock output on EXT_CLK pins (when used as output)
CLK_HF2	2	CSV
CLK_FAST	160	Generated by dividing CLK_HF0, intermediate clock for CM4
CLK_SLOW	100	Generated by clock gating CLK_PERI, intermediate clock for CM0+, Crypto, P-DMA, M-DMA
CLK_PERI	100	Generated by clock gating CLK_HF0, intermediate clock for LIN, SCB, PASS, CAN, TCPWM, IOSS, CPU trace

Table 49.
IMO AC specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID310	f _IMOTOL	IMO operating frequency	7.92	8	8.08	MHz
SID311	tSTARTIMO	IMO startup time			7.5	µs	Startup time to 90% of final frequency
SID312	IIMO_ACT	IMO current		13.5	22	µA	Guaranteed by design

Table 50.
ILO AC specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID320	f _ILOTRIM	ILO operating frequency	31.1296	32.768	34.4064	kHz
SID321	t _STARTILO	ILO startup time		8	12	µs	Startup time to 90% of final frequency
SID323	I _ILO	ILO current		500	2800	nA	Guaranteed by design

Table 51.
ECO specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID330	f _ECO	Crystal frequency range	3.988	–	33.34	MHz
SID332	R _FDBK	Feedback resistor value. Min: RTRIM = 3; Max: RTRIM = 0 with 100-kΩ step size on RTRIM	100	–	400	kΩ	Guaranteed by design
SID333	I _ECO3	ECO current at T _J = 150°C	–	–	2000	µA	Maximum operation current with a 33-MHz crystal, max 18-pF load
SID334	t _{START_4M}	4-MHz ECO startup time	–	–	10	ms	Time from set CLK_ECO_CONFIG.ECO_EN to 1 until CLK_ECO_STATUS.ECO_READY is set to 1 (See Clock Timing Diagrams)
SID335	t _{START_33M}	33-MHz ECO startup time ⁵⁷	–	–	1	ms	Time from set CLK_ECO_CONFIG.ECO_EN to 1 until CLK_ECO_STATUS.ECO_READY is set to 1 (See Clock Timing Diagrams)

Table 52.
PLL specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID340	PLL_LOCK	Time to achieve PLL lock	–	–	35	µs
SID341	f _{PLL_OUT}	Output frequency from PLL block	11	–	160	MHz
SID342	PLL_LJIT1	Long term jitter	–0.25	–	0.25	ns	For 125 ns f _{PLL_VCO} : 320 MHz f _{PLL_OUT} : 40 MHz to 160 MHz f _{PLL_PFD} : 8 MHz f _{PLL_IN} : ECO
SID343	PLL_LJIT2	Long term jitter	–0.5	–	0.5	ns	For 500 ns f _{PLL_VCO} : 320 MHz f _{PLL_OUT} : 40 MHz to 160 MHz f _{PLL_PFD} : 8 MHz f _{PLL_IN} : ECO
SID344	PLL_LJIT3	Long term jitter	–0.5	–	0.5	ns	For 1000 ns f _{PLL_VCO} : 320 MHz f _{PLL_OUT} : 40 MHz to 160 MHz f _{PLL_PFD} : 8 MHz f _{PLL_IN} : ECO
SID345A	PLL_LJIT5	Long term jitter	–0.75	–	0.75	ns	For 10000 ns f _{PLL_VCO} : 320 MHz f _{PLL_OUT} : 40 MHz to 160 MHz f _{PLL_PFD} : 8 MHz f _{PLL_IN} : ECO
SID346	f _{PLL_IN}	PLL input frequency	3.988	–	33.34	MHz
SID347	I _{PLL_160M1}	PLL operating current (f _OUT = 160 MHz)	–	740	1110	µA	f _IN = 4 MHz, f _PFD = 4 MHz, f _VCO = 320 MHz, f _OUT = 160 MHz
SID347A	I _{PLL_160M2}	PLL operating current (f _OUT = 160 MHz)	–	750	1125	µA	f _IN = 8 MHz, f _PFD = 8 MHz, f _VCO = 320 MHz, f _OUT = 160 MHz
SID347B	I _{PLL_160M3}	PLL operating current (f _OUT = 160 MHz)	–	750	1125	µA	f _IN = 16 MHz, f _PFD = 8 MHz, f _VCO = 320 MHz, f _OUT = 160 MHz
SID339	I _{PLL_100M1}	PLL operating current (f _OUT = 100 MHz)	–	520	780	µA	f _IN = 4 MHz, f _PFD = 4 MHz, f _VCO = 200 MHz, f _OUT = 100 MHz
SID339A	I _{PLL_100M2}	PLL operating current (f _OUT = 100 MHz)	–	530	795	µA	f _IN = 8 MHz, f _PFD = 8 MHz, f _VCO = 200 MHz, f _OUT = 100 MHz
SID339B	I _{PLL_100M3}	PLL operating current (f _OUT = 100 MHz)	–	530	795	µA	f _IN = 16 MHz, f _PFD = 8 MHz, f _VCO = 200 MHz, f _OUT = 100 MHz
SID348	I _{PLL_80M1}	PLL operating current (f _OUT = 80 MHz)	–	520	780	µA	f _IN = 4 MHz, f _PFD = 4 MHz, f _VCO = 240 MHz, f _OUT = 80 MHz
SID348A	I _{PLL_80M2}	PLL operating current (f _OUT = 80 MHz)	–	530	795	µA	f _IN = 8 MHz, f _PFD = 8 MHz, f _VCO = 240 MHz, f _OUT = 80 MHz
SID348B	I _{PLL_80M3}	PLL operating current (f _OUT = 80 MHz)	–	530	795	µA	f _IN = 16 MHz, f _PFD = 8 MHz, f _VCO = 240 MHz, f _OUT = 80 MHz
SID348C	f _{PLL_VCO}	VCO frequency	170	–	400	MHz
SID349C	f _{PLL_PFD}	PFD frequency	3.988	–	8	MHz

Table 53.
FLL specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID350	t _{FLL_WAKE}	FLL wake up time	–	–	5	µs	Wakeup with < 10°C temperature change while in DeepSleep. f _{FLL_IN} = 8 MHz, f _{FLL_OUT} = 100 MHz, Time from stable reference clock until FLL frequency is within 5% of final value
SID351	f _{FLL_OUT}	Output frequency from FLL block	24	–	100	MHz	Output range of FLL divided-by-2 output
SID352	FLL_CJIT	FLL frequency accuracy	–1	–	1	%	This is added to the error of the source
SID353	f _{FLL_IN}	Input frequency	0.25	–	80	MHz
SID354	I _FLL	FLL operating current	–	250	360	µA	Reference clock: IMO, CCO frequency: 200 MHz, FLL frequency: 100 MHz, guaranteed by design

Table 54.
WCO specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID360	f _WCO	Watch Crystal frequency	–	32.768	–	kHz	Maximum drive level: 0.5 µW
SID361	WCO_DC	WCO duty cycle	10	–	90	%
SID362	t _{START_WCO}	WCO start-up time	–	–	1000	ms	For Grade-S devices Time from set CTL.WCO_EN to 1 until STATUS.WCO_OK is set to 1. (See Clock Timing Diagrams)
SID362E	t _{START_WCOE}	WCO start-up time ⁶⁰	–	–	1400	ms	For Grade-E devices Time from set CTL.WCO_EN to 1 until STATUS.WCO_OK is set to 1. (See Clock Timing Diagrams)
SID363	I _WCO	WCO current	–	1.4	–	µA

Table 55.
External clock input specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID366	f _EXT	External clock input frequency	0.25	–	80	MHz	For EXT_CLK pin (all input level settings: CMOS, TTL, Automotive)
SID367	EXT_DC	External clock duty cycle	45	–	55	%

Clock timing diagrams

Table 56.
MCWDT timeout specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID410	t _MCWDT1	Minimum MCWDT timeout	58.12	–	–	µs	When using the ILO (32.768 kHz + 5%) and 16-bit MCWDT counter Guaranteed by design
SID411	t _MCWDT2	Maximum MCWDT timeout	–	–	2.11	s	When using the ILO (32.768 kHz – 5%) and 16-bit MCWDT counter Guaranteed by design

Table 57.
WDT timeout specifications
Spec ID	Parameter	Description	Min	Typ	Max	Unit	Details/Conditions
SID412	t _WDT1	Minimum WDT timeout	58.12	–	–	µs	When using the ILO (32.768 kHz + 5%) and 32-bit WDT counter Guaranteed by design
SID413	t _WDT2	Maximum WDT timeout	–	–	38.33	h	When using the ILO (32.768 kHz – 5%) and 32-bit WDT counter Guaranteed by design
SID414	t _WDT3	Default WDT timeout	–	1000	–	ms	When using the ILO and 32-bit WDT counter at 0x8000 (default value), guaranteed by design

Ordering information

The CYT2B7 microcontroller part numbers and features are listed in Table 58 . The Arm® TAP JTAG ID is 0x6BA0 0477.

Table 58.
CYT2B7 ordering information
Device Code	Ordering Code ⁶¹	Package	Code-flash(KB)	Work-flash(KB)	RAM (KB)	ADC Channels	SCB Channels	LIN Channels	CANFD Channels	eSHE/HSM	AUTOSAR package	Temperature Grade	JTAG ID CODE
CYT2B73BAS	CYT2B73BADQ0AZSGS	64-LQFP	1088 ⁶³	96 ⁶⁴	128	27	7	6	5	eSHE	No	S ⁶⁵	0x2E3C9069 ⁶⁶
CYT2B73BAE ⁶²	CYT2B73BADQ0AZEGS	64-LQFP	1088	96	128	27	7	6	5	eSHE	No	E ⁶⁷	0x2E3C9069
CYT2B73CAS	CYT2B73CADQ0AZSGS	64-LQFP	1088	96	128	27	7	6	5	HSM	No	S	0x2E3CA069
CYT2B73CAE	CYT2B73CADQ0AZEGS	64-LQFP	1088	96	128	27	7	6	5	HSM	No	E	0x2E3CA069
CYT2B73CXE	CYT2B73CXDQ0AZEGS	64-LQFP	1088	96	128	27	7	6	5	HSM	Yes	E	0x2E3CA069
CYT2B74BAS ⁶²	CYT2B74BADQ0AZSGS	80-LQFP	1088	96	128	34	8	7	6	eSHE	No	S	0x2E3D1069
CYT2B74BAE ⁶²	CYT2B74BADQ0AZEGS	80-LQFP	1088	96	128	34	8	7	6	eSHE	No	E	0x2E3D1069
CYT2B74CAS	CYT2B74CADQ0AZSGS	80-LQFP	1088	96	128	34	8	7	6	HSM	No	S	0x2E3D2069
CYT2B74CAE	CYT2B74CADQ0AZEGS	80-LQFP	1088	96	128	34	8	7	6	HSM	No	E	0x2E3D2069
CYT2B74CXE	CYT2B74CXDQ0AZEGS	80-LQFP	1088	96	128	34	8	7	6	HSM	Yes	E	0x2E3D2069
CYT2B75BAS ⁶²	CYT2B75BADQ0AZSGS	100-LQFP	1088	96	128	39	8	7	6	eSHE	No	S	0x2E3D9069
CYT2B75BAE ⁶²	CYT2B75BADQ0AZEGS	100-LQFP	1088	96	128	39	8	7	6	eSHE	No	E	0x2E3D9069
CYT2B75CAS	CYT2B75CADQ0AZSGS	100-LQFP	1088	96	128	39	8	7	6	HSM	No	S	0x2E3DA069
CYT2B75CAE	CYT2B75CADQ0AZEGS	100-LQFP	1088	96	128	39	8	7	6	HSM	No	E	0x2E3DA069
CYT2B75CXE	CYT2B75CXDQ0AZEGS	100-LQFP	1088	96	128	39	8	7	6	HSM	Yes	E	0x2E3DA069
CYT2B77BAS ⁶²	CYT2B77BADQ0AZSGS	144-LQFP	1088	96	128	54	8	8	6	eSHE	No	S	0x2E3E1069
CYT2B77BAE ⁶²	CYT2B77BADQ0AZEGS	144-LQFP	1088	96	128	54	8	8	6	eSHE	No	E	0x2E3E1069
CYT2B77CAS	CYT2B77CADQ0AZSGS	144-LQFP	1088	96	128	54	8	8	6	HSM	No	S	0x2E3E2069
CYT2B77CAE	CYT2B77CADQ0AZEGS	144-LQFP	1088	96	128	54	8	8	6	HSM	No	E	0x2E3E2069
CYT2B77CXE	CYT2B77CXDQ0AZEGS	144-LQFP	1088	96	128	54	8	8	6	HSM	Yes	E	0x2E3E2069
CYT2B78BAS ⁶²	CYT2B78BADQ0AZSGS	176-LQFP	1088	96	128	64	8	8	6	eSHE	No	S	0x2E3E9069
CYT2B78BAE ⁶²	CYT2B78BADQ0AZEGS	176-LQFP	1088	96	128	64	8	8	6	eSHE	No	E	0x2E3E9069
CYT2B78CAS	CYT2B78CADQ0AZSGS	176-LQFP	1088	96	128	64	8	8	6	HSM	No	S	0x2E3EA069
CYT2B78CAE	CYT2B78CADQ0AZEGS	176-LQFP	1088	96	128	64	8	8	6	HSM	No	E	0x2E3EA069
CYT2B78CXE	CYT2B78CXDQ0AZEGS	176-LQFP	1088	96	128	64	8	8	6	HSM	Yes	E	0x2E3EA069

Part number nomenclature

Table 59.
Device code nomenclature
Field	Description	Value	Meaning
CY	Cypress prefix, an Infineon company	CY
T	Category	T	TRAVEO™
2	Family name	2	TRAVEO™ T2G (Core M4)
B	Application	B	Body
D	Code-flash/Work-flash/SRAM quantity	7	1088 KB/96 KB/128 KB
P	Packages	3	64-LQFP
		4	80-LQFP
		5	100-LQFP
		7	144-LQFP
		8	176-LQFP
H	Hardware option	B	eSHE – on, HSM – off, RSA-2048
H	Hardware option	C	eSHE – on, HSM – on, RSA-2048
I	Marketing option	A	No options
I	Marketing option	X	AUTOSAR package
C	Temperature grade	S	S-grade (–40°C to 105°C)
C	Temperature grade	E	E-grade (–40°C to 125°C)

Table 60.
Ordering code nomenclature
Field	Description	Value	Meaning
CY	Cypress prefix, an Infineon company	CY
T	Category	T	TRAVEO™
2	Family name	2	TRAVEO™ T2G (Core M4)
B	Application	B	Body
D	Code-flash/Work-flash/SRAM quantity	7	1088 KB/96 KB/128 KB
P	Packages	3	64 LQFP
		4	80 LQFP
		5	100 LQFP
		7	144 LQFP
		8	176 LQFP
H	Hardware option	B	eSHE – on, HSM – off, RSA-2048
H	Hardware option	C	eSHE – on, HSM – on, RSA-2048
I	Marketing option	A	No options
I	Marketing option	X	AUTOSAR package
R	Revision	A	First revision
		B	Second revision
		C	Third revision
		D	Fourth revision
F	Fab location	Q	UMC (Fab 12i) Singapore
X	Reserved	0	Reserved
K	Package code	AZ	LQFP
C	Temperature grade	S	S-grade (–40°C to 105°C)
C	Temperature grade	E	E-grade (–40°C to 125°C)
Q	Quality grade	ES	Engineering samples
Q	Quality grade	GS	Standard grade of automotive
S	Shipment type	Blank	Tray shipment
S	Shipment type	T	Tape and Reel shipment

Packaging

CYT2B7 is offered in the packages listed in the Table 61 .

Table 61.
Package information
Package	Dimensions	Contact/Lead pitch	Coefficient of thermal expansion ⁶⁸	I/O Pins
176-LQFP	24 × 24 × 1.7 mm (max)	0.5 mm	a1 = 8.5 ppm/°C, a2 = 33.8 ppm/°C	152
144-LQFP	20 × 20 × 1.7 mm (max)	0.5 mm	a1 ⁶⁹ = 8.5 ppm/°C, a2 ⁷⁰ = 33.7 ppm/°C	122
100-LQFP	14 × 14 × 1.7 mm (max)	0.5 mm	a1 ⁶⁹ = 8.5 ppm/°C, a2 ⁷⁰ = 33.6 ppm/°C	78
80-LQFP	12 × 12 × 1.7 mm (max)	0.5 mm	a1 ⁶⁹ = 8.5 ppm/°C, a2 ⁷⁰ = 33.5 ppm/°C	63
64-LQFP	10 × 10 × 1.7 mm (max)	0.5 mm	a1 ⁶⁹ = 8.5 ppm/°C, a2 ⁷⁰ = 33.2 ppm/°C	49

Table 62.
Package characteristics
Parameter	Description	Conditions	Min	Typ	Max	Unit
T _A	Operating ambient temperature	S-grade	–40	–	105	°C
T _A	Operating ambient temperature	E-grade	–40	–	125	°C
T _J	Operating junction temperature	–	–	–	150	°C
R _θJA	Package thermal resistance, junction to ambient θ _JA ⁷¹ , ⁷²	64 LQFP	–	–	37.6	°C/Watt
		80 LQFP	–	–	32.7	°C/Watt
		100 LQFP	–	–	29.8	°C/Watt
		144 LQFP	–	–	26.2	°C/Watt
		176 LQFP	–	–	25.9	°C/Watt
R _θJB	Package thermal resistance, junction to board θ _JB	64 LQFP	–	–	32.0	°C/Watt
		80 LQFP	–	–	26.7	°C/Watt
		100 LQFP	–	–	21.3	°C/Watt
		144 LQFP	–	–	20.9	°C/Watt
		176 LQFP	–	–	20.8	°C/Watt
R _θJC	Package thermal resistance, junction to case θ _JC	64 LQFP	–	–	7.8	°C/Watt
		80 LQFP	–	–	6.6	°C/Watt
		100 LQFP	–	–	5.6	°C/Watt
		144 LQFP	–	–	4.2	°C/Watt
		176 LQFP	–	–	3.8	°C/Watt

Table 63.
Solder Reflow Peak Temperature, Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package	Maximum Peak Temperature(°C)	Maximum Time at Peak Temperature (seconds)	MSL
176 LQFP	260	30 seconds	3
144 LQFP	260	30 seconds	3
100 LQFP	260	30 seconds	3
80 LQFP	260	30 seconds	3
64 LQFP	260	30 seconds	3

Figure 40.
176-LQFP package outline (PG-LQFP-176)

Figure 41.
144-LQFP package outline (PG-LQFP-144)

Figure 42.
100-LQFP package outline (PG-LQFP-100)

Figure 43.
80-LQFP package outline (PG-LQFP-80)

Figure 44.
64-LQFP package outline (PG-LQFP-64)

Appendix

Bootloading or end-of-line programming

Triggered at device startup, if a trigger condition is applied
Either CAN or LIN communication may be used
Bootloader polls for the communication on CAN or LIN at separate time frames, until the overall 300-second timeout is reached
If a bootloader command is received on either communication interface, the polling stops and bootloader starts using this interface

Table 64.
CAN interface details
Sl. No.	CAN interface	Configuration
1	CAN Mode	Classic CAN
2	CAN Instance	CAN0, Channel#1
3	CAN TX	P0.2/CAN0_1_TX
4	CAN RX	P0.3/CAN0_1_RX
5	CAN Transceiver NSTB/EN (Low)	P23.3 (optional)
6	CAN Transceiver EN/EN (High)	P2.1 (optional)
7	CAN RX Message ID	0x1A1
8	CAN TX Message ID	0x1B1
9	Baud	100 or 500 kbps alternating

Figure 46.
MCU to CAN transceiver connections

Table 65.
LIN interface details
Sl. No.	LIN interface	Configuration
1	LIN Type	LIN0, Channel#1
2	LIN Mode	Slave
3	LIN Checksum Type	Classic
4	LIN TX	P0.1/LIN1_TX
5	LIN RX	P0.0/LIN1_RX
6	LIN EN/EN (High)	P2.1 (optional)
7	LIN EN (Low)	P23.3 (optional)
8	LIN TX PID	0x46
9	LIN RX PID	0x45
10	Baud	20 or 115.2 kbps
11	Break Field Length	11
12	Break Delimiter Length	1 bit

Figure 47.
MCU to LIN transceiver connections

External IP revisions

Table 66.
IP revisions
Module	IP	Revision	Vendor
CANFD	mxttcanfd	M_TTCAN IP revision: Rev.3.2.3	Bosch
Arm® Cortex®-M0+	armcm0p	Cortex®-M0+-r0p1	Arm®
Arm® Cortex®-M4F	armcm4	Cortex®-M4-r0p1	Arm®
Arm® Coresight	armcoresighttk	CoreSight-SoC-TM100-r3p2	Arm®

Acronyms

Table 67.
Acronyms used in the Document
Acronym	Description
A/D	Analog-to-Digital
ABS	Absolute
ADC	Analog-to-Digital converter
AES	Advanced encryption standard
AHB	AMBA (advanced microcontroller bus architecture) high-performance bus, Arm® data transfer bus
Arm®	Advanced RISC machine, a CPU architecture
ASIL	Automotive safety integrity level
BOD	Brown-out detection
CAN FD	Controller Area Network with Flexible Data rate
CMOS	Complementary metal-oxide-semiconductor
CPU	Central Processing Unit
CRC	Cyclic redundancy check, an error-checking protocol
CSV	Clock supervisor
CTI	Cross trigger interface
DES	Data encryption standard
DFT	Design-For-Test
DW	Datawire same as P-DMA
ECC	Error correcting code/Elliptical curve cryptography
ECO	External crystal oscillator
ETM	Embedded Trace Macrocell
EVTGEN	Event Generator
FLL	Frequency-locked loop
FPU	Floating point unit
GHS	Green Hills tool chain with Multi IDE
GPIO	General purpose input/output
HSM	Hardware security module
I/O	Input/output
I ² C	Inter-Integrated Circuit, a communications protocol
ILO	Internal low-speed oscillator
IMO	Internal main oscillator
IOSS	Input/output sub-system
IPC	Inter-processor communication
IrDA	Infrared interface
IRQ	Interrupt request
JTAG	Joint test action group
LDO	Low drop out regulators
LIN	Local Interconnect Network, a communications protocol
LVD	Low voltage detection
OTA	Over-the-air programming
OTP	One-time programmable
OVD	Over voltage detection
P-DMA	Peripheral-Direct Memory Access same as DW
PLL	Phase-locked loop
POR	Power-on reset
PPU	Peripheral protection unit
PRNG	Pseudorandom number generator
PWM	Pulse-width modulation
MCU	Microcontroller Unit
MCWDT	Multi-counter watchdog timer
M-DMA	Memory-Direct Memory Access
MISO	SPI Master-in slave-out
MMIO	Memory mapped I/O
MOSI	SPI Master-out slave-in
MPU	Memory protection unit
MTB	Micro trace buffer
MUL	Multiplier
MUX	Multiplexer
NVIC	Nested vectored interrupt controller
RAM	Random access memory
RISC	Reduced-instruction-set computing
ROM	Read only memory
RSA	Rivest-Shamir-Adleman Public Key Encryption Algorithm
RTC	Real-time clock
SAR	Successive approximation register
SCB	Serial communication block
SCL	I ² C serial clock
SDA	I ² C serial data
SECDED	Single error correction, double error detection
SHA	Secure hash algorithm
SHE	Secure hardware extension
SMPU	Shared memory protection unit
SPI	Serial peripheral interface, a communications protocol
SRAM	Static random access memory
SWD	Serial wire debug
SWJ	Serial wire JTAG
TCPWM	Timer/Counter Pulse-width modulator
TTL	Transistor-transistor logic
TRNG	True random number generator
UART	Universal Asynchronous Transmitter Receiver
WCO	Watch crystal oscillator
WDT	Watchdog timer reset

Revision history

Table 68.
Revision History
Document revision	Date	Description of changes
**	2017-02-10	Advance datasheet
*A	2017-03-31	Extensive rewrite of all sections for better clarity
*B	2017-09-11	Updated Features . Minor corrections in Features list . Updated Blocks and functionality . Updated Functional description . Updated Memory Map to clarify single and dual bank mode functionality. Updated Electrical specifications . Added the following timing diagrams in Electrical specifications : Reset, TCPWM, SCB (I ² C, SPI), Crystal Connection Scheme, SAR ADC, System Resources, and JTAG. Updated Ordering information . Updated Packaging to include two formats: Without alternate functions With alternate functions Updated Table 62 .
*C	2018-02-12	Updated Ordering information Updated title to “CYT2B5/B7 Datasheet 32-bit Arm® Cortex®-M4F Microcontroller TRAVEO™ T2G Family”. Updated . Electrical specifications Updated SPI Diagrams. Added ADC equivalent circuit for analog input.
*D	2018-09-27	Updated Features list and Peripheral I/O map Updated Pin assignment Updated Alternate function pin assignments Updated Functional description Updated Trigger multiplexer and Interrupts and wake-up assignments Added General P-DMA descriptions, Clock Dividers, and GPIO power port source information. Updated Clock diagram Added Table 13 table and references to it in alternate pin assignment. Update Electrical specifications . Updated Design Review. Added Errata
*E	2019-07-25	Updated Features , Features list , and Functional description . Updated Peripheral I/O map . Updated Alternate function pin assignments Updated Interrupts and wake-up assignments and Core interrupt types . Updated Trigger Groups and Peripheral clocks Updated Peripheral Protection Unit Fixed Structure Pairs Updated Bus masters Updated Miscellaneous configuration Updated Reset Sequence, ADC, and SPI Diagrams. Updated Table 48 and Table 51 Updated Ordering information and Packaging Updated Appendix
*F	2019-11-26	Updated SRAM in CYT2B7 address map Updated PLL and FLL in Functional description Updated Programmable PPU and SCB in Peripheral I/O map . Updated Table 62 Updated affected MPNs in Errata. Updated sample revision in Ordering information .
*G	2020-04-23	Added eSHE footnote on page 1. Updated Block diagram Updated SCB/UART content in Functional description Added note for V _CCD in Power pin assignments Added Table 17 Updated Table 24 table with detailed descriptions. Added JTAG ID and package support footnotes in Ordering information Removed CM7 from Part number nomenclature Updated Packaging Updated Errata
*H	2020-06-29	Updated Features list Updated Clock system Updated Electrical specifications Updated Ordering information Updated Appendix For details, refer to Revision history change log
*I	2021-10-13	Updated Features list Updated Communication peripheral instance list Updated High-speed I/O matrix connections Updated Alternate function pin assignments Updated Faults . Updated Electrical specifications Updated Part number nomenclature Updated Appendix Added Errata For details, refer to Rev *I updates in the Revision history change log .
*J	2022-09-08	Updated Electrical specifications . Updated Errata For details, refer to Rev *J updates in the Revision history change log .
*K	2023-07-12	Updated General description . Updated Features list . Updated Blocks and functionality . Updated . Peripheral I/O map Updated Package pin list and alternate functions . Updated Power pin assignments Updated Alternate function pin assignments Updated Ordering information . Updated Packaging . Updated Errata
*L	2024-03-04	Updated Triggers one-to-one Updated Errata.
*M	2025-06-10	Updated PLL and FLL . Updated Table 38 . Removed Errata. Updated Figure 5 , Figure 7 , Figure 9 , Figure 11 , and Figure 13 .
*N	2026-03-10	Updated General description . Updated Features . Updated Features list . Updated Clock specifications . Updated Ordering information . Updated Table 59 . Updated Table 60 . Updated template. Updated footnote numbers.

Revision history change log

Table 69.
Revision history change log
Section	Change description	Current spec	New spec	Reason for change
*Rev. N section updates**
General description	Added description	None	Infineon's TRAVEO™ T2G 32-bit Automotive MCU is a high-performance, low-power controller designed for automotive applications, compliant to ISO 26262 for functional safety and ISO 21434 for cybersecurity.	Addition
Features	Updated description	Crypto engine	ISO 21434 compliant / EVITA Full	Updated
Features	Updated description	Functional safety for ASIL-B	ISO 26262 functional safety compliant for ASIL-B	Updated
Features list	Updated description	Functional safety \| ASIL-B	Functional safety \| ISO 26262 ASIL-B compliant	Updated
Features list	Updated description	Security	Security - ISO 21434 compliant	Updated
26.12 Clock specifications	Updated description for Note for ECO connection scheme	17: Please refer to the family-specific Architecture TRM for more information on crystal requirements (002-19314, TRAVEO™ T2G Automotive MCU body controller entry architecture technical reference manual).	17: Please refer to the family-specific Architecture TRM for more information on crystal requirements (002-19314, TRAVEO™ T2G Automotive MCU body controller entry architecture technical reference manual). Before enabling ECO, the TRIM registers (ATRIM, WDTRIM, FTRIM, GTRIM and RTRIM) shall be configured with correct settings based on and User Guide "Setting ECO parameters, TRAVEO™ T2G family" (Doc No. 002-30194) and the crystal matching test from the crystal vendor.	Updated
27 Ordering information	Table 58 Added five new device codes, added AUTOSAR package column	None	Added five new device codes CYT2B73CXE, CYT2B74CXE, CYT2B75CXE, CYT2B77CXE, CYT2B78CXE. Added AUTOSAR package column	Addition
27.1 Part number nomenclature	Table 59 Updated Marketing option	A \| No options	A \| No options X \| AUTOSAR package	Updated
27.1 Part number nomenclature	Table 60 Updated Marketing option	A \| No options	A \| No options X \| AUTOSAR package	Updated

¹ The Crypto engine features are available on select MPNs.

² This feature is not available in “eSHE only” parts; for more information, refer to Ordering information .

³ Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM) support are enabled by third-party firmware.

⁴ GPIO_STD supporting 2.7 V to 5.5 V V _DDIO range.

⁵ GPIO_ENH supporting 2.7 V to 5.5 V V _DDIO range with higher currents at lower voltages.

⁶ Operation of reference-timed peripherals (like a UART) with an FLL-based reference is not recommended due the allowed frequency error.

⁷ VREF_L prevents IR drops in the VSSIO and VSSA paths from impacting the measurements. VREF_L, when properly connected, reduces or removes the impact of IR drops in the VSSIO and VSSA paths from measurements.

⁸ I/Os drive level does not support the full bus capacitance in Fast-mode Plus speeds.

⁹ This is not 100% compliant with the I ² C-bus specification; I/Os are not over-voltage tolerant, do not support the 20-mA sink requirement of Fast-mode Plus, and violate the leakage specification when no power is applied.

¹⁰ Only Port 0 with the slew rate control enabled meets the minimum fall time requirement.

¹¹ The Easy SPI (EZSPI) protocol is based on the Motorola SPI operating in any mode (0, 1, 2, or 3). It allows communication between master and slave reduces the need for CPU intervention.

¹² The Easy I ² C (EZI2C) protocol is a unique communication scheme built on top of the I ² C protocol by Infineon. It uses a meta protocol around the standard I ² C protocol to communicate to an I ² C slave using indexed memory transfers. This reduces the need for CPU intervention.

¹³ The I/Os in VDDIO_1 domain are referred to the VDDD domain in 64-LQFP package.

¹⁴ The size representation is not up to scale.

¹⁵ First 2 KB of SRAM is reserved, not available for users. User must keep the power of first 32KB block of SRAM0 in enabled or retained in all Active, LP Active, Sleep, LP Sleep, DeepSleep modes.

¹⁶ These six Programmable PPUs are configured by the Boot ROM and are available for the user based on the access rights. Refer to the device specific TRM to know more about the configuration of these programmable PPUs.

¹⁷ Port configuration of SWD/JTAG pins will be changed from the default GPIO mode to support debugging after the boot process, refer to Table 14 for pin assignments.

¹⁸ Refer to Table 17 for more information on pin multiplexer abbreviations used.

¹⁹ For any function marked with an identifier (n), the AC timing is only guaranteed within the respective group “n”.

²⁰ All port pin functions available in DeepSleep mode are also available in Active mode.

²¹ HCon refers to High Speed I/O matrix connection reference as per Table 13 .

²² DeepSleep ordering (DS #0, DS #1, DS #2) does not have any impact on choosing any alternate functions; the HSIOM module handles the individual alternate function assignment.

²³ I/O pins that support an oscillator function (WCO or ECO) must be configured for high-impedance if the oscillator is enabled.

²⁴ This I/O has increased leakage to ground when the V _DDD supply is below the POR threshold.

²⁵

The V _CCD pins must be connected together to ensure a low-impedance connection. (see the requirement in Figure 16 ).

²⁶ Refer to Table 17 for more information on pin multiplexer abbreviations used.

²⁷ For any function marked with an identifier (n), the AC timing is only guaranteed within the respective group "n".

²⁸ High Speed I/O matrix connection (HCon) reference as per Table 13 .

²⁹ Active Mode ordering (ACT#0, ACT#1, and so on) does not have any impact on configuring alternate functions; the HSIOM module handles the alternate function assignments.

³⁰ User interrupt cannot be used for CM0+ application, as it is used internally by system calls. Note, this does not impact CM4 application

³¹ The diagram shows only the TRIG_LABEL, final trigger formation is based on the formula TRIG_(PREFIX(IN/OUT))(MUX_x)(TRIG_LABEL) / TRIG_(PREFIX(IN_1TO1/OUT_1TO1))(x)(TRIG_LABEL) and Table 20 , Table 21 , and Table 22 .

³² “a:b” depicts a range starting from ‘a’ through ‘b’

³³ Each logical channel of SAR ADC[x] can be connected to any of the SAR ADC[x]_y external pin. (x = 0, or 1, or, 2 and y=0 to max 31)

³⁴ Fixed PPU is configured inside the Boot and user is not allowed to change the attributes of this PPU.

³⁵ These parameters are based on the condition that V _SSD

V _SSA = 0.0 V.

³⁶ The I/Os in V _{DDIO_1} domain are referred to the V _DDD domain in 64-LQFP package.

³⁷ A current-limiting resistor must be provided such that the current at the I/O pin does not exceed rated values at any time, including during power transients. Refer to Figure 15 for more information on the recommended circuit.

³⁸ V _DDIO and V _DDD must be sufficiently loaded or protected to prevent them from being pulled out of the recommended operating range by the clamp current.

³⁹ When the conditions of ³⁷ , ³⁸ , and SID18A/B/C/D are met, |I _{CLAMP_ABS} | supersedes V _{IA_ABS} and V _{I_ABS}

⁴⁰ The definition of “closer” depends on the package. In LQFP packaging, “closest” is determined by counting pins. For example, in a 176-LQFP package, P17.4 (pin 120) is closer to the V _DDD on pin 110 than on pin 132. Ports 11 and 21 should not be used for injection currents. The impact of injection currents is only defined for GPIO_STD/GPIO_ENH type I/Os.

⁴¹ The maximum output current is the peak current flowing through any one I/O.

⁴² The total output current is the maximum current flowing through all I/Os (GPIO_STD, and GPIO_ENH).

⁴³ +B is the positive battery voltage around 45 V.

⁴⁴ V _DDD , V _{DDIO_1} , VDDIO_2 , and V _DDA do not have any sequencing limitation and can establish in any order. These supplies (except for V _DDA and V _{DDIO_2} ) are independent in voltage level. See 12-Bit SAR ADC DC Specifications when using ADC units.

⁴⁵ 3.0 V ±10% is supported with a lower BOD setting option for V _DDD and V _DDA . This setting provides robust protection for internal timing but BOD reset occurs at a voltage below the specified operating conditions. A higher BOD setting option is available (consistent with down to 3.0 V) and guarantees that all operating conditions are met.

⁴⁶ 5.0 V ±10% is supported with a higher OVD setting option for V _DDD and V _DDA . This setting provides robust protection for internal and interface timing, but OVD reset occurs at a voltage above the specified operating conditions. A lower OVD setting option is available (consistent with up to 5.0 V) and guarantees that all operating conditions are met. Voltage overshoot to a higher OVD setting range for V _DDD and V _DDA is permissible, provided the duration is less than 2 hours cumulated. Note that during overshoot voltage condition electrical parameters are not guaranteed.

⁴⁷ eFuse programming must be executed with the part in a “quiet” state, with minimal activity (preferably only JTAG or a single LIN/CAN channel on V _DDD domain, no activity on V _{DDIO_1} ).

⁴⁸ Smoothing capacitor, C _S1 is required per chip (not per V _CCD pin). The V _CCD pins must be connected together to ensure a low-impedance connection (see the requirement in Figure 16 ).

⁴⁹ Capacitors used for power supply decoupling or filtering are operated under a continuous DC-bias. Many capacitors used with DC power across them provide less than their target capacitance, and their capacitance is not constant across their working voltage range. When selecting capacitors for use with this device, ensure that the selected components provide the required capacitance under the specific operating conditions of temperature and voltage used in your design. While the temperature coefficient is normally found within a parts catalog (such as, X7R, C0G, Y5V), the matching voltage coefficient may only be available on the component datasheet or direct from the manufacturer. Use of components that do not provide the required capacitance under the actual operating conditions may cause the device to operate to less than datasheet specifications

⁵⁰ At cold temperature –5°C to –40°C, the DeepSleep to Active transition time can be higher than the max time indicated by as much as 20 µs.

⁵¹ If longer pulse suppression width is required, use Smart I/O.

⁵² V _DDD must be greater than 0.8 × V _DDA when ADC[2] is enabled. V _{DDIO_1} must be greater than 0.8 × V _DDA when ADC[0] is enabled.

⁵³ In order to drive full bus load at 400 kHz, 6 mA I _OL is required at 0.6 V V _OL .

⁵⁴ In order to drive full bus load at 1 MHz, 20 mA I _OL is required at 0.4 V V _OL . However, this device does not support

⁵⁵ The code-flash includes a 'Write Buffer' of 4096-bit. If the application software writes this buffer multiple times, to get the overall write time multiply one sector write time with the corresponding factor (say for factor 64, example, 64 x 512 B = 32 KB [one sector]).

⁵⁶ Intermediate clocks that are not listed have the same limitations as that of their parent clock.

⁵⁷ Mainly depends on the external crystal.

⁵⁸ Please refer to the family-specific Architecture TRM for more information on crystal requirements (002-19314,TRAVEO™ T2G Automotive MCU body controller entry architecture technical reference manual). Before enabling ECO, the TRIM registers (ATRIM, WDTRIM, FTRIM, GTRIM and RTRIM) shall be configured with correct settings based on and User Guide "Setting ECO parameters, TRAVEO™ T2G family" (Doc No. 002-30194) and the crystal matching test from the crystal vendor.

⁵⁹ Please refer to family-specific Architecture reference manual for more information on crystal requirements (002-19314, TRAVEO™ T2G Automotive MCU body controller entry architecture technical reference manual).

⁶⁰ Mainly depends on the external crystal.

⁶¹ Supported shipment types are “Tray” (default) and “Tape and Reel”. Add the character ‘T’ at the end to get the ordering code for “Tape and Reel” shipment type.

⁶² 3DES/SHA-1/SHA-2/SHA-3/CRC/Vector unit for asymmetric cryptography features are not supported.

⁶³ Code-flash size 1088 KB = 32 KB × 30 (Large Sectors) + 8 KB × 16 (Small Sectors)

⁶⁴ Work-flash size 96 KB = 2 KB × 36 (Large Sectors) + 128 B × 192 (Small Sectors).

⁶⁵ S-grade Temperature (–40°C to 105°C).

⁶⁶ JTAG ID CODE bits 12 through 27, represents the Silicon ID of the device.

⁶⁷ E-grade Temperature (–40°C to 125°C).

⁶⁸ The numbers are estimated values based simulation only and are based on a single bill of material combination per package type.

⁶⁹ a1 = CTE (Coefficient of Thermal Expansion) value below T _g (ppm/°C) (T _g is glass transition temperature which is 131°C).

⁷⁰ a2 = CTE value above T _g (ppm/°C).

⁷¹ Board condition complies to JESD51-7(4 Layers)

⁷² Maximum value °C/Watt shown is for T _A = 125°C.

CYT2B7 TRAVEO™ T2G 32-bit Automotive MCU

General description​

Features​

Features list​

Communication peripheral instance list​

Blocks and functionality​

Block diagram​

Functional description​

CPU subsystem​

CPU

DMA controllers

Flash

SRAM

ROM

Cryptography accelerator for security

System resources​

Power system

Regulators

DeepSleep

Core internal

Clock system

IMO clock source

ILO clock source

PLL and FLL

Clock supervisor (CSV)

EXT_CLK

ECO

WCO

Reset

Watchdog timers

Power modes

Peripherals​

Peripheral clock dividers

Peripheral protection unit

12-bit SAR ADC

Timer/counter/PWM block (TCPWM)

Serial communication blocks (SCB)

I 2 C interface

UART interface

SPI interface

CAN FD

Local interconnect network (LIN)

One-time-programmable (OTP) eFuse

Event generator

Trigger multiplexer

I/Os​

Port nomenclature

Smart I/O

CYT2B7 address map​

Flash base address map​

Peripheral I/O map​

CYT2B7 clock diagram​

CYT2B7 CPU start-up sequence​

Pin assignment​

High-speed I/O matrix connections​

Package pin list and alternate functions​

Power pin assignments​

Alternate function pin assignments​

Interrupts and wake-up assignments​

Core interrupt types​

Trigger multiplexer​

Triggers group inputs​

Triggers group outputs​

Triggers one-to-one​

Peripheral clocks​

Faults​

Peripheral Protection Unit Fixed Structure Pairs​

Bus masters​

Miscellaneous configuration​

Development support​

Documentation​

Software user guide

Technical reference manual

Tools​

Electrical specifications​

Absolute maximum ratings​

Recommended operating conditions​

DC specifications​

Reset specifications​

I/O​

General description

Features

Features list

Communication peripheral instance list

Blocks and functionality

Block diagram

Functional description

CPU subsystem

System resources

Peripherals

I ² C interface

I/Os

CYT2B7 address map

Flash base address map

Peripheral I/O map

CYT2B7 clock diagram

CYT2B7 CPU start-up sequence

Pin assignment

High-speed I/O matrix connections

Package pin list and alternate functions

Power pin assignments

Alternate function pin assignments

Interrupts and wake-up assignments

Core interrupt types

Trigger multiplexer

Triggers group inputs

Triggers group outputs

Triggers one-to-one

Peripheral clocks

Faults

Peripheral Protection Unit Fixed Structure Pairs

Bus masters

Miscellaneous configuration

Development support

Documentation

Tools

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Bootloading or end-of-line programming

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³⁵ These parameters are based on the condition that V _SSD