ENABLE_ACQUIRE​

Enables or disables the acquisition of the target device in test mode.


Possible values:

  • 1 – Test mode acquisition enabled (default, recommended)

  • 0 – Test mode acquisition disabled (used for attaching to the running target, not recommended for programming and debugging)

Note:

For PSOC™ Edge E84, Test mode acquisition is implemented for MiniProg4, KitProg3, J-Link, and cmsis-dap probes via SWD and JTAG protocols. For the slow host PC, however, or when using USB virtualization, and for the devices with small Listen window duration, it is recommended to use MiniProg4/KitProg3 and SWD.

ENABLE_CM33, ENABLE_CM55​

Specifies the CPU cores' visibility to OpenOCD. Useful for single or multi-core applications debugging.


Possible values:

  • 1 – Core is enabled.

  • 0 – Core is disabled.

Only CM33 core is enabled by default, allowing any application programming and allowing debugging of CM33-based applications. CM55 core is disabled after reset, and enabling it in OpenOCD is recommended only for CM55 or Multi-Core applications debugging. When enabling CM55, the CM33 core must also be enabled.

DEBUG_CERTIFICATE​

Specifies the location of the debug certificate (token) binary file to re-enable the CPU Access Port(s) for programming and debugging operations if the port(s) was closed per applied policies.

Note:

Debug certificate is of no use if the policy for Access Port is ‘permanent disable’.

DEBUG_CERTIFICATE_ADDR​

(Optional) Specifies the SRAM location where the debug certificate (token) will be loaded. The default address is 0x34000000.

SMIF_BANKS​

Defines QSPI memory banks. This variable is a two-dimensional associative Tcl array of the following format:

set SMIF_BANKS {
  1 {addr <XIPaddr1> size <BankSz1>}
  2 {addr <XIPaddr2> size <BankSz2>}
  ...
  N {addr <XIPaddrN> size <BankSzN>}
}

Where:

  • XIPaddrN

    – XIP mapping address

  • BankSzN

    – Total size of this flash bank, in bytes

RRAM_MAIN_OFFSET​

Defines the offset for the users’ space in the RRAM_MAIN_NVM region, to exclude the system data and proprietary boot assets from programming operations. The default value is 0x11000.

Users may free up to 28 KB at the start of the programmable RRAM region by replacing the extended boot image and setting the appropriate offset in the OpenOCD command line.

Example:

openocd -s scripts -f interface/kitprog3.cfg -c "set RRAM_MAIN_OFFSET 0xA000" -f target/infineon/pse84xgxs2.cfg -c "init; reset init; flash banks; shutdown"


openocd -s scripts -f interface/kitprog3.cfg -c "set RRAM_MAIN_OFFSET 0xA000" -f target/infineon/pse84xgxs4.cfg -c "init; reset init; flash banks; shutdown"

Refer to “PSOC™ Edge MCU Programming Specifications” for the NVM memory definitions. Refer to “Getting started with PSOC™ Edge security” application note for the details of replacing the extended boot image.