XMC1200 AB-Step

XMC1000 Family

Microcontroller Series for Industrial Applications

ARM® Cortex®-M0

32-bit processor core

Datasheet

About this Document

This datasheet is addressed to embedded hardware and software developers. It provides the reader with detailed descriptions about the ordering designations, available features, electrical and physical characteristics of the XMC1200 series devices.

The document describes the characteristics of a superset of the XMC1200 series devices. For simplicity, the various device types are referred to by the collective term XMC1200 throughout this document.

XMC1000 Family User Documentation

The set of user documentation includes:

• Reference Manual

  • describes the functionality of the superset of devices.

• Datasheets

  • list the complete ordering designations, available features and electrical characteristics of derivative devices.

• Errata Sheets

  • list deviations from the specifications given in the related Reference Manual or Datasheets. Errata Sheets are provided for the superset of devices.

Attention:
Please consult all parts of the documentation set to attain consolidated knowledge about your device.

Application related guidance is provided by

Users Guides

and

Application Notes

.

Please refer to

http://www.infineon.com/xmc1000

to get access to the latest versions of those documents.

Summary of Features

The XMC1200 devices are members of the XMC1000 Family of microcontrollers based on the ARM Cortex-M0 processor core. The XMC1200 series devices are optimized for LED Lighting and Human-Machine interface (HMI) applications.

Figure 1. System Block Diagram

CPU Subsystem

• CPU Core

  • High-performance 32-bit ARM Cortex-M0 CPU

  • Most 16-bit Thumb and subset of 32-bit Thumb2 instruction set

  • Single cycle 32-bit hardware multiplier

  • System timer (SysTick) for Operating System support

  • Ultra low power consumption

• Nested Vectored Interrupt Controller (NVIC)

• Event Request Unit (ERU) for processing of external and internal service requests

On-Chip Memories

• 8 kbytes on-chip ROM

• 16 kbytes on-chip high-speed SRAM

• up to 200 kbytes on-chip Flash program and data memory

Communication Peripherals

• Two Universal Serial Interface Channels (USIC), usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces

• LED and Touch-Sense Controller (LEDTS) for Human-Machine interface

Analog Frontend Peripherals

• A/D Converters

  • up to 12 analog input pins

  • 2 sample and hold stages with 8 analog input channels each

  • fast 12-bit analog to digital converter with adjustable gain

• Up to 8 channels of out of range comparators (ORC)

• Up to 3 fast analog comparators (ACMP)

• Temperature Sensor (TSE)

Industrial Control Peripherals

• Capture/Compare Units 4 (CCU4) as general purpose timers

• Brightness and Colour Control Unit (BCCU), for LED color and dimming application

System Control

• Window Watchdog Timer (WDT) for safety sensitive applications

• Real Time Clock module with alarm support (RTC)

• System Control Unit (SCU) for system configuration and control

• Pseudo random number generator (PRNG) for fast random data generation

Input/Output Lines

• Programmable port driver control module (PORTS)

• Individual bit addressability

• Tri-stated in input mode

• Push/pull or open drain output mode

• Configurable pad hysteresis

On-Chip Debug Support

• Support for debug features: 4 breakpoints, 2 watchpoints

• Various interfaces: ARM serial wire debug (SWD), single pin debug (SPD)

Ordering Information

The ordering code for an Infineon microcontroller provides an exact reference to a specific product. The code “XMC1<DDD>-<Z><PPP><T><FFFF>” identifies:

• <DDD> the derivatives function set

• <Z> the package variant

  • T: TSSOP

  • Q: VQFN

• <PPP> package pin count

• <T> the temperature range:

  • F: -40°C to 85°C

  • X: -40°C to 105°C

• <FFFF> the Flash memory size

For ordering codes for the XMC1200 please contact your sales representative or local distributor.

This document describes several derivatives of the XMC1200 series, some descriptions may not apply to a specific product. Please see

Device Types

.

For simplicity the term

XMC1200

is used for all derivatives throughout this document.

Device Types

These device types are available and can be ordered through Infineon’s direct and/or distribution channels.

Table 1. Synopsis of XMC1200 Device Types

Derivative	Package	Flash Kbytes	SRAM Kbytes
XMC1201-T028F0016	PG-TSSOP-28-16	16	16
XMC1201-T028F0032	PG-TSSOP-28-16	32	16
XMC1201-T038F0016	PG-TSSOP-38-9	16	16
XMC1201-T038F0032	PG-TSSOP-38-9	32	16
XMC1201-T038F0064	PG-TSSOP-38-9	64	16
XMC1201-T038F0128	PG-TSSOP-38-9	128	16
XMC1201-T038F0200	PG-TSSOP-38-9	200	16
XMC1200-T038F0200	PG-TSSOP-38-9	200	16
XMC1202-T028X0016	PG-TSSOP-28-16	16	16
XMC1202-T028X0032	PG-TSSOP-28-16	32	16
XMC1202-T028X0064	PG-TSSOP-28-16	64	16
XMC1202-T016X0016	PG-TSSOP-16-8	16	16
XMC1202-T016X0032	PG-TSSOP-16-8	32	16
XMC1202-T016X0064	PG-TSSOP-16-8	64	16
XMC1202-Q024X0016	PG-VQFN-24-19	16	16
XMC1202-Q024X0032	PG-VQFN-24-19	32	16
XMC1201-Q040F0016	PG-VQFN-40-13	16	16
XMC1201-Q040F0032	PG-VQFN-40-13	32	16
XMC1201-Q040F0064	PG-VQFN-40-13	64	16
XMC1201-Q040F0128	PG-VQFN-40-13	128	16
XMC1201-Q040F0200	PG-VQFN-40-13	200	16
XMC1202-Q040X0016	PG-VQFN-40-13	16	16
XMC1202-Q040X0032	PG-VQFN-40-13	32	16

Device Type Features

The following table lists the available features per device type.

Table 2. Features of XMC1200 Device Types ¹

Derivative	ADC channel	ACMP	BCCU	LEDTS
XMC1200-T038	16	3	1	2
XMC1201-T028	14	–	–	2
XMC1201-T038	16	–	–	2
XMC1202-T028	14	3	1	–
XMC1202-T016	11	2	1	–
XMC1202-Q024	13	3	1	–
XMC1201-Q040	16	–	–	2
XMC1202-Q040	16	3	1	–

Table 3. ADC Channels ²

Package	VADC0 G0	VADC0 G1
PG-TSSOP-16	CH0..CH5	CH0..CH4
PG-TSSOP-28	CH0..CH7	CH0 .. CH4, CH7
PG-TSSOP-38	CH0..CH7	CH0..CH7
PG-VQFN-24	CH0..CH7	CH0..CH4
PG-VQFN-40	CH0..CH7	CH1, CH5..CH7

Chip Identification Number

The Chip Identification Number allows software to identify the marking. It is a 8 words value with the most significant 7 words stored in Flash configuration sector 0 (CS0) at address location :

1000 0F00

(MSB) -

1000 0F1B

(LSB). The least significant word and most significant word of the Chip Identification Number are the value of registers DBGROMID and IDCHIP, respectively.

Table 4. XMC1200 Chip Identification Number

Derivative	Value	Marking
XMC1201-T028F0016	00012022 01CF00FF 00001FF7 00006000 00000C00 00001000 00005000 201ED083	AB
XMC1201-T028F0032	00012022 01CF00FF 00001FF7 00006000 00000C00 00001000 00009000 201ED083	AB
XMC1201-T038F0016	00012012 01CF00FF 00001FF7 00006000 00000C00 00001000 00005000 201ED083	AB
XMC1201-T038F0032	00012012 01CF00FF 00001FF7 00006000 00000C00 00001000 00009000 201ED083	AB
XMC1201-T038F0064	00012012 01CF00FF 00001FF7 00006000 00000C00 00001000 00011000 201ED083	AB
XMC1201-T038F0128	00012012 01CF00FF 00001FF7 00006000 00000C00 00001000 00021000 201ED083	AB
XMC1201-T038F0200	00012012 01CF00FF 00001FF7 00006000 00000C00 00001000 00033000 201ED083	AB
XMC1200-T038F0200	00012012 01CF00FF 00001FF7 0000E000 00000C00 00001000 00033000 201ED083	AB
XMC1202-T028X0016	00012023 01CF00FF 00001FF7 00008000 00000C00 00001000 00005000 201ED083	AB
XMC1202-T028X0032	00012023 01CF00FF 00001FF7 00008000 00000C00 00001000 00009000 201ED083	AB
XMC1202-T028X0064	00012023 01CF00FF 00001FF7 00008000 00000C00 00001000 00011000 201ED083	AB
XMC1202-T016X0016	00012033 01CF00FF 00001FF7 00008000 00000C00 00001000 00005000 201ED083	AB
XMC1202-T016X0032	00012033 01CF00FF 00001FF7 00008000 00000C00 00001000 00009000 201ED083	AB
XMC1202-T016X0064	00012033 01CF00FF 00001FF7 00008000 00000C00 00001000 00011000 201ED083	AB
XMC1202-Q024X0016	00012063 01CF00FF 00001FF7 00008000 00000C00 00001000 00005000 201ED083	AB
XMC1202-Q024X0032	00012063 01CF00FF 00001FF7 00008000 00000C00 00001000 00009000 201ED083	AB
XMC1201-Q040F0016	00012042 01CF00FF 00001FF7 00006000 00000C00 00001000 00005000 201ED083	AB
XMC1201-Q040F0032	00012042 01CF00FF 00001FF7 00006000 00000C00 00001000 00009000 201ED083	AB
XMC1201-Q040F0064	00012042 01CF00FF 00001FF7 00006000 00000C00 00001000 00011000 201ED083	AB
XMC1201-Q040F0128	00012042 01CF00FF 00001FF7 00006000 00000C00 00001000 00021000 201ED083	AB
XMC1201-Q040F0200	00012042 01CF00FF 00001FF7 00006000 00000C00 00001000 00033000 201ED083	AB
XMC1202-Q040X0016	00012043 01CF00FF 00001FF7 00008000 00000C00 00001000 00005000 201ED083	AB
XMC1202-Q040X0032	00012043 01CF00FF 00001FF7 00008000 00000C00 00001000 00009000 201ED083	AB

General Device Information

This section summarizes the logic symbols and package pin configurations with a detailed list of the functional I/O mapping.

Logic Symbols

Figure 2. XMC1200 Logic Symbol for TSSOP-38, TSSOP-28 and TSSOP-16

Figure 3. XMC1200 Logic Symbol for VQFN-24 and VQFN-40

Pin Configuration and Definition

The following figures summarize all pins, showing their locations on the different packages.

Figure 4. XMC1200 PG-TSSOP-38 Pin Configuration (top view)

Figure 5. XMC1200 PG-TSSOP-28 Pin Configuration (top view)

Figure 6. XMC1200 PG-TSSOP-16 Pin Configuration (top view)

Figure 7. XMC1200 PG-VQFN-24 Pin Configuration (top view)

Figure 8. XMC1200 PG-VQFN-40 Pin Configuration (top view)

Package Pin Summary

The following general building block is used to describe each pin:

Table 5. Package Pin Mapping Description

Function	Package A	Package B	...	Pad Type
Px.y	N	N		Pad Class

The table is sorted by the “Function” column, starting with the regular Port pins (Px.y), followed by the supply pins.

The following columns, titled with the supported package variants, lists the package pin number to which the respective function is mapped in that package.

The “Pad Type” indicates the employed pad type:

• STD_INOUT(standard bi-directional pads)

• STD_INOUT/AN (standard bi-directional pads with analog input)

• High Current (high current bi-directional pads)

• STD_IN/AN (standard input pads with analog input)

• Power (power supply)

Details about the pad properties are defined in the Electrical Parameters.

Table 6. Package Pin Mapping

Function	VQFN 40	TSSOP 38	TSSOP 28	VQFN 24	TSSOP 16	Pad Type	Notes
P0.0	23	17	13	15	7	STD_INOUT
P0.1	24	18	–	–	–	STD_INOUT
P0.2	25	19	–	–	–	STD_INOUT
P0.3	26	20	–	–	–	STD_INOUT
P0.4	27	21	14	–	–	STD_INOUT
P0.5	28	22	15	16	8	STD_INOUT
P0.6	29	23	16	17	9	STD_INOUT
P0.7	30	24	17	18	10	STD_INOUT
P0.8	33	27	18	19	11	STD_INOUT
P0.9	34	28	19	20	12	STD_INOUT
P0.10	35	29	20	–	–	STD_INOUT
P0.11	36	30	–	–	–	STD_INOUT
P0.12	37	31	21	21	–	STD_INOUT
P0.13	38	32	22	22	–	STD_INOUT
P0.14	39	33	23	23	13	STD_INOUT
P0.15	40	34	24	24	14	STD_INOUT
P1.0	22	16	12	14	–	High Current
P1.1	21	15	11	13	–	High Current
P1.2	20	14	10	12	–	High Current
P1.3	19	13	9	11	–	High Current
P1.4	18	12	–	–	–	High Current
P1.5	17	11	–	–	–	High Current
P1.6	16	–	–	–	–	STD_INOUT
P2.0	1	35	25	1	15	STD_INOUT/AN
P2.1	2	36	26	2	–	STD_INOUT/AN
P2.2	3	37	27	3	–	STD_IN/AN
P2.3	4	38	–	–	–	STD_IN/AN
P2.4	5	1	–	–	–	STD_IN/AN
P2.5	6	2	28	–	–	STD_IN/AN
P2.6	7	3	1	4	16	STD_IN/AN
P2.7	8	4	2	5	1	STD_IN/AN
P2.8	9	5	3	5	1	STD_IN/AN
P2.9	10	6	4	6	2	STD_IN/AN
P2.10	11	7	5	7	3	STD_INOUT/AN
P2.11	12	8	6	8	4	STD_INOUT/AN
VSS	13	9	7	9	5	Power	Supply GND, ADC reference GND
VDD	14	10	8	10	6	Power	Supply VDD, ADC reference voltage/ORC reference voltage
VDDP	15	10	8	10	6	Power	When VDD is supplied, VDDP has to be supplied with the same voltage.
VSSP	31	25	–	–	–	Power	I/O port ground
VDDP	32	26	–	–	–	Power	I/O port supply
VSSP	Exp. Pad	–	–	Exp. Pad	–	Power	Exposed Die Pad The exposed die pad is connected internally to VSSP. For proper operation, it is mandatory to connect the exposed pad to the board ground. For thermal aspects, please refer to the Package and Reliability chapter.

Port I/O Functions

The following general building block is used to describe each PORT pin:

Table 7. Port I/O Function Description

Function	Outputs		Inputs
	ALT1	ALTn	Input	Input
P0.0		MODA.OUT	MODC.INA
Pn.y	MODA.OUT		MODA.INA	MODC.INB

Figure 9. Simplified Port Structure

Pn.y is the port pin name, defining the control and data bits/registers associated with it. As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT defines the output value.

Up to seven alternate output functions (ALT1/2/3/4/5/6/7) can be mapped to a single port pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective module, with the pin characteristics controlled by the port registers (within the limits of the connected pad).

The port pin input can be connected to multiple peripherals. Most peripherals have an input multiplexer to select between different possible input sources.

The input path is also active while the pin is configured as output. This allows to feedback an output to on-chip resources without wasting an additional external pin.

Please refer to

Table 9

for the complete Port I/O function mapping.

Hardware Controlled I/O Function Description

The following general building block is used to describe the hardware I/O and pull control functions of each PORT pin:

Table 8. Hardware Controlled I/O Function Description

Function	Outputs	Inputs	Pull Control
	HWO0	HWI0	HW0_PD	HW0_PU
P0.0	MODB.OUT	MODB.INA
Pn.y			$\stackrel{<p>¯</p>}{\mathrm{<p>M</p>}\mathrm{<p>O</p>}\mathrm{<p>D</p>}\mathrm{<p>C</p>}\mathrm{<p>.</p>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}}$	MODC.OUT

By Pn_HWSEL, it is possible to select between different hardware “masters” (HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s). Hardware control overrules settings in the respective port pin registers. Additional hardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by the peripherals can be used to control the pull devices of the pin.

Please refer to

Table 10

for the complete hardware I/O and pull control function mapping.

Table 9. Port I/O Functions

Function	Outputs							Inputs
	ALT1	ALT2	ALT3	ALT4	ALT5	ALT6	ALT7	Input	Input	Input	Input	Input	Input	Input	Input
P0.0	ERU0. PDOUT0	LEDTS0. LINE7	ERU0. GOUT0	CCU40. OUT0		USIC0_CH0.SELO0	USIC0_CH1.SELO0	BCCU0. TRAPINB	CCU40.IN0C			USIC0_CH0.DX2A	USIC0_CH1.DX2A
P0.1	ERU0. PDOUT1	LEDTS0. LINE6	ERU0. GOUT1	CCU40. OUT1		BCCU0. OUT8	SCU. VDROP		CCU40.IN1 C
P0.2	ERU0. PDOUT2	LEDTS0. LINE5	ERU0. GOUT2	CCU40. OUT2		VADC0. EMUX02			CCU40.IN2 C
P0.3	ERU0. PDOUT3	LEDTS0. LINE4	ERU0. GOUT3	CCU40. OUT3		VADC0. EMUX01			CCU40.IN3 C
P0.4	BCCU0. OUT0	LEDTS0. LINE3	LEDTS0. COL3	CCU40. OUT1		VADC0. EMUX00	WWDT. SERVICE_ OUT
P0.5	BCCU0. OUT1	LEDTS0. LINE2	LEDTS0. COL2	CCU40. OUT0		ACMP2. OUT
P0.6	BCCU0. OUT2	LEDTS0. LINE1	LEDTS0. COL1	CCU40. OUT0		USIC0_CH 1.MCLKOU T	USIC0_CH 1.DOUT0		CCU40.IN0 B			USIC0_CH 1.DX0C
P0.7	BCCU0. OUT3	LEDTS0. LINE0	LEDTS0. COL0	CCU40. OUT1		USIC0_CH 0.SCLKOU T	USIC0_CH 1.DOUT0		CCU40.IN1 B			USIC0_CH 0.DX1C	USIC0_CH 1.DX0D	USIC0_CH 1.DX1C
P0.8	BCCU0. OUT4	LEDTS1. LINE0	LEDTS0. COLA	CCU40. OUT2		USIC0_CH 0.SCLKOU T	USIC0_CH 1.SCLKOU T		CCU40.IN2 B			USIC0_CH 0.DX1B	USIC0_CH 1.DX1B
P0.9	BCCU0. OUT5	LEDTS1. LINE1	LEDTS0. COL6	CCU40. OUT3		USIC0_CH 0.SELO0	USIC0_CH 1.SELO0		CCU40.IN3 B			USIC0_CH 0.DX2B	USIC0_CH 1.DX2B
P0.10	BCCU0. OUT6	LEDTS1. LINE2	LEDTS0. COL5	ACMP0. OUT		USIC0_CH 0.SELO1	USIC0_CH 1.SELO1					USIC0_CH 0.DX2C	USIC0_CH 1.DX2C
P0.11	BCCU0. OUT7	LEDTS1. LINE3	LEDTS0. COL4	USIC0_CH 0.MCLKOU T		USIC0_CH 0.SELO2	USIC0_CH 1.SELO2					USIC0_CH 0.DX2D	USIC0_CH 1.DX2D
P0.12	BCCU0. OUT6	LEDTS1. LINE4	LEDTS0. COL3	LEDTS1. COL3		USIC0_CH 0.SELO3		BCCU0. TRAPINA	CCU40.IN0 A	CCU40.IN1 A	CCU40.IN2 A	CCU40.IN3 A	USIC0_CH 0.DX2E
P0.13	WWDT. SERVICE_ OUT	LEDTS1. LINE5	LEDTS0. COL2	LEDTS1. COL2		USIC0_CH 0.SELO4						USIC0_CH 0.DX2F
P0.14	BCCU0. OUT7	LEDTS1. LINE6	LEDTS0. COL1	LEDTS1. COL1		USIC0_CH 0.DOUT0	USIC0_CH 0.SCLKOU T					USIC0_CH 0.DX0A	USIC0_CH 0.DX1A
P0.15	BCCU0. OUT8	LEDTS1. LINE7	LEDTS0. COL0	LEDTS1. COL0		USIC0_CH 0.DOUT0	USIC0_CH 1.MCLKOU T					USIC0_CH 0.DX0B
P1.0	BCCU0. OUT0	CCU40. OUT0	LEDTS0. COL0	LEDTS1. COLA		ACMP1. OUT	USIC0_CH 0.DOUT0					USIC0_CH 0.DX0C
P1.1	VADC0. EMUX00	CCU40. OUT1	LEDTS0. COL1	LEDTS1. COL0		USIC0_CH 0.DOUT0	USIC0_CH 1.SELO0					USIC0_CH 0.DX0D	USIC0_CH 0.DX1D	USIC0_CH 1.DX2E
P1.2	VADC0. EMUX01	CCU40. OUT2	LEDTS0. COL2	LEDTS1. COL1		ACMP2. OUT	USIC0_CH 1.DOUT0					USIC0_CH 1.DX0B
P1.3	VADC0. EMUX02	CCU40. OUT3	LEDTS0. COL3	LEDTS1. COL2		USIC0_CH 1.SCLKOU T	USIC0_CH 1.DOUT0					USIC0_CH 1.DX0A	USIC0_CH 1.DX1A
P1.4	VADC0. EMUX10	USIC0_CH 1.SCLKOU T	LEDTS0. COL4	LEDTS1. COL3		USIC0_CH 0.SELO0	USIC0_CH 1.SELO1					USIC0_CH 0.DX5E	USIC0_CH 1.DX5E
P1.5	VADC0. EMUX11	USIC0_CH 0.DOUT0	LEDTS0. COLA	BCCU0. OUT1		USIC0_CH 0.SELO1	USIC0_CH 1.SELO2					USIC0_CH 1.DX5F
P1.6	VADC0. EMUX12	USIC0_CH 1.DOUT0	LEDTS0. COL5	USIC0_CH 0.SCLKOU T	BCCU0. OUT2	USIC0_CH 0.SELO2	USIC0_CH 1.SELO3			USIC0_CH 0.DX5F
P2.0	ERU0. PDOUT3	CCU40. OUT0	ERU0. GOUT3	LEDTS1. COL5		USIC0_CH 0.DOUT0	USIC0_CH 0.SCLKOU T		VADC0. G0CH5		ERU0.0B0	USIC0_CH 0.DX0E	USIC0_CH 0.DX1E	USIC0_CH 1.DX2F
P2.1	ERU0. PDOUT2	CCU40. OUT1	ERU0. GOUT2	LEDTS1. COL6		USIC0_CH 0.DOUT0	USIC0_CH 1.SCLKOU T	ACMP2.INP	VADC0. G0CH6		ERU0.1B0	USIC0_CH 0.DX0F	USIC0_CH 1.DX3A	USIC0_CH 1.DX4A
P2.2								ACMP2.INN	VADC0. G0CH7		ERU0.0B1	USIC0_CH 0.DX3A	USIC0_CH 0.DX4A	USIC0_CH 1.DX5A	ORC0.AIN
P2.3									VADC0. G1CH5		ERU0.1B1	USIC0_CH 0.DX5B	USIC0_CH 1.DX3C	USIC0_CH 1.DX4C	ORC1.AIN
P2.4									VADC0. G1CH6		ERU0.0A1	USIC0_CH 0.DX3B	USIC0_CH 0.DX4B	USIC0_CH 1.DX5B	ORC2.AIN
P2.5									VADC0. G1CH7		ERU0.1A1	USIC0_CH 0.DX5D	USIC0_CH 1.DX3E	USIC0_CH 1.DX4E	ORC3.AIN
P2.6								ACMP1.INN	VADC0. G0CH0		ERU0.2A1	USIC0_CH 0.DX3E	USIC0_CH 0.DX4E	USIC0_CH 1.DX5D	ORC4.AIN
P2.7								ACMP1.INP	VADC0. G1CH1		ERU0.3A1	USIC0_CH 0.DX5C	USIC0_CH 1.DX3D	USIC0_CH 1.DX4D	ORC5.AIN
P2.8								ACMP0.INN	VADC0. G0CH1	VADC0. G1CH0	ERU0.3B1	USIC0_CH 0.DX3D	USIC0_CH 0.DX4D	USIC0_CH 1.DX5C	ORC6.AIN
P2.9								ACMP0.INP	VADC0. G0CH2	VADC0. G1CH4	ERU0.3B0	USIC0_CH 0.DX5A	USIC0_CH 1.DX3B	USIC0_CH 1.DX4B	ORC7.AIN
P2.10	ERU0. PDOUT1	CCU40. OUT2	ERU0. GOUT1	LEDTS1. COL4		ACMP0. OUT	USIC0_CH 1.DOUT0		VADC0. G0CH3	VADC0. G1CH2	ERU0.2B0	USIC0_CH 0.DX3C	USIC0_CH 0.DX4C	USIC0_CH 1.DX0F
P2.11	ERU0. PDOUT0	CCU40. OUT3	ERU0. GOUT0	LEDTS1. COL3		USIC0_CH 1.SCLKOU T	USIC0_CH 1.DOUT0	ACMP.REF	VADC0. G0CH4	VADC0. G1CH3	ERU0.2B1	USIC0_CH 1.DX0E	USIC0_CH 1.DX1E

Table 10. Hardware Controlled I/O Functions

Function	Outputs		Inputs		Pull Control
	HWO0	HWO1	HWI0	HWI1	HW0_PD	HW0_PU	HW1_PD	HW1_PU
P0.0	LEDTS0. EXTENDED7		LEDTS0.TSIN7	LEDTS0. TSIN7	Reserved for LEDTS Scheme A: pull-down disabled always	Reserved for LEDTS Scheme A: pull-down enabled always	Reserved for LEDTS Scheme B: pull-up enabled and pull-down disabled, and vice versa
P0.1	LEDTS0. EXTENDED6		LEDTS0.TSIN6	LEDTS0.TSIN6
P0.2	LEDTS0. EXTENDED5		LEDTS0.TSIN5	LEDTS0. TSIN5
P0.3	LEDTS0. EXTENDED4		LEDTS0.TSIN4	LEDTS0. TSIN4
P0.4	LEDTS0. EXTENDED3		LEDTS0. TSIN3	LEDTS0. TSIN3
P0.5	LEDTS0. EXTENDED2		LEDTS0. TSIN2	LEDTS0. TSIN2
P0.6	LEDTS0. EXTENDED1		LEDTS0. TSIN1	LEDTS0. TSIN1
P0.7	LEDTS0. EXTENDED0		LEDTS0. TSIN0	LEDTS0. TSIN0
P0.8	LEDTS1. EXTENDED0		LEDTS1. TSIN0	LEDTS1. TSIN0
P0.9	LEDTS1. EXTENDED1		LEDTS1. TSIN1	LEDTS1. TSIN1
P0.10	LEDTS1. EXTENDED2		LEDTS1. TSIN2	LEDTS1. TSIN2
P0.11	LEDTS1. EXTENDED3		LEDTS1. TSIN3	LEDTS1. TSIN3
P0.12	LEDTS1. EXTENDED4		LEDTS1. TSIN4	LEDTS1. TSIN4
P0.13	LEDTS1. EXTENDED5		LEDTS1. TSIN5	LEDTS1. TSIN5
P0.14	LEDTS1. EXTENDED6		LEDTS1. TSIN6	LEDTS1. TSIN6
P0.15	LEDTS1. EXTENDED7		LEDTS1. TSIN7	LEDTS1. TSIN7
P1.0		USIC0_CH0.DOUT0		USIC0_CH0.HWIN0	$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>2</p>}}$	BCCU0.OUT2
P1.1		USIC0_CH0.DOUT1		USIC0_CH0.HWIN1	$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>3</p>}}$	BCCU0.OUT3
P1.2		USIC0_CH0.DOUT2		USIC0_CH0.HWIN2	$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>4</p>}}$	BCCU0.OUT4
P1.3		USIC0_CH0.DOUT3		USIC0_CH0.HWIN3	$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>5</p>}}$	BCCU0.OUT5
P1.4					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>6</p>}}$	BCCU0.OUT6
P1.5					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>7</p>}}$	BCCU0.OUT7
P1.6					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>8</p>}}$	BCCU0.OUT8
P2.0					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>1</p>}}$	BCCU0.OUT1
P2.1					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>6</p>}}$	BCCU0.OUT6
P2.2					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>0</p>}}$	BCCU0.OUT0	$\stackrel{<p>¯</p>}{\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="40">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>3</p>}}$	CCU40.OUT3
P2.3					$\stackrel{<p>¯</p>}{\mathrm{<p>A</p>}\mathrm{<p>C</p>}\mathrm{<p>M</p>}\mathrm{<p>P</p>}\mathrm{<ol\; start="2">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}}$	ACMP2.OUT
P2.4					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>8</p>}}$	BCCU0.OUT8
P2.5					$\stackrel{<p>¯</p>}{\mathrm{<p>A</p>}\mathrm{<p>C</p>}\mathrm{<p>M</p>}\mathrm{<p>P</p>}\mathrm{<ol>\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}}$	ACMP1.OUT
P2.6					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>2</p>}}$	BCCU0.OUT2	$\stackrel{<p>¯</p>}{\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="40">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>3</p>}}$	CCU40.OUT3
P2.7					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>8</p>}}$	BCCU0.OUT8	$\stackrel{<p>¯</p>}{\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="40">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>3</p>}}$	CCU40.OUT3
P2.8					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>1</p>}}$	BCCU0.OUT1	$\stackrel{<p>¯</p>}{\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="40">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>2</p>}}$	CCU40.OUT2
P2.9					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>7</p>}}$	BCCU0.OUT7	$\stackrel{<p>¯</p>}{\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="40">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>2</p>}}$	CCU40.OUT2
P2.10					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>4</p>}}$	BCCU0.OUT4
P2.11					$\stackrel{<p>¯</p>}{\mathrm{<p>B</p>}\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="0">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>5</p>}}$	BCCU0.OUT5

Electrical Parameters

This section provides the electrical parameters which are implementation-specific for the XMC1200.

General Parameters

Parameter Interpretation

The parameters listed in this section represent partly the characteristics of the XMC1200 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column:

• CC

  Such parameters indicate

  C

  ontroller

  C

  haracteristics, which are distinctive feature of the XMC1200 and must be regarded for a system design.

• SR

  Such parameters indicate

  S

  ystem

  R

  equirements, which must be provided by the application system in which the XMC1200 is designed in.

Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Table 11. Absolute Maximum Rating Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Junction temperature	T J SR	-40	–	115	°C	–
Storage temperature	T ST SR	-40	–	125	°C	–
Voltage on power supply pin with respect to V SSP	V DDP SR	-0.3	–	6	V	–
Voltage on digital pins with respect to V SSP 3	V IN SR	-0.5	–	V DDP + 0.5 or max. 6	V	whichever is lower
Voltage on P2 pins with respect to V SSP 4	V INP2 SR	-0.3	–	V DDP + 0.3	V	–
Voltage on analog input pins with respect to V SSP	V AIN V AREF SR	-0.5	–	V DDP + 0.5 or max. 6	V	whichever is lower
Input current on any pin during overload condition	I IN SR	-10	–	10	mA	–
Absolute maximum sum of all input currents during overload condition	Σ I IN SR	-50	–	+50	mA	–

Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification.

Table 12

defines overload conditions that will not cause any negative reliability impact if all the following conditions are met:

• full operation life-time is not exceeded

• Operating Conditions

  are met for:

  • pad supply levels (

    V

    DDP

    )

  • temperature

If a pin current is outside of the

Operating Conditions

but within the overload conditions, then the parameters of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters.

Note:
An overload condition on one or more pins does not require a reset.

Note:
A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery.

Table 12. Overload Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Input current on any port pin during overload condition	I OV SR	-5	–	5	mA
Absolute sum of all input circuit currents during overload condition	I OVS SR	–	–	25	mA

Figure 10

shows the path of the input currents during overload via the ESD protection structures. The diodes against

V

DDP

and ground are a simplified representation of these ESD protection structures.

Figure 10. Input Overload Current via ESD structures

Table 13

and

Table 14

list input voltages that can be reached under overload conditions. Note that the absolute maximum input voltages as defined in the

Absolute Maximum Ratings

must not be exceeded during overload.

Table 13. PN-Junction Characteristics for positive Overload

Pad Type	IOV= 5 mA
Standard, High-current, AN/DIG_IN	V IN = V DDP + 0.5 V V AIN = V DDP + 0.5 V V AREF = V DDP + 0.5 V
P2.[1,2,6:9,11]	V INP2 = V DDP + 0.3 V

Table 14. PN-Junction Characteristics for negative Overload

Pad Type	IOV = 5 mA
Standard, High-current, AN/DIG_IN	V IN = V SS - 0.5 V V AIN = V SS - 0.5 V V AREF = V SS - 0.5 V
P2.[1,2,6:9,11]	V INP2 = V SS - 0.3 V

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the XMC1200. All parameters specified in the following tables refer to these operating conditions, unless noted otherwise.

Table 15. Operating Conditions Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Ambient Temperature	T A SR	-40	–	85	°C	Temp. Range F
		-40	–	105	°C	Temp. Range X
Digital supply voltage 5	V DDP SR	1.8	–	5.5	V
MCLK Frequency	f MCLK CC	–	–	33.2	MHz	CPU clock
PCLK Frequency	f PCLK CC	–	–	66.4	MHz	Peripherals clock
Short circuit current of digital outputs	I SC SR	-5	–	5	mA
Absolute sum of short circuit currents of the device	Σ I SC_D SR	–	–	25	mA

DC Parameters

Input/Output Characteristics

Table 16

provides the characteristics of the input/output pins of the XMC1200.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Note:
Unless otherwise stated, input DC and AC characteristics, including peripheral timings, assume that the input pads operate with the standard hysteresis.

Table 16. Input/Output Characteristics (Operating Conditions apply)

Parameter	Symbol		Limit Values		Unit	Note/Test Condition
			Min.	Max.
Output low voltage on port pins (with standard pads)	V OLP CC		–	1.0	V	I OL = 11 mA (5 V) I OL = 7 mA (3.3 V)
			–	0.4	V	I OL = 5 mA (5 V) I OL = 3.5 mA (3.3 V)
Output low voltage on high current pads	V OLP1 CC		–	1.0	V	I OL = 50 mA (5 V) I OL = 25 mA (3.3 V)
			–	0.32	V	I OL = 10 mA (5 V)
			–	0.4	V	I OL = 5 mA (3.3 V)
Output high voltage on port pins (with standard pads)	V OHP CC		VDDP - 1.0	–	V	I OH = -10 mA (5 V) I OH = -7 mA (3.3 V)
			VDDP - 0.4	–	V	I OH = -4.5 mA (5 V) I OH = -2.5 mA (3.3 V)
Output high voltage on high current pads	V OHP1 CC		VDDP - 0.32	–	V	I OH = -6 mA (5 V)
			VDDP - 1.0	–	V	I OH = -8 mA (3.3 V)
			VDDP - 0.4	–	V	I OH = -4 mA (3.3 V)
Input low voltage on port pins (Standard Hysteresis)	V ILPS SR		–	0.19 × V DDP	V	CMOS Mode (5 V, 3.3 V & 2.2 V)
Input high voltage on port pins (Standard Hysteresis)	V IHPS SR		0.7 × V DDP	–	V	CMOS Mode (5 V, 3.3 V & 2.2 V)
Input low voltage on port pins (Large Hysteresis)	V ILPL SR		–	0.08 × V DDP	V	CMOS Mode (5 V, 3.3 V & 2.2 V) 15
Input high voltage on port pins (Large Hysteresis)	V IHPL SR		0.85 × V DDP	–	V	CMOS Mode (5 V, 3.3 V & 2.2 V) 15
Rise time on High Current Pad	t HCPR CC		–	9	ns	50 pF @ 5 V
			–	12	ns	50 pF @ 3.3 V
			–	25	ns	50 pF @ 1.8 V
Fall time on High Current Pad 6	t HCPF CC		–	9	ns	50 pF @ 5 V 7
			–	12	ns	50 pF @ 3.3 V 8
			–	25	ns	50 pF @ 1.8 V 9
Rise time on Standard Pad 6	t R CC		–	12	ns	50 pF @ 5 V 10
			–	15	ns	50 pF @ 3.3 V 11
			–	31	ns	50 pF @ 1.8 V 12
Fall time on Standard Pad 6	t F CC		–	12	ns	50 pF @ 5 V
			–	15	ns	50 pF @ 3.3 V
			–	31	ns	50 pF @ 1.8 V
Input Hysteresis 13	HYS CC		0.08 × V DDP	–	V	CMOS Mode (5 V), Standard Hysteresis
			0.03 × V DDP	–	V	CMOS Mode (3.3 V), Standard Hysteresis
			0.02 × V DDP	–	V	CMOS Mode (2.2 V), Standard Hysteresis
			0.5 × V DDP	0.75 × V DDP	V	CMOS Mode(5 V), Large Hysteresis
			0.4 × V DDP	0.75 × V DDP	V	CMOS Mode(3.3 V), Large Hysteresis
			0.2 × V DDP	0.65 × V DDP	V	CMOS Mode(2.2 V), Large Hysteresis
Pin capacitance (digital inputs/outputs)	C IO CC		–	10	pF
Pull-up resistor on port pins	R PUP CC		20	50	kohm	V IN = V SSP
Pull-down resistor on port pins	R PDP CC		20	50	kohm	V IN = V DDP
Input leakage current 14	I OZP CC		-1	1	µA	0 < V IN < V DDP , T A ≤ 105°C
Voltage on any pin during V DDP power off	V PO SR		–	0.3	V
Maximum current per pin (excluding P1, V DDP and V SS )	I MP SR		-10	11	mA	–
Maximum current per high current pins	I MP1A SR		-10	50	mA	–
Maximum current into V DDP (TSSOP28/16, VQFN24)	I MVDD1 SR		–	130	mA	15
Maximum current into V DDP (TSSOP38, VQFN40)	I MVDD2 SR		–	260	mA	15
Maximum current out of V SS (TSSOP28/16, VQFN24)	I MVSS1 SR		–	130	mA	15
Maximum current out of V SS (TSSOP38, VQFN40)	I MVSS2 SR		–	260	mA	15

Analog to Digital Converters (ADC)

Table 17

shows the Analog to Digital Converter (ADC) characteristics.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 17. ADC Characteristics (Operating Conditions apply) ¹⁶

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Supply voltage range (internal reference)	V DD_int SR	2.0	–	3.0	V	SHSCFG.AREF = 11 CALCTR.CALGNSTC = 0C
		3.0	–	5.5	V	SHSCFG.AREF = 10
Supply voltage range (external reference)	V DD_ext SR	3.0	–	5.5	V	SHSCFG.AREF = 00
Analog input voltage range	V AIN SR	V SSP - 0.05	–	V DDP + 0.05	V
Auxiliary analog reference ground	V REFGND SR	V SSP - 0.05	–	1.0	V	G0CH0
		V SSP - 0.05	–	0.2	V	G1CH0
Internal reference voltage (full scale value)	V REFINT CC	5			V
Switched capacitance of an analog input	C AINS CC	–	1.2	2	pF	GNCTRxz.GAINy = 00 (unity gain)
		–	1.2	2	pF	GNCTRxz.GAINy = 01 (gain g1)
		–	4.5	6	pF	GNCTRxz.GAINy = 10 (gain g2)
		–	4.5	6	pF	GNCTRxz.GAINy = 11 (gain g3)
Total capacitance of an analog input	C AINT CC	–	–	10	pF
Total capacitance of the reference input	C AREFT CC	–	–	10	pF
Gain settings	G IN CC	1			–	GNCTRxz.GAINy = 00 (unity gain)
		3			–	GNCTRxz.GAINy = 01 (gain g1)
		6			–	GNCTRxz.GAINy = 10 (gain g2)
		12			–	GNCTRxz.GAINy = 11 (gain g3)
Sample Time	t sample CC	3	–	–	1/ f ADC	V DD = 5.0 V
		3	–	–	1/ f ADC	V DD = 3.3 V
		30	–	–	1/ f ADC	V DD = 2.0 V
Sigma delta loop hold time	t SD_hold CC	20	–	–	µs	Residual charge stored in an active sigma delta loop remains available
Conversion time in fast compare mode	t CF CC	9			1/ f ADC
Conversion time in 12-bit mode	t C12 CC	20			1/ f ADC	17
Maximum sample rate in 12-bit mode	f C12 CC	–	–	f ADC /42.5	–	1 sample pending
		–	–	f ADC /62.5	–	2 samples pending
Conversion time in 10-bit mode	t C10 CC	18			1/ f ADC	17
Maximum sample rate in 10-bit mode 18	f C10 CC	–	–	f ADC /40.5	–	1 sample pending
		–	–	f ADC /58.5	–	2 samples pending
Conversion time in 8-bit mode	t C8 CC	16			1/ f ADC	17
Maximum sample rate in 8-bit mode 18	f C8 CC	–	–	f ADC /38.5	–	1 sample pending
		–	–	f ADC /54.5	–	2 samples pending
RMS noise 19	EN RMS CC	–	1.5	–	LSB12	DC input, V DD = 5.0 V, V AIN = 2.5 V, 25°C
DNL error	EA DNL CC	–	±2.0	–	LSB12
INL error	EA INL CC	–	±4.0	–	LSB12
Gain error with external reference	EA GAIN CC	–	±0.5	–	%	SHSCFG.AREF = 00 (calibrated)
Gain error with internal reference 20	EA GAIN CC	–	±3.6	–	%	SHSCFG.AREF = 1X (calibrated), -40°C - 105°C
		–	±2.0	–	%	SHSCFG.AREF = 1X (calibrated), 0°C - 85°C
Offset error	EA OFF CC	–	±8.0	–	mV	Calibrated, V DD = 5.0 V

Figure 11. ADC Voltage Supply

Out of Range Comparator (ORC) Characteristics

The Out-of-Range Comparator (ORC) triggers on analog input voltages (

V

AIN

) above the

V

DDP

on selected input pins (ORCx.AIN) and generates a service request trigger (ORCx.OUT).

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 18. Out of Range Comparator (ORC) Characteristics (Operating Conditions apply;

V_DDP = 3.0 V - 5.5 V; C_L = 0.25 pF)

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
DC Switching Level	V ODC CC	54	–	183	mV	V AIN ≥ V DDP + V ODC
Hysteresis	V OHYS CC	15	–	54	mV
Always detected Overvoltage Pulse	t OPDD CC	103	–	–	ns	V AIN ≥ V DDP + 150 mV
		88	–	–	ns	V AIN ≥ V DDP + 350 mV
Never detected Overvoltage Pulse	t OPDN CC	–	–	21	ns	V AIN ≥ V DDP + 150 mV
		–	–	11	ns	V AIN ≥ V DDP + 350 mV
Detection Delay of a persistent Overvoltage	t ODD CC	39	–	132	ns	V AIN ≥ V DDP + 150 mV
		31	–	121	ns	V AIN ≥ V DDP + 350 mV
Release Delay	t ORD CC	44	–	240	ns	V AIN ≤ V DDP ; V DDP = 5 V
		57	–	340	ns	V AIN ≤ V DDP ; V DDP = 3.3 V
Enable Delay	t OED CC	–	–	300	ns	ORCCTRL.ENORCx = 1

Figure 12. ORCx.OUT Trigger Generation

Figure 13. ORC Detection Ranges

Analog Comparator Characteristics

Table 19

below shows the Analog Comparator characteristics.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 19. Analog Comparator Characteristics (Operating Conditions apply)

Parameter	Symbol		Limit Values			Unit	Note/Test Condition
			Min.	Typ.	Max.
Input Voltage	V CMP SR		-0.05	–	V DDP + 0.05	V
Input Offset	V CMPOFF CC		–	+/-3	–	mV	High power mode Δ V CMP < 200 mV
			–	+/-20	–	mV	Low power mode Δ V CMP < 200 mV
Propagation Delay	t PDELAY CC		–	25	–	ns	High power mode, Δ V CMP = 100 mV
			–	80	–	ns	High power mode, Δ V CMP = 25 mV
			–	250	–	ns	Low power mode, Δ V CMP = 100 mV
			–	700	–	ns	Low power mode, Δ V CMP = 25 mV
Current Consumption	I ACMP CC		–	100	–	µA	First active ACMP in high power mode, Δ V CMP > 30 mV
			–	66	–	µA	Each additional ACMP in high power mode, Δ V CMP > 30 mV
			–	10	–	µA	First active ACMP in low power mode
			–	6	–	µA	Each additional ACMP in low power mode
Input Hysteresis	V HYS CC		–	+/-15	–	mV
Filter Delay 21	t FDELAY CC		–	5	–	ns

Temperature Sensor Characteristics

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 20. Temperature Sensor Characteristics

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Measurement time	t M CC	–	–	10	ms
Temperature sensor range	T SR SR	-40	–	115	°C
Sensor Accuracy 22	T TSAL CC	-6	–	6	°C	T J > 20°C
		-10	–	10	°C	0°C ≤ T J ≤ 20°C
		-18	–	18	°C	-25°C ≤ TJ < 0°C
		-31	–	31	°C	-40°C ≤ TJ < -25°C
Start-up time after enabling	t TSSTE SR	–	–	15	µs

Power Supply Current

The total power supply current defined below consists of a leakage and a switching component.

Application relevant values are typically lower than those given in the following tables, and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations).

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 21. Power Supply Parameters; V_DDP = 5 V

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ. 23	Max.
Active mode current Peripherals enabled f MCLK / f PCLK in MHz 24	I DDPAE CC	–	8.8	11.5	mA	32/64
		–	7.7	–	mA	24/48
		–	6.4	–	mA	16/32
		–	5.3	–	mA	8/16
		–	3.9	–	mA	1/1
Active mode current Peripherals disabled f MCLK / f PCLK in MHz 25	I DDPAD CC	–	4.8	–	mA	32/64
		–	4.1	–	mA	24/48
		–	3.3	–	mA	16/32
		–	2.6	–	mA	8/16
		–	1.5	–	mA	1/1
Active mode current Code execution from RAM Flash is powered down f MCLK / f PCLK in MHz	I DDPAR CC	–	6.7	–	mA	32/64
		–	5.8	–	mA	24/48
		–	4.9	–	mA	16/32
		–	4.0	–	mA	8/16
		–	3.1	–	mA	1/1
Sleep mode current Peripherals clock enabled f MCLK / f PCLK in MHz 26	I DDPSE CC	–	6.2	–	mA	32/64
			5.6	–	mA	24/48
			5.0	–	mA	16/32
			4.4	–	mA	8/16
			3.7	–	mA	1/1
Sleep mode current Peripherals clock disabled Flash active f MCLK / f PCLK in MHz 27	I DDPSD CC	–	1.8	–	mA	32/64
			1.7	–	mA	24/48
			1.6	–	mA	16/32
			1.5	–	mA	8/16
			1.4	–	mA	1/1
Sleep mode current Peripherals clock disabled Flash powered down f MCLK / f PCLK in MHz 28	I DDPSR CC	–	1.2	–	mA	32/64
			1.1	–	mA	24/48
			1.0	–	mA	16/32
			0.8	–	mA	8/16
			0.7	–	mA	1/1
Deep Sleep mode current 29	I DDPDS CC	–	0.24	–	mA
Wake-up time from Sleep to Active mode 30	t SSA CC	–	6	–	cycles
Wake-up time from Deep Sleep to Active mode 31	t DSA CC	–	280	–	µsec

Figure 14

shows typical graphs for active mode supply current for

V

DDP

= 5 V,

V

DDP

= 3.3 V,

V

DDP

= 1.8 V across different clock frequencies.

Figure 14. Active mode, a) peripherals clocks enabled, b) peripherals clocks disabled: Supply current I_DDPA

over supply voltage V_DDP for different clock frequencies

Figure 15

shows typical graphs for sleep mode current for

V

DDP

= 5 V,

V

DDP

= 3.3 V,

V

DDP

= 1.8 V across different clock frequencies.

Figure 15. Sleep mode, peripherals clocks disabled, Flash powered down: Supply current

I_DDPSR over supply voltage V_DDP for different clock frequencies

Table 22

provides the active current consumption of some modules operating at 5 V power supply at 25°C. The typical values shown are used as a reference guide on the current consumption when these modules are enabled.

Table 22. Typical Active Current Consumption

Active Current Consumption	Symbol	Limit Values	Unit	Note/Test Condition
		Typ.
Baseload current	I CPUDDC	5.04	mA	Modules including Core, SCU, PORT, memories, ANATOP 32
VADC and SHS	I ADCDDC	3.4	mA	Set CGATCLR0.VADC to 1 33
USIC0	I USIC0DDC	0.87	mA	Set CGATCLR0.USIC0 to 1 34
CCU40	I CCU40DDC	0.94	mA	Set CGATCLR0.CCU40 to 1 35
LEDTSx	I LTSxDDC	0.76	mA	Set CGATCLR0.LEDTSx to 1 36
BCCU0	I BCCU0DDC	0.24	mA	Set CGATCLR0.BCCU0 to 1 37
WDT	I WDTDDC	0.03	mA	Set CGATCLR0.WDT to 1 38
RTC	I RTCDDC	0.01	mA	Set CGATCLR0.RTC to 1 39

Flash Memory Parameters

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 23. Flash Memory Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Erase Time per page/sector	t ERASE CC	6.8	7.1	7.6	ms
Program time per block	t PSER CC	102	152	204	µs
Wake-Up time	t WU CC	–	32.2	–	µs
Read time per word	t a CC	–	50	–	ns
Data Retention Time	t RET CC	10	–	–	years	Max. 100 erase/program cycles
Flash Wait States 40	N WSFLASH CC	0	0	0		f MCLK = 8 MHz
		0	1	1		f MCLK = 16 MHz
		1	1.3	2		f MCLK = 32 MHz
Fixed Flash Wait States configured in bit NVM_NVMCONF.WS	N FWSFLASH SR	0	0	1		NVM_CONFIG1.FIXWS = 1 , f MCLK ≤ 16 MHz
		1	1	1		NVM_CONFIG1.FIXWS = 1 , 16 MHz < f MCLK ≤ 32 MHz
Erase Cycles	N ECYC CC	–	–	5*10 4	cycles	Sum of page and sector erase cycles
Total Erase Cycles	N TECYC CC	–	–	2*10 6	cycles

AC Parameters

Testing Waveforms

Figure 16. Rise/Fall Time Parameters

Figure 17. Testing Waveform, Output Delay

Figure 18. Testing Waveform, Output High Impedance

Power-Up and Supply Monitoring Characteristics

Table 24

provides the characteristics of the power-up and supply monitoring in XMC1200.

The guard band between the lowest valid operating voltage and the brownout reset threshold provides a margin for noise immunity and hysteresis. The electrical parameters may be violated while

V

DDP

is outside its operating range.

The brownout detection triggers a reset within the defined range. The prewarning detection can be used to trigger an early warning and issue corrective and/or fail-safe actions in case of a critical supply voltage drop.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 24. Power-Up and Supply Monitoring Parameters (Operating Conditions apply) ⁴¹

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
V DDP ramp-up time	t RAMPUP SR	V DDP / S VDDPrise	–	10 7	µs
V DDP slew rate	S VDDPOP SR	0	–	0.1	V/µs	Slope during normal operation
	S VDDP10 SR	0	–	10	V/µs	Slope during fast transient within +/-10% of V DDP
	S VDDPrise SR	0	–	10	V/µs	Slope during power-on or restart after brownout event
	S VDDPfall 42 SR	0	–	0.25	V/µs	Slope during supply falling out of the +/-10% limits 43
V DDP prewarning voltage	V DDPPW CC	2.1	2.25	2.4	V	ANAVDEL.VDEL_SELECT = 00
		2.85	3	3.15	V	ANAVDEL.VDEL_SELECT = 01
		4.2	4.4	4.6	V	ANAVDEL.VDEL_SELECT = 10
V DDP brownout reset voltage	V DDPBO CC	1.55	1.62	1.75	V	calibrated, before user code starts running
V DDP voltage to ensure defined pad states	V DDPPA CC	–	1.0	–	V
Start-up time from power-on reset	t SSW SR	–	320	–	µs	Time to the first user code instruction in all start-up modes 44
BMI program time	t BMI SR	–	8.25	–	ms	Time taken from a user-triggered system reset after BMI installation is requested

Figure 19. Supply Threshold Parameters

On-Chip Oscillator Characteristics

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 25

provides the characteristics of the 64 MHz clock output from the digital controlled oscillator, DCO1 in XMC1200.

Table 25. 64 MHz DCO1 Characteristics (Operating Conditions apply)

Parameter	Symbol	Limit Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Nominal frequency	f NOM CC	–	64	–	MHz	under nominal conditions 45 after trimming
Accuracy 46	Δ f LT CC	-1.7	–	3.4	%	with respect to f NOM (typ), over temperature (0°C to 85°C)
		-3.9	–	4.0	%	with respect to f NOM (typ), over temperature (-40°C to 105°C)

Figure 20

shows the typical curves for the accuracy of DCO1, with and without calibration based on temperature sensor, respectively.

Figure 20. Typical DCO1 accuracy over temperature

Table 26

provides the characteristics of the 32 kHz clock output from digital controlled oscillators, DCO2 in XMC1200.

Table 26. 32 kHz DCO2 Characteristics (Operating Conditions apply)

Parameter	Symbol	Limit Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Nominal frequency	f NOM CC	–	32.75	–	kHz	under nominal conditions 47 after trimming
Accuracy	Δ f LT CC	-1.7	–	3.4	%	with respect to f NOM (typ), over temperature (0°C to 85°C)
		-3.9	–	4.0	%	with respect to f NOM (typ), over temperature (-40°C to 105°C)

Serial Wire Debug Port (SW-DP) Timing

The following parameters are applicable for communication through the SW-DP interface.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 27. SWD Interface Timing Parameters(Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
SWDCLK high time	t 1 SR	50	–	500000	ns	–
SWDCLK low time	t 2 SR	50	–	500000	ns	–
SWDIO input setup to SWDCLK rising edge	t 3 SR	10	–	–	ns	–
SWDIO input hold after SWDCLK rising edge	t 4 SR	10	–	–	ns	–
SWDIO output valid time after SWDCLK rising edge	t 5 CC	–	–	68	ns	C L = 50 pF
		–	–	62	ns	C L = 30 pF
SWDIO output hold time from SWDCLK rising edge	t 6 CC	4	–	–	ns

Figure 21. SWD Timing

SPD Timing Requirements

The optimum SPD decision time between

0

and

1

is 0.75 µs. With this value the system has maximum robustness against frequency deviations of the sampling clock on tool and on device side. However it is not always possible to exactly match this value with the given constraints for the sample clock. For instance for a oversampling rate of 4, the sample clock will be 8 MHz and in this case the closest possible effective decision time is 5.5 clock cycles (0.69 µs).

Table 28. Optimum Number of Sample Clocks for SPD

Sample Freq.	Sampling Factor	Sample Clocks 0	Sample Clocks 1	Effective Decision Time 48	Remark
8 MHz	4	1 to 5	6 to 12	0.69 µs	The other closest option (0.81 µs) for the effective decision time is less robust.

For a balanced distribution of the timing robustness of SPD between tool and device, the timing requirements for the tool are:

• Frequency deviation of the sample clock is +/- 5%

• Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal sample frequency)

Peripheral Timings

Note:

These parameters are not subject to production test, but verified by design and/or characterization.

Synchronous Serial Interface (USIC SSC) Timing

The following parameters are applicable for a USIC channel operated in SSC mode.

Note:
Operating Conditions apply.

Table 29. USIC SSC Master Mode Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
SCLKOUT master clock period	t CLK CC	62.5	–	–	ns
Slave select output SELO active to first SCLKOUT transmit edge	t 1 CC	80	–	–	ns
Slave select output SELO inactive after last SCLKOUT receive edge	t 2 CC	0	–	–	ns
Data output DOUT[3:0] valid time	t 3 CC	-10	–	10	ns
Receive data input DX0/DX[5:3] setup time to SCLKOUT receive edge	t 4 SR	80	–	–	ns
Data input DX0/DX[5:3] hold time from SCLKOUT receive edge	t 5 SR	0	–	–	ns

Table 30. USIC SSC Slave Mode Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
DX1 slave clock period	t CLK SR	125	–	–	ns
Select input DX2 setup to first clock input DX1 transmit edge	t 10 SR	10	–	–	ns
Select input DX2 hold after last clock input DX1 receive edge 49	t 11 SR	10	–	–	ns
Receive data input DX0/DX[5:3] setup time to shift clock receive edge 49	t 12 SR	10	–	–	ns
Data input DX0/DX[5:3] hold time from clock input DX1 receive edge 49	t 13 SR	10	–	–	ns
Data output DOUT[3:0] valid time	t 14 CC	–	–	80	ns

Figure 22. USIC - SSC Master/Slave Mode Timing

Note:

This timing diagram shows a standard configuration, for which the slave select signal is low-active, and the serial clock signal is not shifted and not inverted.

Inter-IC (IIC) Interface Timing

The following parameters are applicable for a USIC channel operated in IIC mode.

Note:
Operating Conditions apply.

Table 31. USIC IIC Standard Mode Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Fall time of both SDA and SCL	t 1 CC/SR	–	–	300	ns
Rise time of both SDA and SCL	t 2 CC/SR	–	–	1000	ns
Data hold time	t 3 CC/SR	0	–	–	µs
Data set-up time	t 4 CC/SR	250	–	–	ns
LOW period of SCL clock	t 5 CC/SR	4.7	–	–	µs
HIGH period of SCL clock	t 6 CC/SR	4.0	–	–	µs
Hold time for (repeated) START condition	t 7 CC/SR	4.0	–	–	µs
Set-up time for repeated START condition	t 8 CC/SR	4.7	–	–	µs
Set-up time for STOP condition	t 9 CC/SR	4.0	–	–	µs
Bus free time between a STOP and START condition	t 10 CC/SR	4.7	–	–	µs
Capacitive load for each bus line	C b SR	–	–	400	pF

Table 32. USIC IIC Fast Mode Timing ⁵¹

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Fall time of both SDA and SCL	t 1 CC/SR	20 + 0.1* C b 52	–	300	ns
Rise time of both SDA and SCL	t 2 CC/SR	20 + 0.1* C b	–	300	ns
Data hold time	t 3 CC/SR	0	–	–	µs
Data set-up time	t 4 CC/SR	100	–	–	ns
LOW period of SCL clock	t 5 CC/SR	1.3	–	–	µs
HIGH period of SCL clock	t 6 CC/SR	0.6	–	–	µs
Hold time for (repeated) START condition	t 7 CC/SR	0.6	–	–	µs
Set-up time for repeated START condition	t 8 CC/SR	0.6	–	–	µs
Set-up time for STOP condition	t 9 CC/SR	0.6	–	–	µs
Bus free time between a STOP and START condition	t 10 CC/SR	1.3	–	–	µs
Capacitive load for each bus line	C b SR	–	–	400	pF

Figure 23. USIC IIC Stand and Fast Mode Timing

Inter-IC Sound (IIS) Interface Timing

The following parameters are applicable for a USIC channel operated in IIS mode.

Note:
Operating Conditions apply.

Table 33. USIC IIS Master Transmitter Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Clock period	t 1 CC	2/ f MCLK	–	–	ns	V DDP ≥ 3 V
		4/ f MCLK	–	–	ns	V DDP < 3 V
Clock HIGH	t 2 CC	0.35 × t 1min	–	–	ns
Clock Low	t 3 CC	0.35 × t 1min	–	–	ns
Hold time	t 4 CC	0	–	–	ns
Clock rise time	t 5 CC	–	–	0.15 × t 1min	ns

Figure 24. USIC IIS Master Transmitter Timing

Table 34. USIC IIS Slave Receiver Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Clock period	t 6 SR	4/ f MCLK	–	–	ns
Clock HIGH	t 7 SR	0.35 × t 6min	–	–	ns
Clock Low	t 8 SR	0.35 × t 6min	–	–	ns
Set-up time	t 9 SR	0.2 × t 6min	–	–	ns
Hold time	t 10 SR	10	–	–	ns

Figure 25. USIC IIS Slave Receiver Timing

Package and Reliability

The XMC1200 is a member of the XMC1000 Family of microcontrollers. It is also compatible to a certain extent with members of similar families or subfamilies.

Each package is optimized for the device it houses. Therefore, there may be slight differences between packages of the same pin-count but for different device types. In particular, the size of the exposed die pad may vary.

If different device types are considered or planned for an application, it must be ensured that the board layout fits all packages under consideration.

Package Parameters

Table 35

provides the thermal characteristics of the packages used in XMC1200.

Table 35. Thermal Characteristics of the Packages

Parameter	Symbol	Limit Values		Unit	Package Types
		Min.	Max.
Exposed Die Pad Dimensions	Ex × Ey CC	–	2.7 × 2.7	mm	PG-VQFN-24-19
		–	3.7 × 3.7	mm	PG-VQFN-40-13
Thermal resistance Junction-Ambient	R ΘJA CC	–	104.6	K/W	PG-TSSOP-16-8
		–	83.2	K/W	PG-TSSOP-28-16 53
		–	70.3	K/W	PG-TSSOP-38-9 53
		–	46.0	K/W	PG-VQFN-24-19 53
		–	38.4	K/W	PG-VQFN-40-13 53

Note:
For electrical reasons, it is required to connect the exposed pad to the board ground V_SSP, independent of EMC and thermal requirements.

Thermal Considerations

When operating the XMC1200 in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage.

The maximum heat that can be dissipated depends on the package and its integration into the target board. The “Thermal resistance

R

ΘJA

” quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 115°C.

The difference between junction temperature and ambient temperature is determined by

Δ

T

= (

P

INT

+

P

IOSTAT

+

P

IODYN

) ×

R

ΘJA

The internal power consumption is defined as

P

INT

=

V

DDP

×

I

DDP

(switching current and leakage current).

The static external power consumption caused by the output drivers is defined as

P

IOSTAT

= Σ((

V

DDP

-

V

OH

) ×

I

OH

) + Σ(

V

OL

×

I

OL

)

The dynamic external power consumption caused by the output drivers (

P

IODYN

) depends on the capacitive load connected to the respective pins and their switching frequencies.

If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation:

• Reduce

  V

  DDP

  , if possible in the system

• Reduce the system frequency

• Reduce the number of output pins

• Reduce the load on active output drivers

Package Outlines

Figure 26. PG-TSSOP-38-9

Figure 27. PG-TSSOP-28-16

Figure 28. PG-TSSOP-16-8

Figure 29. PG-VQFN-24-19

Figure 30. PG-VQFN-40-13

All dimensions in mm.

Quality Declaration

Table 36

shows the characteristics of the quality parameters in the XMC1200.

Table 36. Quality Parameters

Parameter	Symbol	Limit Values		Unit	Notes
		Min.	Max.
ESD susceptibility according to Human Body Model (HBM)	V HBM SR	–	4000	V	Conforming to EIA/JESD22-A114-B
ESD susceptibility according to Charged Device Model (CDM) pins	V CDM SR	–	1000	V	Conforming to JESD22-C101-C
Moisture sensitivity level	MSL CC	–	–	–	JEDEC J-STD-020D
TSSOP-16, TSSOP-28, TSSOP-38			3
VQFN-24, VQFN-40			1
Soldering temperature	T SDR SR	–	260	°C	Profile according to JEDEC J-STD-020D

Revision history

Document revision	Date	Description of changes
V1.8	2016-09	In Absolute Maximum Ratings renamed parameter V CM to V INP2 , as the limitation is related to most P2 pins, also if no ACMP is available. Clarified limit to pins P2.[1,2,6:9,11] in Overload specification.
V1.9	2025-01-22	Updated template. Updated Moisture sensitivity level in Quality Declaration section.
V2.0	2025-06-30	Updated ESD ratings in Table 36

1

Features that are not included in this table are available in all the derivatives.

2

Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port I/O Function table.

3

Excluding port pins P2.[1,2,6,7,8,9,11].

4

Applicable to port pins P2.[1,2,6,7,8,9,11].

5

See also the Supply Monitoring thresholds,

Chapter 3.3.2

.

6

Rise/Fall time parameters are taken with 10% - 90% of supply.

7

Additional rise/fall time valid for

C

L

= 50 pF -

C

L

= 100 pF @ 0.150 ns/pF at 5 V supply voltage.

8

Additional rise/fall time valid for

C

L

= 50 pF -

C

L

= 100 pF @ 0.205 ns/pF at 3.3 V supply voltage.

9

Additional rise/fall time valid for

C

L

= 50 pF -

C

L

= 100 pF @ 0.445 ns/pF at 1.8 V supply voltage.

10

Additional rise/fall time valid for

C

L

= 50 pF -

C

L

= 100 pF @ 0.225 ns/pF at 5 V supply voltage.

11

Additional rise/fall time valid for C_L= 50 pF -

C

L

= 100 pF @ 0.288 ns/pF at 3.3 V supply voltage.

12

Additional rise/fall time valid for

C

L

= 50 pF -

C

L

= 100 pF @ 0.588 ns/pF at 1.8 V supply voltage.

13

Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise.

14

An additional error current (

I

INJ

)

will flow if an overload current flows through an adjacent pin.

15

However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when

V

DDP

is powered off.

16

The parameters are defined for ADC clock frequency

f

SH

= 32 MHz, SHSCFG.DIVS =

0000

. Usage of any other frequencies may affect the ADC performance.

17

No pending samples assumed, excluding sampling time and calibration.

18

Includes synchronization and calibration (average of gain and offset calibration).

19

This parameter can also be defined as an SNR value: SNR[dB] = 20 × log(

A

MAXeff

/

N

RMS

).

With

A

MAXeff

= 2

N

/2, SNR[dB] = 20 × log (2048/

N

RMS

) [N = 12].

N

RMS

= 1.5 LSB12, therefore, equals SNR = 20 × log (2048/1.5) = 62.7 dB.

20

Includes error from the reference voltage.

21

Total Analog Comparator Delay is the sum of Propagation Delay and Filter Delay.

22

The temperature sensor accuracy is independent of the supply voltage.

23

The typical values are measured at

T

A

= + 25°C and

V

DDP

= 5 V.

24

CPU and all peripherals clock enabled, Flash is in active mode.

25

CPU enabled, all peripherals clock disabled, Flash is in active mode.

26

CPU in sleep, all peripherals clock enabled and Flash is in active mode.

27

CPU in sleep, Flash is in active mode.

28

CPU in sleep, Flash is powered down and code executed from RAM after wake-up.

29

CPU in sleep, peripherals clock disabled, Flash is powered down and code executed from RAM after wake-up.

30

CPU in sleep, Flash is in active mode during sleep mode.

31

CPU in sleep, Flash is in powered down mode during deep sleep mode.

32

Baseload current is measured with device running in user mode, MCLK=PCLK=32 MHz, with an endless loop in the flash memory. The clock to the modules stated in CGATSTAT0 are gated.

33

Active current is measured with: module enabled, MCLK=32 MHz, running in auto-scan conversion mode.

34

Active current is measured with: module enabled, alternating messages sent to PC at 57.6 kbaud every 200 ms.

35

Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU4 slice for PWM switching from 1500 Hz and 1000 Hz at regular intervals, 1 CCU4 slice in capture mode for reading period and duty cycle.

36

Active current is measured with: module enabled, MCLK=32 MHz, 1 LED column, 6 LED/TS lines, Pad Scheme A with large pad hysteresis config, time slice duration = 1.048 ms.

37

Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64 MHz, FCLK=0.8 MHz, Normal mode (BCCU Clk = FCLK/4), 3 BCCU Channels and 1 Dimming Engine, change color or dim every 1 s.

38

Active current is measured with: module enabled, MCLK=32 MHz, time-out mode; WLB = 0, WUB = 0x00008000; WDT serviced every 1 s.

39

Active current is measured with: module enabled, MCLK=32 MHz, Periodic interrupt enabled.

40

Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical values are calculated from the execution of the Dhrystone benchmark program.

41

Not all parameters are 100% tested, but are verified by design/characterization.

42

A capacitor of at least 100 nF has to be added between

V

DDP

and

V

SSP

to fulfill the requirement as stated for this parameter.

43

Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forwarded only to the chip. A larger capacitor value has to be chosen if the power source sink a current.

44

This values does not include the ramp-up time. During start-up firmware execution, MCLK is running at 32 MHz and the clocks to peripheral as specified in register CGATSTAT0 are gated.

45

The deviation is relative to the factory trimmed frequency at nominal

V

DDC

and

T

A

= + 25°C.

46

The accuracy of the DCO1 oscillator can be further improved through alternative methods, refer to XMC1000 Oscillator Handling Application Note.

47

The deviation is relative to the factory trimmed frequency at nominal

V

DDC

and

T

A

= + 25°C.

48

Nominal sample frequency period multiplied with 0.5 + (max. number of

0

sample clocks).

49

These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0).

50

Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximately 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

51

Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximately 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

52

C

b

refers to the total capacitance of one bus line in pF.

53

Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered.