XMC1100 AB-Step

XMC1000 Family

Microcontroller Series for Industrial Applications

ARM® Cortex®-M0

32-bit processor core

Datasheet

About this Document

This datasheet is addressed to embedded hardware and software developers. It provides the reader with detailed descriptions about the ordering designations, available features, electrical and physical characteristics of the XMC1100 series devices.

The document describes the characteristics of a superset of the XMC1100 series devices. For simplicity, the various device types are referred to by the collective term XMC1100 throughout this document.

XMC1000 Family User Documentation

The set of user documentation includes:

• Reference Manual

  • describes the functionality of the superset of devices.

• Datasheets

  • list the complete ordering designations, available features and electrical characteristics of derivative devices.

• Errata Sheets

  • list deviations from the specifications given in the related Reference Manual or Datasheets. Errata Sheets are provided for the superset of devices.

Attention:

Please consult all parts of the documentation set to attain consolidated knowledge about your device.

Application related guidance is provided by Users Guides and Application Notes .

Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions of those documents.

Summary of Features

The XMC1100 devices are members of the XMC1000 Family of microcontrollers based on the ARM Cortex-M0 processor core. The XMC1100 series devices are designed for general purpose applications.

Figure 1. System Block Diagram

CPU Subsystem

• CPU Core

  • High-performance 32-bit ARM Cortex-M0 CPU

  • Most 16-bit Thumb and subset of 32-bit Thumb2 instruction set

  • Single cycle 32-bit hardware multiplier

  • System timer (SysTick) for Operating System support

  • Ultra low power consumption

• Nested Vectored Interrupt Controller (NVIC)

• Event Request Unit (ERU) for processing of external and internal service requests

On-Chip Memories

• 8 kbytes on-chip ROM

• 16 kbytes on-chip high-speed SRAM

• up to 200 KB on-chip Flash program and data memory

On-Chip Peripherals

• Two Universal Serial Interface Channels (USIC), usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces

• A/D Converters

  • up to 12 analog input pins and channels

  • 12-bit analog to digital converter

• Capture/Compare Units 4 (CCU4) for use as general purpose timers

• Window Watchdog Timer (WDT) for safety sensitive applications

• Real Time Clock module with alarm support (RTC)

• System Control Unit (SCU) for system configuration and control

• Pseudo random number generator (PRNG) for fast random data generation

• Temperature Sensor (TSE)

Input/Output Lines With Individual Bit Controllability

• Tri-stated in input mode

• Push/pull or open drain output mode

• Configurable pad hysteresis

Debug System

• Access through the standard ARM serial wire debug (SWD) or the single pin debug (SPD) interface

• A breakpoint unit (BPU) supporting up to 4 hardware breakpoints

• A watchpoint unit (DWT) supporting up to 2 watchpoints

Ordering Information

The ordering code for an Infineon microcontroller provides an exact reference to a specific product. The code “XMC1<DDD>-<Z><PPP><T><FFFF>” identifies:

• <DDD> the derivatives function set

• <Z> the package variant

  • T: TSSOP

  • Q: VQFN

• <PPP> package pin count

• <T> the temperature range:

  • F: -40°C to 85°C

  • X: -40°C to 105°C

• <FFFF> the Flash memory size

For ordering codes for the XMC1100 please contact your sales representative or local distributor.

This document describes several derivatives of the XMC1100 series, some descriptions may not apply to a specific product. Please see Table 1 .

For simplicity the term XMC1100 is used for all derivatives throughout this document.

Device Types

These device types are available and can be ordered through Infineon’s direct and/or distribution channels.

Table 1. Synopsis of XMC1100 Device Types

Derivative	Package	Flash Kbytes	SRAM Kbytes
XMC1100-T016F0008	PG-TSSOP-16-8	8	16
XMC1100-T016F0016	PG-TSSOP-16-8	16	16
XMC1100-T016F0032	PG-TSSOP-16-8	32	16
XMC1100-T016F0064	PG-TSSOP-16-8	64	16
XMC1100-T016X0016	PG-TSSOP-16-8	16	16
XMC1100-T016X0032	PG-TSSOP-16-8	32	16
XMC1100-T016X0064	PG-TSSOP-16-8	64	16
XMC1100-T038F0016	PG-TSSOP-38-9	16	16
XMC1100-T038F0032	PG-TSSOP-38-9	32	16
XMC1100-T038F0064	PG-TSSOP-38-9	64	16
XMC1100-T038X0064	PG-TSSOP-38-9	64	16
XMC1100-T038X0128	PG-TSSOP-38-9	128	16
XMC1100-T038X0200	PG-TSSOP-38-9	200	16
XMC1100-Q024F0008	PG-VQFN-24-19	8	16
XMC1100-Q024F0016	PG-VQFN-24-19	16	16
XMC1100-Q024F0032	PG-VQFN-24-19	32	16
XMC1100-Q024F0064	PG-VQFN-24-19	64	16
XMC1100-Q040F0016	PG-VQFN-40-13	16	16
XMC1100-Q040F0032	PG-VQFN-40-13	32	16
XMC1100-Q040F0064	PG-VQFN-40-13	64	16

Device Type Features

The following table lists the available features per device type.

Table 2.Features of XMC1100 Device Types ¹

Derivative	ADC channel
XMC1100-T016	6
XMC1100-T038	12
XMC1100-Q024	8
XMC1100-Q040	12

Table 3. ADC Channels

Package	VADC0 G0	VADC0 G1
PG-TSSOP-16	CH0..CH5	–
PG-TSSOP-38	CH0..CH7	CH1, CH5 .. CH7
PG-VQFN-24	CH0..CH7	–
PG-VQFN-40	CH0..CH7	CH1, CH5 .. CH7

Chip Identification Number

The Chip Identification Number allows software to identify the marking. It is a 8 words value with the most significant 7 words stored in Flash configuration sector 0 (CS0) at address location:

1000 0F00

(MSB) -

1000 0F1B

(LSB). The least significant word and most significant word of the Chip Identification Number are the value of registers DBGROMID and IDCHIP, respectively.

Table 4. XMC1100 Chip Identification Number

Derivative	Value	Marking
XMC1100-T016F0008	00011032 01CF00FF 00001F37 00000000 00000C00 00001000 00003000 201ED083	AB
XMC1100-T016F0016	00011032 01CF00FF 00001F37 00000000 00000C00 00001000 00005000 201ED083	AB
XMC1100-T016F0032	00011032 01CF00FF 00001F37 00000000 00000C00 00001000 00009000 201ED083	AB
XMC1100-T016F0064	00011032 01CF00FF 00001F37 00000000 00000C00 00001000 00011000 201ED083	AB
XMC1100-T016X0016	00011033 01CF00FF 00001F37 00000000 00000C00 00001000 00005000 201ED083	AB
XMC1100-T016X0032	00011033 01CF00FF 00001F37 00000000 00000C00 00001000 00009000 201ED083	AB
XMC1100-T016X0064	00011033 01CF00FF 00001F37 00000000 00000C00 00001000 00011000 201ED083	AB
XMC1100-T038F0016	00011012 01CF00FF 00001F37 00000000 00000C00 00001000 00005000 201ED083	AB
XMC1100-T038F0032	00011012 01CF00FF 00001F37 00000000 00000C00 00001000 00009000 201ED083	AB
XMC1100-T038F0064	00011012 01CF00FF 00001F37 00000000 00000C00 00001000 00011000 201ED083	AB
XMC1100-T038X0064	00011013 01CF00FF 00001F37 00000000 00000C00 00001000 00011000 201ED083	AB
XMC1100-T038X0128	00011013 01CF00FF 00001F37 00000000 00000C00 00001000 00021000 201ED083	AB
XMC1100-T038X0200	00011013 01CF00FF 00001F37 00000000 00000C00 00001000 00033000 201ED083	AB
XMC1100-Q024F0008	00011062 01CF00FF 00001F37 00000000 00000C00 00001000 00003000 201ED083	AB
XMC1100-Q024F0016	00011062 01CF00FF 00001F37 00000000 00000C00 00001000 00005000 201ED083	AB
XMC1100-Q024F0032	00011062 01CF00FF 00001F37 00000000 00000C00 00001000 00009000 201ED083	AB
XMC1100-Q024F0064	00011062 01CF00FF 00001F37 00000000 00000C00 00001000 00011000 201ED083	AB
XMC1100-Q040F0016	00011042 01CF00FF 00001F37 00000000 00000C00 00001000 00005000 201ED083	AB
XMC1100-Q040F0032	00011042 01CF00FF 00001F37 00000000 00000C00 00001000 00009000 201ED083	AB
XMC1100-Q040F0064	00011042 01CF00FF 00001F37 00000000 00000C00 00001000 00011000 201ED083	AB

General Device Information

This section summarizes the logic symbols and package pin configurations with a detailed list of the functional I/O mapping.

Logic Symbols

Figure 2. XMC1100 Logic Symbol for TSSOP-38 and TSSOP-16

Figure 3. XMC1100 Logic Symbol for VQFN-24 and VQFN-40

Pin Configuration and Definition

The following figures summarize all pins, showing their locations on the different packages.

Figure 4. XMC1100 PG-TSSOP-38 Pin Configuration (top view)

Figure 5. XMC1100 PG-TSSOP-16 Pin Configuration (top view)

Figure 6. XMC1100 PG-VQFN-24 Pin Configuration (top view)

Figure 7. XMC1100 PG-VQFN-40 Pin Configuration (top view)

Package Pin Summary

The following general building block is used to describe each pin:

Table 5. Package Pin Mapping Description

Function	Package A	Package B	...	Pad Type
Px.y	N	N		Pad Class

The table is sorted by the “Function” column, starting with the regular Port pins (Px.y), followed by the supply pins.

The following columns, titled with the supported package variants, lists the package pin number to which the respective function is mapped in that package.

The “Pad Type” indicates the employed pad type:

• STD_INOUT (standard bi-directional pads)

• STD_INOUT/AN (standard bi-directional pads with analog input)

• High Current (high current bi-directional pads)

• STD_IN/AN (standard input pads with analog input)

• Power (power supply)

Details about the pad properties are defined in the Electrical Parameters.

Table 6. Package Pin Mapping

Function	VQFN 40	TSSOP 38	VQFN 24	TSSOP 16	Pad Type	Notes
P0.0	23	17	15	7	STD_INOUT
P0.1	24	18	–	–	STD_INOUT
P0.2	25	19	–	–	STD_INOUT
P0.3	26	20	–	–	STD_INOUT
P0.4	27	21	–	–	STD_INOUT
P0.5	28	22	16	8	STD_INOUT
P0.6	29	23	17	9	STD_INOUT
P0.7	30	24	18	10	STD_INOUT
P0.8	33	27	19	11	STD_INOUT
P0.9	34	28	20	12	STD_INOUT
P0.10	35	29	–	–	STD_INOUT
P0.11	36	30	–	–	STD_INOUT
P0.12	37	31	21	–	STD_INOUT
P0.13	38	32	22	–	STD_INOUT
P0.14	39	33	23	13	STD_INOUT
P0.15	40	34	24	14	STD_INOUT
P1.0	22	16	14	–	High Current
P1.1	21	15	13	–	High Current
P1.2	20	14	12	–	High Current
P1.3	19	13	11	–	High Current
P1.4	18	12	–	–	High Current
P1.5	17	11	–	–	High Current
P1.6	16	–	–	–	STD_INOUT
P2.0	1	35	1	15	STD_INOUT/AN
P2.1	2	36	2	–	STD_INOUT/AN
P2.2	3	37	3	–	STD_IN/AN
P2.3	4	38	–	–	STD_IN/AN
P2.4	5	1	–	–	STD_IN/AN
P2.5	6	2	–	–	STD_IN/AN
P2.6	7	3	4	16	STD_IN/AN
P2.7	8	4	5	1	STD_IN/AN
P2.8	9	5	5	1	STD_IN/AN
P2.9	10	6	6	2	STD_IN/AN
P2.10	11	7	7	3	STD_INOUT/AN
P2.11	12	8	8	4	STD_INOUT/AN
VSS	13	9	9	5	Power	Supply GND, ADC reference GND
VDD	14	10	10	6	Power	Supply VDD, ADC reference voltage/ORC reference voltage
VDDP	15	10	10	6	Power	When VDD is supplied, VDDP has to be supplied with the same voltage.
VSSP	31	25	–	–	Power	I/O port ground
VDDP	32	26	–	–	Power	I/O port supply
VSSP	Exp. Pad	–	Exp. Pad	–	Power	Exposed Die Pad The exposed die pad is connected internally to VSSP. For proper operation, it is mandatory to connect the exposed pad to the board ground. For thermal aspects, please refer to the Package and Reliability chapter.

Port I/O Function Description

The following general building block is used to describe the I/O functions of each PORT pin:

Table 7. Port I/O Function Description

Function	Outputs		Inputs
	ALT1	ALTn	Input	Input
P0.0		MODA.OUT	MODC.INA
Pn.y	MODA.OUT		MODA.INA	MODC.INB

Figure 8. Simplified Port Structure

Pn.y is the port pin name, defining the control and data bits/registers associated with it. As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT defines the output value.

Up to seven alternate output functions (ALT1/2/3/4/5/6/7) can be mapped to a single port pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective module, with the pin characteristics controlled by the port registers (within the limits of the connected pad).

The port pin input can be connected to multiple peripherals. Most peripherals have an input multiplexer to select between different possible input sources.

The input path is also active while the pin is configured as output. This allows to feedback an output to on-chip resources without wasting an additional external pin.

Please refer to

Table 9

for the complete Port I/O function mapping.

Hardware Controlled I/O Function Description

The following general building block is used to describe the hardware I/O and pull control functions of each PORT pin:

Table 8. Hardware Controlled I/O Function Description

Function	Outputs	Inputs	Pull Control
	HWO0	HWI0	HW0_PD	HW0_PU
P0.0	MODB.OUT	MODB.INA
Pn.y			$\stackrel{<p>¯</p>}{\mathrm{<p>M</p>}\mathrm{<p>O</p>}\mathrm{<p>D</p>}\mathrm{<p>C</p>}\mathrm{<p>.</p>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}}$	MODC.OUT

By Pn_HWSEL, it is possible to select between different hardware “masters” (HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s). Hardware control overrules settings in the respective port pin registers. Additional hardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by the peripherals can be used to control the pull devices of the pin.

Please refer to

Table 10

for the complete hardware I/O and pull control function mapping.

Table 9. Port I/O Functions

Function	Outputs							Inputs
	ALT1	ALT2	ALT3	ALT4	ALT5	ALT6	ALT7	Input	Input	Input	Input	Input	Input	Input
P0.0	ERU0. PDOUT0		ERU0. GOUT0	CCU40.OUT0		USIC0_CH0. SELO0	USIC0_CH1. SELO0	CCU40.IN0C				USIC0_CH0. DX2A	USIC0_CH1. DX2A
P0.1	ERU0. PDOUT1		ERU0. GOUT1	CCU40.OUT1			SCU. VDROP	CCU40.IN1C
P0.2	ERU0. PDOUT2		ERU0. GOUT2	CCU40.OUT2		VADC0. EMUX02		CCU40.IN2C
P0.3	ERU0. PDOUT3		ERU0. GOUT3	CCU40.OUT3		VADC0. EMUX01		CCU40.IN3C
P0.4				CCU40.OUT1		VADC0. EMUX00	WWDT. SERVICE_OUT
P0.5				CCU40.OUT0
P0.6				CCU40.OUT0		USIC0_CH1.MCLKOUT	USIC0_CH1. DOUT0	CCU40.IN0B				USIC0_CH1. DX0C
P0.7				CCU40.OUT1		USIC0_CH0. SCLKOUT	USIC0_CH1. DOUT0	CCU40.IN1B				USIC0_CH0. DX1C	USIC0_CH1. DX0D	USIC0_CH1. DX1C
P0.8				CCU40.OUT2		USIC0_CH0. SCLKOUT	USIC0_CH1. SCLKOUT	CCU40.IN2B				USIC0_CH0. DX1B	USIC0_CH1. DX1B
P0.9				CCU40.OUT3		USIC0_CH0. SELO0	USIC0_CH1. SELO0	CCU40.IN3B				USIC0_CH0. DX2B	USIC0_CH1. DX2B
P0.10						USIC0_CH0. SELO1	USIC0_CH1. SELO1					USIC0_CH0. DX2C	USIC0_CH1. DX2C
P0.11				USIC0_CH0.MCLKOUT		USIC0_CH0. SELO2	USIC0_CH1. SELO2					USIC0_CH0. DX2D	USIC0_CH1. DX2D
P0.12						USIC0_CH0. SELO3		CCU40.IN0A	CCU40.IN1A	CCU40.IN2A	CCU40.IN3A	USIC0_CH0. DX2E
P0.13	WWDT. SERVICE_OUT					USIC0_CH0. SELO4						USIC0_CH0. DX2F
P0.14						USIC0_CH0. DOUT0	USIC0_CH0. SCLKOUT					USIC0_CH0. DX0A	USIC0_CH0. DX1A
P0.15						USIC0_CH0. DOUT0	USIC0_CH1.MCLKOUT					USIC0_CH0. DX0B
P1.0		CCU40.OUT0					USIC0_CH0. DOUT0					USIC0_CH0. DX0C
P1.1	VADC0. EMUX00	CCU40.OUT1				USIC0_CH0. DOUT0	USIC0_CH1. SELO0					USIC0_CH0. DX0D	USIC0_CH0. DX1D	USIC0_CH1. DX2E
P1.2	VADC0. EMUX01	CCU40.OUT2					USIC0_CH1. DOUT0					USIC0_CH1. DX0B
P1.3	VADC0. EMUX02	CCU40.OUT3				USIC0_CH1. SCLKOUT	USIC0_CH1. DOUT0					USIC0_CH1. DX0A	USIC0_CH1. DX1A
P1.4	VADC0. EMUX10	USIC0_CH1. SCLKOUT				USIC0_CH0. SELO0	USIC0_CH1. SELO1					USIC0_CH0. DX5E	USIC0_CH1. DX5E
P1.5	VADC0. EMUX11	USIC0_CH0. DOUT0				USIC0_CH0. SELO1	USIC0_CH1. SELO2					USIC0_CH1. DX5F
P1.6	VADC0. EMUX12	USIC0_CH1.DOUT0		USIC0_CH0.SCLKOUT		USIC0_CH0.SELO2	USIC0_CH1.SELO3			USIC0_CH0.DX5F
P2.0	ERU0. PDOUT3	CCU40.OUT0	ERU0. GOUT3			USIC0_CH0. DOUT0	USIC0_CH0. SCLKOUT		VADC0. G0CH5		ERU0.0B0	USIC0_CH0. DX0E	USIC0_CH0. DX1E	USIC0_CH1. DX2F
P2.1	ERU0. PDOUT2	CCU40.OUT1	ERU0. GOUT2			USIC0_CH0. DOUT0	USIC0_CH1. SCLKOUT		VADC0. G0CH6		ERU0.1B0	USIC0_CH0. DX0F	USIC0_CH1. DX3A	USIC0_CH1. DX4A
P2.2									VADC0. G0CH7		ERU0.0B1	USIC0_CH0. DX3A	USIC0_CH0. DX4A	USIC0_CH1. DX5A
P2.3									VADC0. G1CH5		ERU0.1B1	USIC0_CH0. DX5B	USIC0_CH1. DX3C	USIC0_CH1. DX4C
P2.4									VADC0. G1CH6		ERU0.0A1	USIC0_CH0. DX3B	USIC0_CH0. DX4B	USIC0_CH1. DX5B
P2.5									VADC0. G1CH7		ERU0.1A1	USIC0_CH0. DX5D	USIC0_CH1. DX3E	USIC0_CH1. DX4E
P2.6									VADC0. G0CH0		ERU0.2A1	USIC0_CH0. DX3E	USIC0_CH0. DX4E	USIC0_CH1. DX5D
P2.7									VADC0. G1CH1		ERU0.3A1	USIC0_CH0. DX5C	USIC0_CH1. DX3D	USIC0_CH1. DX4D
P2.8									VADC0. G0CH1		ERU0.3B1	USIC0_CH0. DX3D	USIC0_CH0. DX4D	USIC0_CH1. DX5C
P2.9									VADC0. G0CH2		ERU0.3B0	USIC0_CH0. DX5A	USIC0_CH1. DX3B	USIC0_CH1. DX4B
P2.10	ERU0. PDOUT1	CCU40.OUT2	ERU0. GOUT1				USIC0_CH1. DOUT0		VADC0. G0CH3		ERU0.2B0	USIC0_CH0. DX3C	USIC0_CH0. DX4C	USIC0_CH1. DX0F
P2.11	ERU0. PDOUT0	CCU40.OUT3	ERU0. GOUT0			USIC0_CH1. SCLKOUT	USIC0_CH1. DOUT0		VADC0. G0CH4		ERU0.2B1	USIC0_CH1. DX0E	USIC0_CH1. DX1E

Table 10. Hardware Controlled I/O Functions

Function	Outputs		Inputs		Pull Control
	HWO0	HWO1	HWI0	HWI1	HW0_PD	HW0_PU	HW1_PD	HW1_PU
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
P1.0		USIC0_CH0. DOUT0		USIC0_CH0. HWIN0
P1.1		USIC0_CH0. DOUT1		USIC0_CH0. HWIN1
P1.2		USIC0_CH0. DOUT2		USIC0_CH0. HWIN2
P1.3		USIC0_CH0. DOUT3		USIC0_CH0. HWIN3
P1.4
P1.5
P1.6
P2.0
P2.1
P2.2							$\stackrel{<p>¯</p>}{\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="40">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>3</p>}}$	CCU40.OUT3
P2.3
P2.4
P2.5
P2.6							$\stackrel{<p>¯</p>}{\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="40">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>3</p>}}$	CCU40.OUT3
P2.7							$\stackrel{<p>¯</p>}{\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="40">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>3</p>}}$	CCU40.OUT3
P2.8							$\stackrel{<p>¯</p>}{\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="40">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>2</p>}}$	CCU40.OUT2
P2.9							$\stackrel{<p>¯</p>}{\mathrm{<p>C</p>}\mathrm{<p>C</p>}\mathrm{<p>U</p>}\mathrm{<ol\; start="40">\; <li></li>\; </ol>}\mathrm{<p>O</p>}\mathrm{<p>U</p>}\mathrm{<p>T</p>}\mathrm{<p>2</p>}}$	CCU40.OUT2
P2.10
P2.11

Electrical Parameters

This section provides the electrical parameters which are implementation-specific for the XMC1100.

General Parameters

Parameter Interpretation

The parameters listed in this section represent partly the characteristics of the XMC1100 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column:

• CC

  
  

  Such parameters indicate

  C

  ontroller

  C

  haracteristics, which are distinctive feature of the XMC1100 and must be regarded for a system design.

• SR

  
  

  Such parameters indicate

  S

  ystem

  R

  equirements, which must be provided by the application system in which the XMC1100 is designed in.

Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Table 11. Absolute Maximum Rating Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Junction temperature	T J SR	-40	–	115	°C	–
Storage temperature	T ST SR	-40	–	125	°C	–
Voltage on power supply pin with respect to V SSP	V DDP SR	-0.3	–	6	V	–
Voltage on digital pins with respect to V SSP 2	V IN SR	-0.5	–	V DDP + 0.5 or max. 6	V	whichever is lower
Voltage on P2 pins with respect to V SSP 3	V INP2 SR	-0.3	–	V DDP + 0.3	V	–
Voltage on analog input pins with respect to V SSP	V AIN V AREF SR	-0.5	–	V DDP + 0.5 or max. 6	V	whichever is lower
Input current on any pin during overload condition	I IN SR	-10	–	10	mA	–
Absolute maximum sum of all input currents during overload condition	Σ I IN SR	-50	–	+50	mA	–

Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification.

Table 12

defines overload conditions that will not cause any negative reliability impact if all the following conditions are met:

• full operation life-time is not exceeded

• Operating Conditions

  are met for

  • pad supply levels (

    V

    _DDP )

  • temperature

If a pin current is outside of the

Operating Conditions

but within the overload conditions, then the parameters of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters.

Note:

An overload condition on one or more pins does not require a reset.

Note:

A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery.

Table 12. Overload Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Input current on any port pin during overload condition	I OV SR	-5	–	5	mA
Absolute sum of all input circuit currents during overload condition	I OVS SR	–	–	25	mA

Figure 9

shows the path of the input currents during overload via the ESD protection structures. The diodes against

V _DDP

and ground are a simplified representation of these ESD protection structures.

Figure 9. Input Overload Current via ESD structures

Table 13

and

Table 14

list input voltages that can be reached under overload conditions. Note that the absolute maximum input voltages as defined in the

Absolute Maximum Ratings

must not be exceeded during overload.

Table 13. PN-Junction Characteristics for positive Overload

Pad Type	IOV = 5 mA
Standard, High-current, AN/DIG_IN	V IN = V DDP + 0.5 V V AIN = V DDP + 0.5 V V AREF = V DDP + 0.5 V
P2.[1,2,6:9,11]	V INP2 = V DDP + 0.3 V

Table 14. PN-Junction Characteristics for negative Overload

Pad Type	IOV = 5 mA
Standard, High-current, AN/DIG_IN	V IN = V SS - 0.5 V V AIN = V SS - 0.5 V V AREF = V SS - 0.5 V
P2.[1,2,6:9,11]	V INP2 = V SS - 0.3 V

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the XMC1100. All parameters specified in the following tables refer to these operating conditions, unless noted otherwise.

Table 15. Operating Conditions Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Ambient Temperature	T A SR	-40	–	85	°C	Temp. Range F
		-40	–	105	°C	Temp. Range X
Digital supply voltage 4	V DDP SR	1.8	–	5.5	V
MCLK Frequency	f MCLK CC	–	–	33.2	MHz	CPU clock
PCLK Frequency	f PCLK CC	–	–	66.4	MHz	Peripherals clock
Short circuit current of digital outputs	I SC SR	-5	–	5	mA
Absolute sum of short circuit currents of the device	Σ I SC_D SR	–	–	25	mA

DC Parameters

Input/Output Characteristics

Table 16

provides the characteristics of the input/output pins of the XMC1100.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Note:
Unless otherwise stated, input DC and AC characteristics, including peripheral timings, assume that the input pads operate with the standard hysteresis.

Table 16. Input/Output Characteristics (Operating Conditions apply)

Parameter	Symbol		Limit Values		Unit	Note/Test Condition
			Min.	Max.
Output low voltage on port pins (with standard pads)	V OLP CC		–	1.0	V	I OL = 11 mA (5 V) I OL = 7 mA (3.3 V)
			–	0.4	V	I OL = 5 mA (5 V) I OL = 3.5 mA (3.3 V)
Output low voltage on high current pads	V OLP1 CC		–	1.0	V	I OL = 50 mA (5 V) I OL = 25 mA (3.3 V)
			–	0.32	V	I OL = 10 mA (5 V)
			–	0.4	V	I OL = 5 mA (3.3 V)
Output high voltage on port pins (with standard pads)	V OHP CC		V DDP - 1.0	–	V	I OH = -10 mA (5 V) I OH = -7 mA (3.3 V)
			V DDP - 0.4	–	V	I OH = -4.5 mA (5 V) I OH = -2.5 mA (3.3 V)
Output high voltage on high current pads	V OHP1 CC		V DDP - 0.32	–	V	I OH = -6 mA (5 V)
			V DDP - 1.0	–	V	I OH = -8 mA (3.3 V)
			V DDP - 0.4	–	V	I OH = -4 mA (3.3 V)
Input low voltage on port pins (Standard Hysteresis)	V ILPS SR		–	0.19 × V DDP	V	CMOS Mode (5 V, 3.3 V & 2.2 V)
Input high voltage on port pins (Standard Hysteresis)	V IHPS SR		0.7 × V DDP	–	V	CMOS Mode (5 V, 3.3 V & 2.2 V)
Input low voltage on port pins (Large Hysteresis)	V ILPL SR		–	0.08 × V DDP	V	CMOS Mode (5 V, 3.3 V & 2.2 V) 14
Input high voltage on port pins (Large Hysteresis)	V IHPL SR		0.85 × V DDP	–	V	CMOS Mode (5 V, 3.3 V & 2.2 V) 14
Rise time on High Current Pad	t HCPR CC		–	9	ns	50 pF @ 5 V
			–	12	ns	50 pF @ 3.3 V
			–	25	ns	50 pF @ 1.8 V
Fall time on High Current Pad 5	t HCPF CC		–	9	ns	50 pF @ 5 V 6
			–	12	ns	50 pF @ 3.3 V 7
			–	25	ns	50 pF @ 1.8 V 8
Rise time on Standard Pad 5	t R CC		–	12	ns	50 pF @ 5 V
			–	15	ns	50 pF @ 3.3 V
			–	31	ns	50 pF @ 1.8 V
Fall time on Standard Pad 5	t F CC		–	12	ns	50 pF @ 5 V 9
			–	15	ns	50 pF @ 3.3 V 10
			–	31	ns	50 pF @ 1.8 V 11
Input Hysteresis 12	HYS CC		0.08 × V DDP	–	V	CMOS Mode (5 V), Standard Hysteresis
			0.03 × V DDP	–	V	CMOS Mode (3.3 V), Standard Hysteresis
			0.02 × V DDP	–	V	CMOS Mode (2.2 V), Standard Hysteresis
			0.5 × V DDP	0.75 × V DDP	V	CMOS Mode(5 V), Large Hysteresis
			0.4 × V DDP	0.75 × V DDP	V	CMOS Mode(3.3 V), Large Hysteresis
			0.2 × V DDP	0.65 × V DDP	V	CMOS Mode(2.2 V), Large Hysteresis
Pin capacitance (digital inputs/outputs)	C IO CC		–	10	pF
Pull-up resistor on port pins	R PUP CC		20	50	kohm	V IN = V SSP
Pull-down resistor on port pins	R PDP CC		20	50	kohm	V IN = V DDP
Input leakage current 13	I OZP CC		-1	1	µA	0 < V IN < V DDP , T A ≤ 105°C
Voltage on any pin during V DDP power off	V PO SR		–	0.3	V
Maximum current per pin (excluding P1, V DDP and V SS )	I MP SR		-10	11	mA	–
Maximum current per high current pins	I MP1A SR		-10	50	mA	–
Maximum current into V DDP (TSSOP28/16, VQFN24)	I MVDD1 SR		–	130	mA	14
Maximum current into V DDP (TSSOP38, VQFN40)	I MVDD2 SR		–	260	mA	14
Maximum current out of V SS (TSSOP28/16, VQFN24)	I MVSS1 SR		–	130	mA	14
Maximum current out of V SS (TSSOP38, VQFN40)	I MVSS2 SR		–	260	mA	14

Analog to Digital Converters (ADC)

Table 17

shows the Analog to Digital Converter (ADC) characteristics.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 17. ADC Characteristics (Operating Conditions apply)¹⁵

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Supply voltage range (internal reference)	V DD_int SR	2.0	–	3.0	V	SHSCFG.AREF = 11 CALCTR.CALGNSTC = 0C
		3.0	–	5.5	V	SHSCFG.AREF = 10
Supply voltage range (external reference)	V DD_ext SR	3.0	–	5.5	V	SHSCFG.AREF = 00
Analog input voltage range	V AIN SR	VSSP - 0.05	–	VDDP + 0.05	V
Auxiliary analog reference ground	V REFGND SR	V SSP - 0.05	–	1.0	V	G0CH0
Internal reference voltage (full scale value)	V REFINT CC	5			V
Switched capacitance of an analog input	C AINS CC	–	1.2	2	pF	GNCTRxz.GAINy = 00(unity gain)
		–	1.2	2	pF	GNCTRxz.GAINy = 01 (gain g1)
		–	4.5	6	pF	GNCTRxz.GAINy = 10 (gain g2)
		–	4.5	6	pF	GNCTRxz.GAINy = 11 (gain g3)
Total capacitance of an analog input	C AINT CC	–	–	10	pF
Total capacitance of the reference input	C AREFT CC	–	–	10	pF
Gain settings	G IN CC	1			–	GNCTRxz.GAINy = 00 (unity gain)
		3			–	GNCTRxz.GAINy = 01 (gain g1)
		6			–	GNCTRxz.GAINy = 10 (gain g2)
		12			–	GNCTRxz.GAINy = 11 (gain g3)
Sample Time	t sample CC	4	–	–	1/ f ADC	V DD = 5.0 V
		4	–	–	1/ f ADC	V DD = 3.3 V
		30	–	–	1/ f ADC	V DD = 2.0 V
Sigma delta loop hold time	t SD_hold CC	20	–	–	μs	Residual charge stored in an active sigma delta loop remains available
Conversion time in fast compare mode	t CF CC	9			1/ f ADC
Conversion time in 12-bit mode	t C12 CC	20			1/ f ADC	16
Maximum sample rate in 12-bit mode	f C12 CC	–	–	f ADC /43.5	–	1 sample pending
		–	–	f ADC /63.5	–	2 samples pending
Conversion time in 10-bit mode	t C10 CC	18			1/ f ADC	16
Maximum sample rate in 10-bit mode 17	f C10 CC	–	–	f ADC /41.5	–	1 sample pending
		–	–	f ADC /59.5	–	2 samples pending
Conversion time in 8-bit mode	t C8 CC	16			1/ f ADC	16
Maximum sample rate in 8-bit mode 17	f C8 CC	–	–	f ADC /38.5	–	1 sample pending
		–	–	f ADC /54.5	–	2 samples pending
RMS noise 18	EN RMS CC	–	1.5	–	LSB12	DC input, V DD = 5.0 V, V AIN = 2.5 V, 25°C
DNL error	EA DNL CC	–	±2.0	–	LSB12
INL error	EA INL CC	–	±4.0	–	LSB12
Gain error with external reference	EA GAIN CC	–	±0.5	–	%	SHSCFG.AREF = 00 (calibrated)
Gain error with internal reference 19	EA GAIN CC	–	±3.6	–	%	SHSCFG.AREF = 1X (calibrated), -40°C - 105°C
		–	±2.0	–	%	SHSCFG.AREF = 1X (calibrated), 0°C - 85°C
Offset error	EA OFF CC	–	±8.0	–	mV	Calibrated, V DD = 5.0 V

Figure 10. ADC Voltage Supply

Temperature Sensor Characteristics

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 18. Temperature Sensor Characteristics

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Measurement time	t M CC	–	–	10	ms
Temperature sensor range	T SR SR	-40	–	115	°C
Sensor Accuracy 20	T TSAL CC	-6	–	6	°C	T J > 20°C
		-10	–	10	°C	0°C ≤ T J ≤ 20°C
		-18	–	18	°C	-25°C ≤ T J < 0°C
		-31	–	31	°C	-40°C ≤ T J < -25°C
Start-up time after enabling	t TSSTE SR	–	–	15	μs

Power Supply Current

The total power supply current defined below consists of a leakage and a switching component.

Application relevant values are typically lower than those given in the following tables, and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations).

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 19.Power Supply Parameters;V_DDP= 5 V

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ. 21	Max.
Active mode current Peripherals enabled f MCLK / f PCLK in MHz 22	I DDPAE CC	–	8.4	11.0	mA	32/64
		–	7.3	–	mA	24/48
		–	6.1	–	mA	16/32
		–	5.1	–	mA	8/16
		–	3.7	–	mA	1/1
Active mode current Peripherals disabled f MCLK / f PCLK in MHz 23	I DDPAD CC	–	4.7	–	mA	32/64
		–	4.1	–	mA	24/48
		–	3.3	–	mA	16/32
		–	2.6	–	mA	8/16
		–	1.5	–	mA	1/1
Active mode current Code execution from RAM Flash is powered down f MCLK / f PCLK in MHz	I DDPAR CC	–	6.3	–	mA	32/64
		–	5.4	–	mA	24/48
		–	4.6	–	mA	16/32
		–	3.8	–	mA	8/16
		–	3.0	–	mA	1/1
Sleep mode current Peripherals clock enabled f MCLK / f PCLK in MHz 24	I DDPSE CC	–	5.9	–	mA	32/64
			5.4	–	mA	24/48
			4.8	–	mA	16/32
			4.3	–	mA	8/16
			3.7	–	mA	1/1
Sleep mode current Peripherals clock disabled Flash active f MCLK / f PCLK in MHz 25	I DDPSD CC	–	1.8	–	mA	32/64
			1.7	–	mA	24/48
			1.6	–	mA	16/32
			1.5	–	mA	8/16
			1.4	–	mA	1/1
Sleep mode current Peripherals clock disabled Flash powered down f MCLK / f PCLK in MHz 26	I DDPSR CC	–	1.2	–	mA	32/64
			1.1	–	mA	24/48
			1.0	–	mA	16/32
			0.8	–	mA	8/16
			0.7	–	mA	1/1
Deep Sleep mode current 27	I DDPDS CC	–	0.24	–	mA
Wake-up time from Sleep to Active mode 28	t SSA CC	–	6	–	cycles
Wake-up time from Deep Sleep to Active mode 29	t DSA CC	–	280	–	μsec

Figure 11

shows typical graphs for active mode supply current for

V

DDP

= 5 V,

V

DDP

= 3.3 V,

V

DDP

= 1.8 V across different clock frequencies.

Figure 11. Active mode, a) peripherals clocks enabled, b) peripherals clocks disabled: Supply current I_DDPA over supply voltage V_DDP for different clock frequencies

Figure 12

shows typical graphs for sleep mode current for

V

DDP

= 5 V,

V

DDP

= 3.3 V,

V

DDP

= 1.8 V across different clock frequencies.

Figure 12. Sleep mode, peripherals clocks disabled, Flash powered down: Supply current I_DDPSR over supply voltage V_DDP for different clock frequencies

Table 20

provides the active current consumption of some modules operating at 5 V power supply at 25°C. The typical values shown are used as a reference guide on the current consumption when these modules are enabled.

Table 20. Typical Active Current Consumption

Active Current Consumption	Symbol	Limit Values	Unit	Note/Test Condition
		Typ.
Baseload current	I CPUDDC	5.04	mA	Modules including Core, SCU, PORT, memories, ANATOP 30
VADC and SHS	I ADCDDC	3.4	mA	Set CGATCLR0.VADC to 1 31
USIC0	I USIC0DDC	0.87	mA	Set CGATCLR0.USIC0 to 1 32
CCU40	I CCU40DDC	0.94	mA	Set CGATCLR0.CCU40 to 1 33
WDT	I WDTDDC	0.03	mA	Set CGATCLR0.WDT to 1 34
RTC	I RTCDDC	0.01	mA	Set CGATCLR0.RTC to 1 35

Flash Memory Parameters

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 21. Flash Memory Parameters

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Erase Time per page/sector	t ERASE CC	6.8	7.1	7.6	ms
Program time per block	t PSER CC	102	152	204	μs
Wake-Up time	t WU CC	–	32.2	–	μs
Read time per word	t a CC	–	50	–	ns
Data Retention Time	t RET CC	10	–	–	years	Max. 100 erase/program cycles
Flash Wait States 36	N WSFLASH CC	0	0	0		fMCLK = 8 MHz
		0	1	1		fMCLK = 16 MHz
		1	1.3	2		fMCLK = 32 MHz
Fixed Flash Wait States configured in bit NVM_NVMCONF.WS	N FWSFLASH SR	0	0	1		NVM_CONFIG1.FIXWS = 1 , fMCLK ≤ 16 MHz
		1	1	1		NVM_CONFIG1.FIXWS = 1 , 16 MHz < fMCLK ≤ 32 MHz
Erase Cycles	N ECYC CC	–	–	5*10 4	cycles	Sum of page and sector erase cycles
Total Erase Cycles	N TECYC CC	–	–	2*10 6	cycles

AC Parameters

Testing Waveforms

Figure 13. Rise/Fall Time Parameters

Figure 14. Testing Waveform, Output Delay

Figure 15. Testing Waveform, Output High Impedance

Power-Up and Supply Monitoring Characteristics

Table 22

provides the characteristics of the supply monitoring in XMC1100.

The guard band between the lowest valid operating voltage and the brownout reset threshold provides a margin for noise immunity and hysteresis. The electrical parameters may be violated while

V

DDP

is outside its operating range.

The brownout detection triggers a reset within the defined range. The prewarning detection can be used to trigger an early warning and issue corrective and/or fail-safe actions in case of a critical supply voltage drop.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 22. Power-Up and Supply Monitoring Parameters (Operating Conditions apply)³⁷

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
V DDP ramp-up time	t RAMPUP SR	V DDP /S VDDPrise	–	10 7	μs
V DDP slew rate	S VDDPOP SR	0	–	0.1	V/μs	Slope during normal operation
	S VDDP10 SR	0	–	10	V/μs	Slope during fast transient within +/-10% of V DDP
	S VDDPrise SR	0	–	10	V/μs	Slope during power-on or restart after brownout event
	S VDDPfall 38 SR	0	–	0.25	V/μs	Slope during supply falling out of the +/-10% limits 39
V DDP prewarning voltage	V DDPPW CC	2.1	2.25	2.4	V	ANAVDEL.VDEL_SELECT = 00
		2.85	3	3.15	V	ANAVDEL.VDEL_SELECT = 01
		4.2	4.4	4.6	V	ANAVDEL.VDEL_SELECT = 10
V DDP brownout reset voltage	V DDPBO CC	1.55	1.62	1.75	V	calibrated, before user code starts running
V DDP voltage to ensure defined pad states	V DDPPA CC	–	1.0	–	V
Start-up time from power-on reset	t SSW SR	–	320	–	μs	Time to the first user code instruction in all start-up modes 40
BMI program time	t BMI SR	–	8.25	–	ms	Time taken from a user-triggered system reset after BMI installation is requested

Figure 16. Supply Threshold Parameters

On-Chip Oscillator Characteristics

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 23

provides the characteristics of the 64 MHz clock output from the digital controlled oscillator, DCO1 in XMC1100.

Table 23. 64 MHz DCO1 Characteristics (Operating Conditions apply)

Parameter	Symbol	Limit Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Nominal frequency	f NOM CC	–	64	–	MHz	under nominal conditions 41 after trimming
Accuracy 42	Δ f LT CC	-1.7	–	3.4	%	with respect to f NOM (typ), over temperature (0°C to 85°C)
		-3.9	–	4.0	%	with respect to f NOM (typ), over temperature (-40°C to 105°C)

Figure 17

shows the typical curves for the accuracy of DCO1, with and without calibration based on temperature sensor, respectively.

Figure 17. Typical DCO1 accuracy over temperature

Table 24

provides the characteristics of the 32 kHz clock output from digital controlled oscillators, DCO2 in XMC1100.

Table 24. 32 kHz DCO2 Characteristics (Operating Conditions apply)

Parameter	Symbol	Limit Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Nominal frequency	f NOM CC	–	32.75	–	kHz	under nominal conditions 43 after trimming
Accuracy	Δ f LT CC	-1.7	–	3.4	%	with respect to f NOM (typ), over temperature (0°C to 85°C)
		-3.9	–	4.0	%	with respect to f NOM (typ), over temperature (-40°C to 105°C)

Serial Wire Debug Port (SW-DP) Timing

The following parameters are applicable for communication through the SW-DP interface.

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Table 25. SWD Interface Timing Parameters (Operating Conditions apply)

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
SWDCLK high time	t 1 SR	50	–	500000	ns	–
SWDCLK low time	t 2 SR	50	–	500000	ns	–
SWDIO input setup to SWDCLK rising edge	t 3 SR	10	–	–	ns	–
SWDIO input hold after SWDCLK rising edge	t 4 SR	10	–	–	ns	–
SWDIO output valid time after SWDCLK rising edge	t 5 CC	–	–	68	ns	C L = 50 pF
		–	–	62	ns	C L = 30 pF
SWDIO output hold time from SWDCLK rising edge	t 6 CC	4	–	–	ns

Figure 18. SWD Timing

SPD Timing Requirements

The optimum SPD decision time between

0

and

1

is 0.75 µs. With this value the system has maximum robustness against frequency deviations of the sampling clock on tool and on device side. However it is not always possible to exactly match this value with the given constraints for the sample clock. For instance for a oversampling rate of 4, the sample clock will be 8 MHz and in this case the closest possible effective decision time is 5.5 clock cycles (0.69 µs).

Table 26. Optimum Number of Sample Clocks for SPD

Sample Freq.	Sampling Factor	Sample Clocks 0	Sample Clocks 1	Effective Decision Time 44	Remark
8 MHz	4	1 to 5	6 to 12	0.69 µs	The other closest option (0.81 µs) for the effective decision time is less robust.

For a balanced distribution of the timing robustness of SPD between tool and device, the timing requirements for the tool are:

• Frequency deviation of the sample clock is +/- 5%

• Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal sample frequency)

Peripheral Timings

Note:
These parameters are not subject to production test, but verified by design and/or characterization.

Synchronous Serial Interface (USIC SSC) Timing

The following parameters are applicable for a USIC channel operated in SSC mode.

Note:
Operating Conditions apply.

Table 27. USIC SSC Master Mode Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
SCLKOUT master clock period	t CLK CC	62.5	–	–	ns
Slave select output SELO active to first SCLKOUT transmit edge	t 1 CC	80	–	–	ns
Slave select output SELO inactive after last SCLKOUT receive edge	t 2 CC	0	–	–	ns
Data output DOUT[3:0] valid time	t 3 CC	-10	–	10	ns
Receive data input DX0/DX[5:3] setup time to SCLKOUT receive edge	t 4 SR	80	–	–	ns
Data input DX0/DX[5:3] hold time from SCLKOUT receive edge	t 5 SR	0	–	–	ns

Table 28. USIC SSC Slave Mode Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
DX1 slave clock period	t CLK SR	125	–	–	ns
Select input DX2 setup to first clock input DX1 transmit edge	t 10 SR	10	–	–	ns
Select input DX2 hold after last clock input DX1 receive edge 45	t 11 SR	10	–	–	ns
Receive data input DX0/DX[5:3] setup time to shift clock receive edge 45	t 12 SR	10	–	–	ns
Data input DX0/DX[5:3] hold time from clock input DX1 receive edge 45	t 13 SR	10	–	–	ns
Data output DOUT[3:0] valid time	t 14 CC	–	–	80	ns

Figure 19. USIC - SSC Master/Slave Mode Timing

Note:
This timing diagram shows a standard configuration, for which the slave select signal is low-active, and the serial clock signal is not shifted and not inverted.

Inter-IC (IIC) Interface Timing

The following parameters are applicable for a USIC channel operated in IIC mode.

Note:
Operating Conditions apply.

Table 29. USIC IIC Standard Mode Timing ⁴⁶

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Fall time of both SDA and SCL	t 1 CC/SR	–	–	300	ns
Rise time of both SDA and SCL	t 2 CC/SR	–	–	1000	ns
Data hold time	t 3 CC/SR	0	–	–	µs
Data set-up time	t 4 CC/SR	250	–	–	ns
LOW period of SCL clock	t 5 CC/SR	4.7	–	–	µs
HIGH period of SCL clock	t 6 CC/SR	4.0	–	–	µs
Hold time for (repeated) START condition	t 7 CC/SR	4.0	–	–	µs
Set-up time for repeated START condition	t 8 CC/SR	4.7	–	–	µs
Set-up time for STOP condition	t 9 CC/SR	4.0	–	–	µs
Bus free time between a STOP and START condition	t 10 CC/SR	4.7	–	–	µs
Capacitive load for each bus line	C b SR	–	–	400	pF

Table 30. USIC IIC Fast Mode Timings ⁴⁷

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Fall time of both SDA and SCL	t 1 CC/SR	20 + 0.1* C b 48	–	300	ns
Rise time of both SDA and SCL	t 2 CC/SR	20 + 0.1* C b	–	300	ns
Data hold time	t 3 CC/SR	0	–	–	µs
Data set-up time	t 4 CC/SR	100	–	–	ns
LOW period of SCL clock	t 5 CC/SR	1.3	–	–	µs
HIGH period of SCL clock	t 6 CC/SR	0.6	–	–	µs
Hold time for (repeated) START condition	t 7 CC/SR	0.6	–	–	µs
Set-up time for repeated START condition	t 8 CC/SR	0.6	–	–	µs
Set-up time for STOP condition	t 9 CC/SR	0.6	–	–	µs
Bus free time between a STOP and START condition	t 10 CC/SR	1.3	–	–	µs
Capacitive load for each bus line	C b SR	–	–	400	pF

Figure 20. USIC IIC Stand and Fast Mode Timing

Inter-IC Sound (IIS) Interface Timing

The following parameters are applicable for a USIC channel operated in IIS mode.

Note:
Operating Conditions apply.

Table 31. USIC IIS Master Transmitter Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Clock period	t 1 CC	2/ f MCLK	–	–	ns	V DDP ≥ 3 V
		4/ f MCLK	–	–	ns	V DDP < 3 V
Clock HIGH	t 2 CC	0.35 × t 1min	–	–	ns
Clock Low	t 3 CC	0.35 × t 1min	–	–	ns
Hold time	t 4 CC	0	–	–	ns
Clock rise time	t 5 CC	–	–	0.15 × t 1min	ns

Figure 21. USIC IIS Master Transmitter Timing

Table 32. USIC IIS Slave Receiver Timing

Parameter	Symbol	Values			Unit	Note/Test Condition
		Min.	Typ.	Max.
Clock period	t 6 SR	4/ f MCLK	–	–	ns
Clock HIGH	t 7 SR	0.35 × t 6min	–	–	ns
Clock Low	t 8 SR	0.35 × t 6min	–	–	ns
Set-up time	t 9 SR	0.2 × t 6min	–	–	ns
Hold time	t 10 SR	10	–	–	ns

Figure 22. USIC IIS Slave Receiver Timing

Package and Reliability

The XMC1100 is a member of the XMC1000 Family of microcontrollers. It is also compatible to a certain extent with members of similar families or subfamilies.

Each package is optimized for the device it houses. Therefore, there may be slight differences between packages of the same pin-count but for different device types. In particular, the size of the exposed die pad may vary.

If different device types are considered or planned for an application, it must be ensured that the board layout fits all packages under consideration.

Package Parameters

Table 33

provides the thermal characteristics of the packages used in XMC1100.

Table 33. Thermal Characteristics of the Packages

Parameter	Symbol	Limit Values		Unit	Package Types
		Min.	Max.
Exposed Die Pad Dimensions	Ex × Ey CC	–	2.7 × 2.7	mm	PG-VQFN-24-19
		–	3.7 × 3.7	mm	PG-VQFN-40-13
Thermal resistance Junction-Ambient	R ΘJA CC	–	104.6	K/W	PG-TSSOP-16-8
		–	70.3	K/W	PG-TSSOP-38-9 49
		–	46.0	K/W	PG-VQFN-24-19 49
		–	38.4	K/W	PG-VQFN-40-13 49

Note:
For electrical reasons, it is required to connect the exposed pad to the board ground V_SSP, independent of EMC and thermal requirements.

Thermal Considerations

When operating the XMC1100 in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage.

The maximum heat that can be dissipated depends on the package and its integration into the target board. The “Thermal resistance

R

ΘJA

” quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 115°C.

The difference between junction temperature and ambient temperature is determined by

Δ

T

= (

P

INT

+

P

IOSTAT

+

P

IODYN

) ×

R

ΘJA

The internal power consumption is defined as

P

INT

=

V

DDP

×

I

DDP

(switching current and leakage current).

The static external power consumption caused by the output drivers is defined as

P

IOSTAT

= Σ((

V

DDP

-

V

OH

) ×

I

OH

) + Σ(

V

OL

×

I

OL

)

The dynamic external power consumption caused by the output drivers (

P

IODYN

) depends on the capacitive load connected to the respective pins and their switching frequencies.

If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation:

• Reduce

  V

  DDP

  , if possible in the system

• Reduce the system frequency

• Reduce the number of output pins

• Reduce the load on active output drivers

Package Outlines

Figure 23. PG-TSSOP-38-9

Figure 24. PG-TSSOP-16-8

Figure 25. PG-VQFN-24-19

Figure 26. PG-VQFN-40-13

All dimensions in mm.

Quality Declaration

Table 34

shows the characteristics of the quality parameters in the XMC1100.

Table 34. Quality Parameters

Parameter	Symbol	Limit Values		Unit	Notes
		Min.	Max.
ESD susceptibility according to Human Body Model (HBM)	V HBM SR	–	4000	V	Conforming to EIA/JESD22-A114-B
ESD susceptibility according to Charged Device Model (CDM) pins	V CDM SR	–	1000	V	Conforming to JESD22-C101-C
Moisture sensitivity level	MSL CC	–	–	–	JEDEC J-STD-020D
TSSOP-16, TSSOP-38			3
VQFN-24, VQFN-40			1
Soldering temperature	T SDR SR	–	260	°C	Profile according to JEDEC J-STD-020D

Revision History

Document revision	Date	Description of changes
V1.8	2016-09	In Absolute Maximum Ratings renamed parameter V CM to V INP2 , as the limitation is related to most P2 pins, also if no ACMP is available. Clarified limit to pins P2.[1,2,6:9,11] in Overload specification.
V1.9	2025-01-22	Updated template. Updated Moisture sensitivity level in Quality Declaration section.
V2.0	2025-04-22	Updated On-Chip Memories in Summary of Features section. Added XMC1100-T038X0128 and XMC1100-T038X0200 in Table 1 and Table 4 . Updated the block diagram to show 64k to 200K.
V2.1	2025-06-30	Updated ESD ratings in Table 34

1

Features that are not included in this table are available in all the derivatives.

2

Excluding port pins P2.[1,2,6,7,8,9,11].

3

Applicable to port pins P2.[1,2,6,7,8,9,11].

4

See also the Supply Monitoring thresholds,

Chapter 3.3.2

.

5

Rise/Fall time parameters are taken with 10% - 90% of supply.

6

Additional rise/fall time valid for

C

L

= 50 pF -

C

L

= 100 pF @ 0.150 ns/pF at 5 V supply voltage.

7

Additional rise/fall time valid for

C

L

= 50 pF -

C

L

= 100 pF @ 0.205 ns/pF at 3.3 V supply voltage.

8

Additional rise/fall time valid for

C

L

= 50 pF -

C

L

= 100 pF @ 0.445 ns/pF at 1.8 V supply voltage.

9

Additional rise/fall time valid for

C

L

= 50 pF -

C

L

= 100 pF @ 0.225 ns/pF at 5 V supply voltage.

10

Additional rise/fall time valid for

C

L

= 50 pF -

C

L

= 100 pF @ 0.288 ns/pF at 3.3 V supply voltage.

11

Additional rise/fall time valid for

C

L

= 50 pF -

C

L

= 100 pF @ 0.588 ns/pF at 1.8 V supply voltage.

12

Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise.

13

An additional error current (

I

INJ

) will flow if an overload current flows through an adjacent pin.

14

However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when

V

DDP

is powered off.

15

The parameters are defined for ADC clock frequency

f

SH

= 32 MHz.

16

No pending samples assumed, excluding sampling time and calibration.

17

Includes synchronization and calibration (average of gain and offset calibration).

18

This parameter can also be defined as an SNR value: SNR[dB] = 20 × log(

A

MAXeff

/

N

RMS

).

With

A

MAXeff

= 2N/2, SNR[dB] = 20 × log (2048/

N

RMS

) [N = 12].

N

RMS

= 1.5 LSB12, therefore, equals SNR = 20 × log (2048/1.5) = 62.7 dB.

19

Includes error from the reference voltage.

20

The temperature sensor accuracy is independent of the supply voltage.

21

The typical values are measured at

T

A

= + 25°C and

V

DDP

= 5 V.

22

CPU and all peripherals clock enabled, Flash is in active mode.

23

CPU enabled, all peripherals clock disabled, Flash is in active mode.

24

CPU in sleep, all peripherals clock enabled and Flash is in active mode.

25

CPU in sleep, Flash is in active mode.

26

CPU in sleep, Flash is powered down and code executed from RAM after wake-up.

27

CPU in sleep, peripherals clock disabled, Flash is powered down and code executed from RAM after wake-up.

28

CPU in sleep, Flash is in active mode during sleep mode.

29

CPU in sleep, Flash is in powered down mode during deep sleep mode.

30

Baseload current is measured with device running in user mode, MCLK=PCLK=32 MHz, with an endless loop in the flash memory. The clock to the modules stated in CGATSTAT0 are gated.

31

Active current is measured with: module enabled, MCLK=32 MHz, running in auto-scan conversion mode.

32

Active current is measured with: module enabled, alternating messages sent to PC at 57.6 kbaud every 200 ms.

33

Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU4 slice for PWM switching from 1500 Hz and 1000 Hz at regular intervals, 1 CCU4 slice in capture mode for reading period and duty cycle.

34

Active current is measured with: module enabled, MCLK=32 MHz, time-out mode; WLB = 0, WUB = 0x00008000; WDT serviced every 1 s.

35

Active current is measured with: module enabled, MCLK=32 MHz, Periodic interrupt enabled.

36

Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical values are calculated from the execution of the Dhrystone benchmark program.

37

Not all parameters are 100% tested, but are verified by design/characterization.

38

A capacitor of at least 100 nF has to be added between

V

DDP

and

V

SSP

to fulfill the requirement as stated for this parameter.

39

Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forwarded only to the chip. A larger capacitor value has to be chosen if the power source sink a current.

40

This values does not include the ramp-up time. During start-up firmware execution, MCLK is running at 32 MHz and the clocks to peripheral as specified in register CGATSTAT0 are gated.

41

The deviation is relative to the factory trimmed frequency at nominal

V

DDC

and

T

A

= + 25°C.

42

The accuracy of the DCO1 oscillator can be further improved through alternative methods, refer to XMC1000 Oscillator Handling Application Note.

43

The deviation is relative to the factory trimmed frequency at nominal

V

DDC

and

T

A

= + 25°C.

44

Nominal sample frequency period multiplied with 0.5 + (max. number of

0

sample clocks).

45

These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0).

46

Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximately 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

47

Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximately 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

48

C

b

refers to the total capacitance of one bus line in pF.

49

Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered.