1. Connect the PSOC™ 6 kit to the host PC.

  2. As needed, run the fw-loader tool to make sure the board firmware is upgraded to KitProg3. See

    KitProg3 User Guide

    for details. The tool is located in this directory by default:

    <user_home>/ModusToolbox/tools_3.1/fw-loader/bin/

  3. Select

    Debug > Start/Stop Debug Session

    .


    ../figures/image27.png

You can view the system and peripheral registers in the SVD view.


../figures/image28.png

To use KitProg3/MiniProg4, CMSIS-DAP, and ULink2 debuggers

  1. Select the

    Device

    tab in the Options for Target dialog and check that M4 core is selected:


    ../figures/image29.png

  2. Select the

    Debug

    tab.

    Note:

    To use the ULink2 probe for multi-core debugging, select the CMSIS-DAP Debugger instead of ULink for each core of the project (CM4 and CM0P).

  3. Click the

    Settings

    button.


    ../figures/image30.png

  4. On the Target Driver Setup dialog on the

    Debug

    tab, select the following:

    • set

      Port

      to "SW"

    • set

      Max Clock

      to "1 MHz"

    • set

      Connect

      to "Normal"

    • set

      Reset

      :

      • For PSOC™ 6, to "VECTRESET"

      • For PSOC™ 4, PMG1, and AIROC™ CYW208xx, to "SYSRESETREQ"

    • enable

      Reset after Connect

      option


    ../figures/image31.png

  5. For PSOC™ 4, PMG1, and AIROC™ CYW208xx, to "SYSRESETREQ"

  6. Select the

    Flash Download

    tab and select "Reset and Run" option after download, if needed:



  7. Select the

    Pack

    tab and check if "Cypress.PSoC6_DFP" is enabled:


    ../figures/image33.png

  1. Make sure you have J-Link software version 6.62 or newer.

  2. Select the

    Debug

    tab in the Options for Target dialog, select J-LINK / J-TRACE Cortex as debug adapter, and click "Settings":


    ../figures/image34.png

  3. If you see the following message, click

    OK

    in the Device selection message box:


    ../figures/image35.png

  4. Select the appropriate target in Wizard:


    ../figures/image36.png

  5. Go to

    Debug

    tab in Target Driver Setup dialog and select:

    • set Port to "SW"

    • set Max Clock to "1 MHz"

    • set Connect to "Normal"

    • set Reset to "Normal"

    • enable Reset after Connect option


    ../figures/image37.png

  6. Select the

    Flash Download

    tab in Target Driver Setup dialog and select "Reset and Run" option after download if needed:


    ../figures/image38.png

Program set-up instructions

  1. Select the

    Debug

    tab in the Options for Target dialog, select "J-LINK / J-TRACE Cortex" as the debug adapter, and click

    Settings

    .


    ../figures/image39.png

  2. On the

    Debug

    tab in the Cortex J-Link/JTrace Target Driver Setup dialog, select "SW" for

    Port

    , 2 MHz for

    Max Clock

    , and "Connect under Reset" on the

    Reset

    pull-down menu, and then click

    OK

    .


    ../figures/image40.png

  3. Select the

    Utilities

    tab in the Options for Target dialog and deselect the

    Update target before Debugging

    check box.


    ../figures/image41.png

Debug set-up instructions

  1. Select the

    Debug

    tab in the Options for Target dialog, select "J-LINK / J-TRACE Cortex" as the debug adapter, and click

    Settings

    .


    ../figures/image42.png

  2. On the

    Debug

    tab in the Target Driver Setup dialog:

    • Port

      : select "SW"

    • Max Clock

      : select 2 MHz

    • Reset

      pull-down: select "Normal," "Core" or "Reset Pin"

    • Download Options

      : enable "Verify Code Download" and "Download to Flash"


    ../figures/image43.png

Program external memory

  1. Download internal flash as described above.

    Notice "No Algorithm found for: 18000000H - 1800FFFFH" warning.

  2. Select the Flash Download tab in Target Driver Setup dialog and remove all programming algorithms for On-chip Flash and add programming algorithm for External Flash SPI:


    ../figures/image44.png


    ../figures/image45.png

  3. Download flash.

Notice warnings:

  • No Algorithm found for: 10000000H - 1000182FH

  • No Algorithm found for: 10002000H - 10007E5BH

  • No Algorithm found for: 16007C00H - 16007DFFH

Erase external memory

  1. Select the

    Flash Download

    tab in Target Driver Setup dialog and remove all programming algorithms for On-chip Flash and add programming algorithm for External Flash SPI:


    ../figures/image44.png


    ../figures/image45.png

  2. Click

    Flash > Erase

    in menu bar.

PSOC™ Control C3 devices

For Infineon PSOC™ Control C3 devices, the same physical flash memory can be erased/programmed over SBUS either over non-secure addresses (0x22000000-0x2203FFFF) or over secure addresses (0x32000000-0x3203FFFF).

During flash programming operations, the CPU core operates in the Secure world. In this state, the non-secure addresses are always accessible, but secure addresses may be unavailable if certain regions are configured for non-secure access (for PSOC™ Control C3, this means non-secure access only).

To erase the entire flash memory, it's important to only erase the non-secure range of addresses. Remove the flashloader with the secure address range from the list prior to performing the erase.



However, if the application has data that must be programmed through a secure address range, the previously deleted flashloader needs to be re-added by using the

Add

button and specifying the secure address range.