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TLD2362-3ET

Datasheet

LITIX™ Basic+

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Features

  • Single channel device with integrated and protected output stage (current sink), optimized to drive LEDs
  • High output current up to 400 mA
  • Possibility to offload power consumption via low cost external resistor to allow maximum current driving capability (Power Shift)
  • Fault management supports both 1-fail-all-OFF and 1-fail-all-ON
  • Analog output current control input to adjust the output current
  • Three-channel device with integrated and protected output stages (current sinks), optimized to drive LEDs
  • High output current up to 150 mA per channel
  • Independent output current control via enable pins
  • Fault management supports both 1-fail-all-OFF and 1-fail-all-ON
  • Analog output current control input to adjust the output current
  • Three-channel device with integrated and protected output stages (current sinks), optimized to drive LEDs
  • High output current up to 150 mA per channel
  • Possibility to offload power consumption via low cost external resistors to allow maximum current driving capability (Power Shift)
  • Output current control via enable pin
  • Fault management supports both 1-fail-all-OFF and 1-fail-all-ON
  • Analog output current control input to adjust the output current
  • Three-channel device with integrated and protected output stages (current sinks), optimized to drive LEDs
  • High output current up to 150 mA per channel
  • Possibility to offload power consumption via low cost external resistors to allow maximum current driving capability (Power Shift)
  • Independent output current control via enable pins
  • Fault management supports 1-fail-all-OFF
  • Analog output current control input to adjust the output current
  • Three-channel device with integrated and protected output stages (current sinks), optimized to drive LEDs
  • High output current up to 150 mA per channel
  • Possibility to offload power consumption via low cost external resistors to allow maximum current driving capability (Power Shift)
  • Independent output current control via enable pins
  • Fault management supports 1-fail-all-ON
  • Analog output current control input to adjust the output current
  • Open load (OL), short to battery (SC) and thermal shutdown protections
  • Intelligent fault management: up to 10 devices can share a common error network with only one external resistor
  • Thermal derating function via external NTC resistor

Potential applications

  • Cost effective "stop"/"tail" function with shared and separated LEDs per function
  • Automotive light functions like turn indicators, position, fog, stop/tail, DRL and side markers
  • Animated light functions like sequential indicator and "welcome/goodbye" functions
  • Interior lighting functions like ambient lighting, illumination and dash board lighting
  • LED indicators for industrial applications and instrumentation

Product validation

Product validation according to AEC-Q100, Grade 1.

Qualified for automotive applications.

Description

The TLD1173-1ET is a single channel low-side driver IC with integrated and protected output stage. It is designed to control LEDs with a current up to 400 mA as linear current sink (LCS). The power shift feature allows the device to reach maximum current driving capability by offloading power consumption to an external low cost resistor. Along with its integrated diagnostic features, it offers a simple and reliable solution compared to discrete solutions. The diagnostic features and thermal derating via external NTC resistor provide a reliable solution for high current applications. The configurable fault management allows up to 10 and more devices to share the same error network and to be combined in applications with other LITIX™ LED drivers, such other LITIX™ Basic+ products and LITIX™ TLD7002-16ES.

The TLD2382-3ET is a three channel low-side driver IC with integrated and protected output stages. It is designed to control LEDs with a current up to 150 mA as linear current sink (LCS). The Power Shift feature allows the device to reach maximum current driving capability by offloading power consumption to external low cost components. The diagnostic features and thermal derating via external NTC resistor provide a reliable solution for high current applications. The fault management, implementing 1 fail-all-OFF reaction, allows up to 10 and more devices to share the same error network and to be combined in applications with other LITIX™ LED drivers, such as other LITIX™ Basic+ products and LITIX™ TLD7002-16ES.

The TLD2392-3ET is a three channel low-side driver IC with integrated and protected output stages. It is designed to control LEDs with a current up to 150 mA as linear current sink (LCS). The Power Shift feature allows the device to reach maximum current driving capability by offloading power consumption to external low cost components. The diagnostic features and thermal derating via external NTC resistor provide a reliable solution for high current applications. The fault management, implementing 1 fail-all-ON reaction, allows up to 10 and more devices to share the same error network and to be combined in applications with other LITIX™ LED drivers, such as other LITIX™ Basic+ products and LITIX™ TLD7002-16ES.

The TLD2372-3ET is a three channel low-side driver IC with integrated and protected output stages. It is designed to control LEDs with a current up to 150 mA as linear current sink (LCS). The Power Shift feature allows the device to reach maximum current driving capability by offloading power consumption to external low cost components. The diagnostic features and thermal derating via external NTC resistor provide a reliable solution for high current applications. The configurable fault management allows up to 10 and more devices to share the same error network and to be combined in applications with other LITIX™ LED drivers, such as other LITIX™ Basic+ products and LITIX™ TLD7002-16ES.

The TLD2362-3ET is a three channel low-side driver IC with integrated and protected output stages. It is designed to control LEDs with a current up to 150 mA as linear current sink (LCS). The diagnostic features and thermal derating via external NTC resistors provide a reliable solution. The configurable fault management allows up to 10 and more devices to share the same error network and to be combined in applications with other LITIX™ LED drivers, such as other LITIX™ Basic+ products and LITIX™ TLD7002-16ES.











Product typePackageMarking
TLD1173-1ETTFDSO-16117
Product typePackageMarking
TLD2392-3ETTFDSO-16239
Product typePackageMarking
TLD2382-3ETTFDSO-16238
Product typePackageMarking
TLD2362-3ETTFDSO-16236
Product typePackageMarking
TLD2372-3ETTFDSO-16237

Product description

Table 1. Product summary
ParameterSymbolValues
Operating voltageVS(func)5.5 V - 18 V
Extended operating voltageVS(ext)4.5 V - 36 V
Maximum load currentISENSE(max)150 mA
Output current accuracyVSENSE(reg)±4% with VSENSE = 400 mV
Current consumption in sleep modeIVS(sleep, max)3 μA
Maximum current consumption during faultIVS(fault, ERRN)850 μA
Maximum dropout voltageVDR,CS(max)0.54 V
Table 2. Product summary
ParameterSymbolValues
Operating voltageVS(func)5.5 V - 18 V
Extended operating voltageVS(ext)4.5 V - 36 V
Maximum load currentISENSE(max)150 mA
Output current accuracyVSENSE(reg)±4% with VSENSE = 400 mV
Current consumption in sleep modeIVS(sleep, max)3 μA
Maximum current consumption during faultIVS(fault, ERRN)850 μA
Maximum dropout voltageVDR,CS(max)0.6 V
Table 3. Product summary
ParameterSymbolValues
Operating voltageVS(func)5.5 V - 18 V
Extended operating voltageVS(ext)4.5 V - 36 V
Maximum load currentISENSE(max)400 mA
Output current accuracyVSENSE(reg)±4% with VSENSE = 400 mV
Current consumption in sleep modeIVS(sleep, max)3 μA
Maximum current consumption during faultIVS(fault, ERRN)850 μA
Maximum dropout voltageVDR,CS(max)0.6 V

Block diagram

Figure 1. TLD1173-1ET Block diagram


Figure 2. TLD2362-3ET Block diagram


Figure 3. TLD2372-3ET Block diagram


Figure 4. TLD2382-3ET Block diagram


Figure 5. TLD2382-3ET Block diagram


Pin configuration

Pin assignment

Figure 6. PG-TFDSO-16


Figure 7. Pin configuration PG-TFDSO-16


Figure 8. Pin configuration PG-TFDSO-16


Figure 9. Pin configuration PG-TFDSO-16


Pin definitions and functions

Table 4. Pin definitions and functions
PinSymbolFunction
16VS

Power supply voltage

Battery supply input

4GND

Ground

Ground potential. Connect externally close to the chip

8EN/DEN

Output enable and diagnosis control input

Connect to VS via a resistor divider to enable OUT control and diagnosis capability

9ERRN/DEN

ERROR flag I/O and diagnosis control input

Open drain, active low. Connect to VS via pull-up resistor for ERROR flag capability only otherwise connect to VS via a resistor divider to enable diagnosis capability

6SENSE

Sense input

Connect to low ohmic accurate sense resistor

14OUT

Channel output pin

Open drain linear current sink. Connect to the target load

15PS

Power shift

Connect to external power resistor

2D

Disable/delay error input

Connect to a capacitor, leave open or connect to GND depending on the required diagnostic management

5ACC/PWMI

Analog current control and PWMI input pin

Connect to external low power resistor or apply a desired reference voltage to adjust the output current. Connect to external NTC to apply thermal derating. It is possible also to connect to an external open drain PWM controller

3IREF

Current reference generation

Connect to an external accurate low power resistor to generate a current reference

1,7,10,

11,12,13

NC

Not connected

Leave these pins open

Exposed padEP

Exposed pad

Used only for thermal dissipation purpose. Connect externally to GND close to the chip

Table 5. Pin definitions and functions
PinSymbolFunction
16VS

Power supply voltage

Battery supply input

4GND

Ground

Ground potential. Connect externally close to the chip

1EN/DEN1

Output 1 enable and diagnosis control input

Connect to VS via a resistor divider to enable OUT1 control and diagnosis capability

2EN/DEN2

Output 2 enable and diagnosis control input

Connect to VS via a resistor divider to enable OUT2 control and diagnosis capability

3EN/DEN3

Output 3 enable and diagnosis control input

Connect to VS via a resistor divider to enable OUT3 control and diagnosis capability

9ERRN/DEN

ERROR flag I/O and diagnosis control input

Open drain, active low. Connect to VS via pull-up resistor for ERROR flag capability only otherwise connect to VS via a resistor divider to enable diagnosis capability

6SENSE1

Sense input 1

Connect to low ohmic accurate sense resistor

7SENSE2

Sense input 2

Connect to low ohmic accurate sense resistor

8SENSE3

Sense input 3

Connect to low ohmic accurate sense resistor

14OUT1

Channel 1, output pin

Open drain linear current sink. Connect to the target load

15PS1

Power shift 1

Connect to external power resistor

12OUT2

Channel 2, output pin

Open drain linear current sink. Connect to the target load

13PS2

Power shift 2

Connect to external power resistor

10OUT3

Channel 3, output pin

Open drain linear current sink. Connect to the target load

11PS3

Power shift 3

Connect to external power resistor

5ACC/PWMI

Analog current control and PWMI input pin

Connect to external voltage reference to adjust the output current. Connect to external NTC to apply thermal derating. It is possible also to connect to an external open drain PWM controller

Exposed padEP

Exposed pad

Used only for thermal dissipation purpose. Connect externally to GND close to the chip

Table 6. Pin definitions and functions
PinSymbolFunction
16VS

Power supply voltage

Battery supply input

4GND

Ground

Ground potential. Connect externally close to the chip

1EN/DEN

Output enable and diagnosis control input

Connect to VS via a resistor divider to enable all outputs control and diagnosis capability

2D

Disable/delay error input

Connect to a capacitor, leave open or connect to GND depending on the required diagnostic management

3IREF

Current reference generation

Connect to an external accurate low power resistor to generate a current reference

9ERRN/DEN

ERROR flag I/O and diagnosis control input

Open drain, active low. Connect to VS via pull-up resistor for ERROR flag capability only otherwise connect to VS via a resistor divider to enable diagnosis capability

6SENSE1

Sense input 1

Connect to low ohmic accurate sense resistor

7SENSE2

Sense input 2

Connect to low ohmic accurate sense resistor

8SENSE3

Sense input 3

Connect to low ohmic accurate sense resistor

14OUT1

Channel 1, output pin

Open drain linear current sink. Connect to the target load

15PS1

Power shift 1

Connect to external power resistor

12OUT2

Channel 2, output pin

Open drain linear current sink. Connect to the target load

13PS2

Power shift 2

Connect to external power resistor

10OUT3

Channel 3, output pin

Open drain linear current sink. Connect to the target load

11PS3

Power shift 3

Connect to external power resistor

5ACC/PWMI

Analog current control and PWMI input pin

Connect to external low power resistor or apply a desired reference voltage to adjust the output current. Connect to external NTC to apply thermal derating. It is possible also to connect to an external open drain PWM controller

Exposed padEP

Exposed pad

Used only for thermal dissipation purpose. Connect externally to GND close to the chip

Table 7. Pin definitions and functions
PinSymbolFunction
16VS

Power supply voltage

Battery supply input

4GND

Ground

Ground potential. Connect externally close to the chip

2D

Disable/delay error input

Connect to a capacitor, leave open or connect to GND depending on the required diagnostic management

3IREF

Current reference generation

Connect to an external accurate low power resistor to generate a current reference

9ERRN/DEN

ERROR flag I/O and diagnosis control input

Open drain, active low. Connect to VS via pull-up resistor for ERROR flag capability only otherwise connect to VS via a resistor divider to enable diagnosis capability

6SENSE1

Sense input 1

Connect to low ohmic accurate sense resistor

7SENSE2

Sense input 2

Connect to low ohmic accurate sense resistor

8SENSE3

Sense input 3

Connect to low ohmic accurate sense resistor

15EN/DEN1

Output 1 enable and diagnosis control input

Connect to VS via a resistor divider to enable OUT1 control and diagnosis capability

14OUT1

Channel 1, output pin

Open drain linear current sink. Connect to the target load

13EN/DEN2

Output 2 enable and diagnosis control input

Connect to VS via a resistor divider to enable OUT2 control and diagnosis capability

12OUT2

Channel 2, output pin

Open drain linear current sink. Connect to the target load

11EN/DEN3

Output 3 enable and diagnosis control input

Connect to VS via a resistor divider to enable OUT3 control and diagnosis capability

10OUT3

Channel 3, output pin

Open drain linear current sink. Connect to the target load

1NC

Not connected

Leave this pin open

5ACC/PWMI

Analog current control and PWMI input pin

Connect to external low power resistor or apply a desired reference voltage to adjust the output current. Connect to external NTC to apply thermal derating. It is possible also to connect to an external open drain PWM controller

Exposed padEP

Exposed pad

Used only for thermal dissipation purpose. Connect externally to GND close to the chip

General product characteristics

Absolute maximum ratings

Table 8. Absolute maximum ratings

 TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or condition P-Number
Min. Typ. Max.

Voltages

Supply voltage

VS

-0.3

–

40

V

–

PRQ-32

EN/DEN voltage

VEN/DEN

-0.3

–

40

V

–

PRQ-55

EN/DENx voltage

VEN/DENx

-0.3

–

40

V

–

PRQ-57

Output voltage

VOUT

-0.3

–

40

V

– 

PRQ-56

Output voltages

VOUTx

-0.3

–

40

V

– 

PRQ-58

Power shift voltage

VPS

-0.3

–

40

V

– 

PRQ-59

Power shift voltages

VPSx

-0.3

–

40

V

– 

PRQ-60

Sense voltage

VSENSE

-0.3

–

0.9

V

– 

PRQ-63

Sense voltage

VSENSEx

-0.3

–

0.9

V

– 

PRQ-62

ERRN/DEN voltage

VERRN/DEN

-0.3

–

40

V

–

PRQ-61

D voltage

VD

-0.3

–

5.5

V

– 

PRQ-175

ACC/PWMI voltage

VACC/PWMI

-0.3

–

5.5

V

– 

PRQ-64

IREF voltage

VIREF

-0.3

–

5.5

V

– 

PRQ-176

Temperatures

Junction temperature

TJ_ABS

-40

–

150

°C

– 

PRQ-39

Storage temperature

TSTG

-55

–

150

–

–

PRQ-40

ESD robustness

ESD robustness all pins (HBM)

VESD(HBM)

-2

–

2

kV

ESD robustness, Human Body Model “HBM” according to AEC Q100-002

PRQ-53

ESD robustness all pins (CDM)

VESD(CDM)

-500

–

500

V

ESD robustness, Charged Device Model “CDM” according to AEC Q100-011 Rev.D

PRQ-41

ESD robustness corner pins (CDM)

VESD(CDM) CR

-750

–

750

V

ESD robustness, Charged Device Model “CDM” according to AEC Q100-011 Rev.D

PRQ-54

Note:

Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 

Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as outside the normal operating range. Protection functions are not designed for continuous repetitive operation.

Functional range

Table 9. Functional rangeTJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or condition P-Number
Min. Typ. Max.

Voltages

Supply voltage for operating range

VS(func)

5.5

–

18

V

–

PRQ-33

Extended supply voltage for operating range

VS(ext)

4.5

–

36

V

– 

PRQ-71

Currents

Channel output current

ISENSEx(func)

5

–

150

mA

– 

PRQ-223

Channel output current

ISENSE(func)

5

–

400

mA

– 

PRQ-224

Power dissipation

Max. static and dynamic power dissipation

Pmax

–

–

1.5

W

TA = 85°C and RthJA = 40 K/W 

PRQ-178

Max. static and dynamic power dissipation

Pmax

1.5

W

TA = 85°C and RthJA = 42 K/W

PRQ-419

Temperatures

Junction temperature

TJ(func)

-40

–

150

°C

–

PRQ-72

Note:

Within the functional or operating range, the IC operates as described in the circuit description. Within the Extended Operation range, parameters deviations are possible. The electrical characteristics are specified within the conditions given in the electrical characteristics table.

Thermal resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org

Table 10. Thermal resistanceVS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or condition P-Number
Min. Typ. Max.

Junction to top

ΨJTOP

–

8

–

K/W

PRQ-34

Junction to top

ΨJTOP

–

7

–

K/W

PRQ-262

Junction to case

RthJC

–

8

–

K/W

PRQ-49

Junction to case

RthJC

 

–

6

 

–

K/W

PRQ-263

Junction to ambient 1s0p board

RthJA1

–

64

–

K/W

TA = 85°C

PRQ-48

Junction to ambient 1s0p board

RthJA1

–

61

–

K/W

TA = 85°C

PRQ-264

Junction to ambient 2s2p board

RthJA2

–

42

–

K/W

TA = 85°C

PRQ-180

Junction to ambient 2s2p board

RthJA2

–

40

–

K/W

TA = 85°C

PRQ-265

Internal supply

This chapter describes the internal supply, its main parameters and functionality.

Description

As soon as the voltage applied at the supply pin VS is above VSUV(th) and the voltage applied at the EN/DEN pin is above VEN(th), the device is ready to deliver output current from the output stage after the power on reset time tPOR. When the supply voltage VS is below the threshold VSUV(th), the internal Power-ON-Reset (POR) function holds the device in reset state.

The power on reset time tPOR has to be taken into account under relevant application conditions, i.e. with PWM control from VS.

As soon as the voltage applied at the supply pin VS is above VSUV(th) and the voltage applied at the EN/DENx pins is above VENx(th), the device is ready to deliver output current from the output stages after the power on reset time tPOR. When the supply voltage VS is below the threshold VSUV(th), the internal Power-ON-Reset (POR) function holds the device in reset state.

The power on reset time tPOR has to be taken into account under relevant application conditions, i.e. with PWM control from VS. 

Figure 10. Power on reset timing diagram


Figure 11. Power on reset timing diagram


Figure 12. Power on reset timing diagram


If the voltage applied at the EN/DEN pin is below VEN(th) for more than tSLEEP the device enters sleep mode. In this state all internal functions are switched off and the current consumption is reduced to IVS(sleep).

If the voltage applied at all the EN/DENx pins is below VENx(th) for more than tSLEEP the device enters sleep mode. In this state all internal functions are switched off and the current consumption is reduced to IVS(sleep).

Electrical characteristics

Table 11. Electrical characteristics

VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or condition P-Number
Min. Typ. Max.

Current consumption, sleep mode

IVS(sleep)

–

–

3

µA

VEN/DENx = 0 V

TJ = 150°C

PRQ-84

Current consumption, sleep mode

IVS(sleep)

–

–

3

µA

VEN/DEN = 0 V

TJ =  150°C

PRQ-85

Current consumption, active mode (no fault)

IVS(active)

–

2.5

3.5

mA

VEN/DENx = 5.5 V

VACC/PWMI = 2.4 V

IREF pin left open

PRQ-86

Current consumption, active mode (no fault)

IVS(active)

–

2.5

3.5

mA

VEN/DENx = 5.5 V

VACC/PWMI = 2.4 V

PRQ-306

Current consumption, active mode (no fault)

IVS(active)

–

2.5

3.5

mA

VEN/DEN = 5.5 V

VACC/PWMI = 2.4 V

IREF pin left open

PRQ-154

Current consumption during fault condition (1-fail-all-OFF)

IVS(fault, ERRN)

–

–

850

µA

VEN/DEN = 5.5 V

VERRN = 0 V

D pin open

PRQ-87

Current consumption during fault condition (1-fail-all-OFF)

IVS(fault, ERRN)

–

–

850

µA

VEN/DENx = 5.5 V

VERRN = 0 V

PRQ-162

Current consumption during fault condition (1-fail-all-OFF)

IVS(fault, ERRN)

–

–

850

 

µA

VEN/DENx = 5.5 V

VERRN = 0 V

D pin left open

PRQ-307

VS undervoltage threshold

VSUV(th)

3.5

–

4.5

V

–

PRQ-89

EN/DENx outputs enable threshold

VENx(th)

0.6

–

1.8

V

–   

PRQ-92

EN/DEN outputs enable threshold

VEN(th)

0.6

–

1.8

V

– 

PRQ-159

EN/DENx outputs enable hysteresis

VENx(hys)

80

120

–

mV

PRQ-93

EN/DEN outputs enable hysteresis

VEN(hys)

80

120

–

mV

PRQ-160

EN/DENx pull-down current

IEN/DENx(PD)

–

–

5

µA

VEN/DENx = 3 V

PRQ-96

EN/DENx pull-down current

IEN/DENx(PD)

–

–

150

µA

VEN/DENx = 18 V

PRQ-370

EN/DEN pull-down current

IEN/DEN(PD)

–

–

5

µA

VEN/DEN = 3 V

PRQ-161

EN/DEN pull-down current

IEN/DEN(PD)

–

–

150

µA

VEN/DEN = 18 V

PRQ-371

Power on reset delay time

tPOR

–

–

75

µs

VS rising edge from 0 V to 8 V to 10% of output current

VEN/DENx = 5.5 V

VACC/PWMI ≥ 2.4 V

PRQ-99

Power on reset delay time

tPOR

–

–

75

µs

VS rising edge from 0 V to 8 V to 10% of output current

VEN/DEN = 5.5 V

VACC/PWMI ≥ 2.4 V

PRQ-164

Sleep mode filter time

tSLEEP

15

–

45

ms

– 

PRQ-109

Power stage

The power stage sinks from the OUT pin an output current IOUT which is a function of the external sense resistor placed at SENSE pin.

The maximum output current is limited by the power dissipation Pmax and used cooling areas.

The power stages sinks from the OUTx pins an output current IOUTx which is a function of the external sense resistors placed at SENSEx pins.

The overall maximum output current is limited by the power dissipation and used cooling areas.

Figure 13. Power stage block diagram


Figure 14. Power stages block diagram


Output current regulation

The output current regulation block controls the LEDs current by regulating the voltage drop VSENSE(reg) on the external low-side current-sense resistor RSENSE placed between SENSE pin and GND.

The output current regulation block controls the LEDs current by regulating the voltage drop VSENSEx(reg) on the external low-side current-sense resistors RSENSEx placed between SENSEx pin and GND.

When the LEDs current is in regulation, the LEDs current value can be calculated by using the following equation:

ISENSE=VSENSE(reg)RSENSE

When the LEDs current is in regulation, the LEDs current value for each channel can be calculated by using the following equation:

ISENSEx=VSENSEx(reg)RSENSEx

For an operating output current control loop, the power stage dropout voltage (VDR,CS), the VSENSE(reg) voltage, the forward voltage VD_RP of the reverse polarity protection diode (when used) and the minimum supply voltage have to be considered in the LED string design.

To grant a proper control of the output current the following equation has to be satisfied:

VS≥VSENSE(reg)+VDR,CS+VLED_STRING+VD_RP

For an operating output current control loop, the power stages dropout voltage (VDR,CSx), the VSENSEx(reg) voltage, the forward voltage VD_RP of the reverse polarity protection diode (when used) and the minimum supply voltage have to be considered in the LED string design.

To grant a proper control of the output current the following equation has to be satisfied:

VS≥VSENSEx(reg)+VDR,CSx+VLED_STRINGx+VD_RP

In case the supply voltage drops below the minimum requested, the LEDs current is no longer properly regulated. Consequently, a lower current is delivered and the voltage across the RSENSE resistor is lower than the expected VSENSE(reg).

In case the supply voltage drops below the minimum requested by a particular channel, the LEDs current of that channel is no longer properly regulated. Consequently, a lower current is delivered and the voltage across the RSENSEx resistor is lower than the expected VSENSEx(reg).

Note:
The RSENSE has to be placed as close as possible to the pin VSENSE to avoid current regulation instability.

Thermal protection

A thermal protection function is integrated into the device to prevent IC damage under fault conditions described in the datasheet. Fault conditions are considered as "outside" the normal operating range. Protective functions are not designed for continuous operations.

The thermal protection function is achieved by temperature monitoring of the power stage. As soon as the junction temperature exceeds the overtemperature threshold TJSD:

  • The output current is disabled by turning off the power stage
  • The ERRN/DEN pin is pulled low
  • The current consumption is below IVS(fault, ERRN)

The thermal protection function is achieved by temperature monitoring of the power stages. As soon as the junction temperature exceeds the overtemperature threshold TJSD:

  • The output currents are disabled by turning off the power stages
  • The ERRN/DEN pin is pulled low
  • The current consumption is below IVS(fault, ERRN)

Once the junction temperature falls below TJSD - TJ(hys):

  • The power stage recovers to normal operation
  • The ERRN/DEN pin is released

Once the junction temperature falls below TJSD - TJ(hys):

  • The power stages recover to normal operation
  • The ERRN/DEN pin is released

Electrical characteristics

Table 12. Electrical characteristics

VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or condition P-Number
Min. Typ. Max.
Leakage currents

Output leakage current

IOUTx(leak)

–

–

1

µA

 TJ = 85°C

VOUTx ≤ 16 V

VACC/PWMI = 0 V

VEN/DENx = 5.5 V

PRQ-115

Output leakage current

IOUTx(leak)

–

–

1

µA

 TJ = 85°C

VOUTx ≤ 16 V

VACC/PWMI = 0 V

VEN/DEN = 5.5 V

PRQ-308

Output leakage current

IOUT(leak)

–

–

1

µA

  TJ = 85°C

VOUT ≤ 16 V

VACC/PWMI = 0 V

VEN/DEN = 5.5 V

PRQ-116

Output leakage currents

IOUTx(leak)

–

–

3

µA

TJ = 150°C

VOUTx ≤ 16 V

VACC/PWMI = 0 V

VEN/DENx = 5.5 V

PRQ-117

Output leakage currents

IOUTx(leak)

 

–

 

–

3

µA

TJ = 150°C

VOUTx ≤ 16 V

VACC/PWMI = 0 V

VEN/DEN = 5.5 V

PRQ-309

Output leakage current

IOUT(leak)

–

–

5

µA

TJ = 150°C

VOUT ≤ 16 V

VACC/PWMI = 0 V

VEN/DEN = 5.5 V

PRQ-118

Sense regulation voltage accuracy

SENSE voltage regulation accuracy

VSENSE(reg)

384

400

416

mV

VACC/PWMI ≥ 2.4 V

PRQ-120

SENSEx voltage regulation accuracy

VSENSEx(reg)

384

400

416

mV

VACC/PWMI ≥ 2.4 V

PRQ-135

SENSE voltage regulation accuracy

VSENSE(reg)

95

100

105

mV

VACC/PWMI = 0.9 V

PRQ-121

SENSEx voltage regulation accuracy

VSENSEx(reg)

95

100

105

mV

VACC/PWMI = 0.9 V

PRQ-137

SENSE voltage regulation accuracy

VSENSE(reg)

14

20

26

mV

VACC/PWMI = 0.5 V

PRQ-123

SENSEx voltage regulation accuracy

VSENSEx(reg)

14

20

26

mV

VACC/PWMI = 0.5 V

PRQ-139

Power stage drop out

Power stage drop out voltage

VDR,CS

–

–

0.6

V

IOUT = 400 mA

PRQ-124

Power stages drop out voltage

VDR,CSx

–

–

0.6

V

IOUTx = 150 mA

PRQ-126

Power stages drop out voltage

VDR,CSx

–

–

0.54

V

IOUTx = 150 mA

PRQ-225

Thermal protection thresholds

Overtemperature shutdown threshold

TJSD

165

175

185

°C

 

PRQ-131

Overtemperature hysteresis

TJ(hys)

5

10

15

°C

 15

PRQ-132

PWM control

PWM dimming is adopted to vary LEDs brightness with greatly reduced chromaticity shift. PWM dimming achieves brightness reduction by varying the duty cycle of a constant current in the LED string.

The PWM modulation is performed via the ACC/PWMI pin. The power stage and the power shift are disabled if the voltage applied on the ACC/PWMI pin is lower than VPWM(OFF) while they are enabled if the voltage applied on the PWMI/ACC pin is higher than VPWM(ON).

The PWM modulation is performed via the ACC/PWMI pin. The power stages and the power shift blocks are disabled if the voltage applied on the ACC/PWMI pin is lower than VPWM(OFF) while they are enabled if the voltage applied on the ACC/PWMI pin is higher than VPWM(ON).

The PWM modulation is performed via the ACC/PWMI pin. The power stages are disabled if the voltage applied on the ACC/PWMI pin is lower than VPWM(OFF) while they are enabled if the voltage applied on the ACC/PWMI pin is higher than VPWM(ON).

In Figure 15 two examples of PWM dimming are shown via the ACC/PWMI input pin:

  1. In case a resistor is needed on the ACC/PWMI input pin to apply analog current control (i.e. binning or thermal derating) the PWM signal can be applied using an open drain output from the PWM generator
  2. In case the analog current control function is not needed a push-pull output from the PWM generator can be used to apply the PWM modulation

In Figure 16 two examples of PWM dimming are shown via the ACC/PWMI input pin:

  1. In case a resistor is needed on the ACC/PWMI input pin to apply analog current control (i.e. binning or thermal derating) the PWM signal can be applied using an open drain output from the PWM generator
  2. In case the analog current control function is not needed a push-pull output from the PWM generator can be used to apply the PWM modulation
Figure 15. PWM control via ACC/PWMI input pin


Figure 16. PWM control via ACC/PWMI input pin


The PWM signal can be applied via the EN/DENx pins as well to allow PWM modulation on each channel independently. After the exit from sleep state the tPOR delay time has to be considered on the first PWM pulse generation.

The PWM signal can be applied via the EN/DEN pin as well to allow PWM modulation from the battery line. Indeed by applying a proper filtering on the VS pin to avoid to trigger the VS undervoltage threshold, the tPOR delay time would be applied only on the first PWM pulse generation after the exit from sleep state, like shown if Figure 23. 

The PWM signal can be applied via the EN/DEN pin as well to allow PWM modulation from the battery line. Indeed by applying a proper filtering on the VS pin to avoid to trigger the VS undervoltage threshold, the tPOR delay time would be applied only on the first PWM pulse generation after the exit from sleep state, like shown in Figure 24.

When applied on the EN/DENx the PWM signal has a frequency range fPWM to avoid to turn-off any channels by triggering the tSLEEP filter time.

When applied on the EN/DEN pin the PWM signal has a frequency range fPWM to avoid to turn-off the channels by triggering the tSLEEP filter time.

When applied on the EN/DEN pin the PWM signal has a frequency range fPWM to avoid to turn-off the channel by triggering the tSLEEP filter time.

The power stage and the power shift of each channel are enabled if the voltage applied on the EN/DENx pin is higher than VENx(th) while they are disabled if the voltage applied on the EN/DENx pin is lower than VENx(th).

The power stage and the power shift of all the channels are enabled if the voltage applied on the EN/DEN pin is higher than VEN(th) while they are disabled if the voltage applied on the EN/DENx pin is lower than VEN(th).

The power stage and the power shift of the channel are enabled if the voltage applied on the EN/DEN pin is higher than VEN(th) while they are disabled if the voltage applied on the EN/DENx pin is lower than VEN(th).

The power stage of each channel is enabled if the voltage applied on the EN/DENx pin is higher than VENx(th) while it is disabled if the voltage applied on the EN/DENx pin is lower than VENx(th).

Figure 17. PWM control via EN/DEN input pin


Figure 18. PWM control via EN/DEN input pin


Figure 19. PWM control via EN/DENx input pins


When the voltage applied on the ACC/PWMI pin is below VPWM(OFF), the load diagnostic is disabled unless a fault was previously detected.

When the voltage applied on the EN/DENx pin is below VDENx(th), the load diagnostic of the related channel is disabled unless a fault was previously detected.

As well, when the voltage applied on the EN/DEN pin is below VDEN(th), the load diagnostic is disabled unless a fault was previously detected.

While if the voltage applied on the ACC/PWMI pin is below VPWM(OFF), the load diagnostic of all the channels is disabled unless a fault was previously detected.

In particular, if a fault is already present when the voltage applied on the ACC/PWMI pin is below VPWM(OFF) or the voltage applied on EN/DENx pin is below VDENx(th) the diagnostic is kept active until the fault condition disappears, after that it is then disabled.

In particular, if a fault is already present when the voltage applied on the ACC/PWMI pin is below VPWM(OFF) or the voltage applied on EN/DEN pin is below VDEN(th) the diagnostic is kept active until the fault condition disappears, after that it is then disabled.

The PWM control block implements a slope control of the VSENSE voltage in order to improve EMC performances. The slew rate timings are defined by dV/dtON and dV/dtOFF parameters.

The PWM control block implements a slope rate control of the VSENSEx voltages in order to improve EMC performances. The slew rate timings are defined by dV/dtON and dV/dtOFF parameters.

Figure 20. PWMI control timing diagram for VACC/PWMI ≥ 2.4 V


Figure 21. PWMI control timing diagram for VACC/PWMI ≥ 2.4 V


Figure 22. PWM control on EN/DENx timing diagrams for VACC/PWMI ≥ 2.4 V


Figure 23. PWM control on EN/DEN timing diagrams for VACC/PWMI ≥ 2.4 V


Figure 24. PWM control on EN/DEN timing diagrams for VACC/PWMI ≥ 2.4 V


Electrical characteristics

Table 13. Electrical characteristicsVS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or condition P-Number
Min. Typ. Max.

PWM turn off threshold

VPWM(OFF)

0.35

0.4

–

V

– 

PRQ-145

PWM turn on threshold

VPWM(ON)

–

–

0.45

V

– 

PRQ-261

PWM frequency range

fPWM

100

–

–

Hz

PRQ-146

PWM turn on time

tON

–

–

20

µs

16 VSENSE rising to 80% of regulation

VACC/PWMI ≥ 2.4 V

PRQ-147

PWM turn on time

tON

–

–

20

µs

16 VSENSEx rising to 80% of regulation

VACC/PWMI ≥ 2.4 V

PRQ-356

PWM turn off time

tOFF

–

–

20

µs

16 VSENSE falling to 20% of regulation

VACC/PWMI falling from ≥ 2.4 V to less than VPWM(OFF)

PRQ-148

PWM turn off time

tOFF

–

–

20

µs

16 VSENSEx falling to 20% of regulation

VACC/PWMI falling from ≥ 2.4 V to less than VPWM(OFF)

PRQ-357

VSENSE rising slew rate

dV/dtON

15

35

50

mV/µs

16 VSENSE rising from 20% to 80% of regulation

VACC/PWMI ≥ 2.4 V

PRQ-149

VSENSE rising slew rate

dV/dtON

15

35

50

mV/µs

16 VSENSEx rising from 20% to 80% of regulation

VACC/PWMI ≥ 2.4 V

PRQ-358

VSENSE falling slew rate

dV/dtOFF

-50

-35

-15

mV/µs

16 VSENSE falling from 80% to 20% of regulation

VACC/PWMI falling from ≥ 2.4 V to less than VPWM(OFF)

PRQ-150

VSENSE falling slew rate

dV/dtOFF

-50

-35

-15

mV/µs

16 VSENSEx falling from 80% to 20% of regulation

VACC/PWMI falling from ≥ 2.4 V to less than VPWM(OFF)

PRQ-359

Analog output current control

The analog output current control function adjusts the VSENSE voltage by sensing the applied voltage on the ACC/PWMI pin VACC/PWMI.

The analog output current control function adjusts the VSENSEx voltages by sensing the applied voltage on the ACC/PWMI pin VACC/PWMI.

As described in Power stage the output current provided by the channel is a direct function of the regulated voltage VSENSE. In this way by adjusting the voltage applied on the ACC/PWMI pin it is possible to control the output current. 

As described in Power stage the output current provided by each channel is a direct function of the regulated voltage VSENSEx. In this way by adjusting the voltage applied on the ACC/PWMI pin it is possible to control the output current of all the channels. 

ISENSE=0.2×VACC/PWMI-0.08 VRSENSE
ISENSEx=0.2×VACC/PWMI-0.08 VRSENSEx

The relation between the ACC/PWMI voltage VACC/PWMI and the respective regulated voltage VSENSE is shown in the Figure 25.

The relation between the ACC/PWMI voltage VACC/PWMI and the respective regulated voltages VSENSEx is shown in the Figure 26.

Figure 25. Analog output current control


Figure 26. Analog output current control


The voltage on ACC/PWMI can be set by applying an accurate external resistor on the ACC/PWMI pin. In case the resistor is placed in another PCB (i.e. binning resistor) it is recommended to add capacitor of 220 nF close to the ACC/PWMI pin.

The ACC/PWMI pin outputs a constant current based on the IREF output current and the ACC current ratio IACC/IIREF.

Note:

In case the analog output current control function is not needed it is recommended to put 100 kΩ pull-down resistor on the IREF pin to proper bias the ACC/PWMI voltage to avoid wrong VSENSE setting.

Note:

In case the analog output current control function is not needed it is recommended to leave the ACC/PWMI pin open. Indeed the internal pull-up current IACC can be used to bias the ACC/PWMI voltage to avoid wrong VSENSE setting.

Figure 27. Analog output current control configurations


Figure 28. Analog output current control configurations


Electrical characteristics

Table 14. Electrical characteristicsVS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or condition P-Number
Min. Typ. Max.

ACC pull-up current

IACC

8

12.5

17

µA

current flowing outside the pin

PRQ-220

ACC current ratio

IACC/IIREF

4.85

5

5.15

–

20 μA ≤ IIREF ≤ 250 μA

PRQ-253

Current reference generation

The current reference generation block, outputs an accurate output reference current with low temperature shift.

The voltage on the IREF pin is regulated in the VIREF range.

It turns out that the reference current can be set by placing an external resistor from IREF pin to GND and can be calculated using the following formula:

IIREF=VIREFRIREF
Note:
The RIREF has to be placed as close as possible to the pin IREF to avoid current regulation instability.

Electrical characteristics

Table 15. Electrical characteristicsVS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or condition P-Number
Min. Typ. Max.

IREF regulated voltage

VIREF

1.164

1.2

1.236

V

– 

PRQ-268

IREF current range

IIREF

–

–

250

μA

–

PRQ-269

IREF capacitance

CIREF

– 

– 

0.22

nF

PRQ-273

Load diagnostics

Several diagnosis features are integrated:

  • Open load detection (OL)
  • Short to supply detection (SC)
  • Power shift short to supply detection (SC)
  • Overtemperature thermal detection (OT)

 Several diagnosis features are integrated:

  • Open load detection (OL)
  • Short to supply detection (SC)
  • Overtemperature thermal detection (OT)

The behavior of the device during overload conditions that lead to an excess of internal heating, up to overtemperature condition, is already described in chapter Thermal protection.

An open load condition is detected if the voltage across the power stage VDR = VOUT - VSENSE is below the threshold VDR(OL) for at least a filter time tfault.

An open load condition is detected if the voltage across the power stage VDRx = VOUTx - VSENSEx is below the threshold VDR(OL) for at least a filter time tfault.

A short to supply condition is detected if the output voltage drop over the load VS - VOUT is below the threshold VOUT(SC) for at least a filter time tfault.

A short to supply condition is detected if the output voltage drop over one of the loads VS - VOUTx is below the threshold VOUT(SC) for at least a filter time tfault.

A power shift short to supply condition is detected if the power shift voltage drop VS - VPSx is below the threshold VPS(SC) for at least a filter time tfault.

A power shift short to supply condition is detected if the power shift voltage drop VS - VPS is below the threshold VPS(SC) for at least a filter time tfault.

If an OL condition is detected on the OUT pin or a SC condition is detected on one of the OUT or PS pins, a pull-down current IOUT(fault) flows inside the OUT pin replacing the configured output current. Only in case of 1-fail-all-OFF configuration (D pin open or connect to a capacitor) any further fault on additional channels leads to turn-off the channel without replacing the configured output current with the IOUT(fault).

If an OL condition is detected on the OUT pin or a SC condition is detected on one of the OUT or PS pins, a pull-down current IOUT(fault) flows inside the OUT pin replacing the configured output current. Any further fault on additional channels leads to turn-off the channel without replacing the configured output current with the IOUT(fault).

If an OL condition is detected on the OUT pin or a SC condition is detected on one of the OUT or PS pins, a pull-down current IOUT(fault) flows inside the OUT pin replacing the configured output current. 

If an OL condition is detected on the OUT pin or a SC condition is detected on one of the OUT or PS pins, a pull-down current IOUT(fault) flows inside the OUT pin replacing the configured output current.

If an OL or SC condition is detected on the OUT pin a pull-down current IOUT(fault) flows inside the OUT pin replacing the configured output current. Only in case of 1-fail-all-OFF configuration (D pin open or connect to a capacitor) any further fault on additional channels leads to turn-off the channel without replacing the the configured output current with the IOUT(fault).

It turns out that in case of multiple faults on different channels of the same device configured with the 1-fail-all-OFF fault management, only one channel at time will provide the IOUT(fault) current.

Note:

The IOUT(fault) current is limited by the actual load impedance, e.g. it is reduced to zero with an ideal open load.

Diagnostics enable

As soon as the voltage applied at the supply pin VS is above VSUV(th) and the voltage applied to the EN/DEN pin is above VDEN(th), the device is ready to detect and report fault conditions via ERRN/DEN pin.

There are several possibilities to program the output enable and diagnosis enable via EN/DEN pin, like a resistor divider from VS to GND, a Zener diode from EN/DEN to VS and also a logic control pin (e.g. from a microcontroller output).

As soon as the voltage applied at the supply pin VS is above VSUV(th) and the voltage applied to the EN/DENx pins is above VDENx(th), the device is ready to detect and report fault conditions via ERRN/DEN pin.

There are several possibilities to program the output enable and diagnosis enable via EN/DENx pins, like a resistor divider from VS to GND, a Zener diode from EN/DENx to VS and also a logic control pin (e.g. from a microcontroller output).

Figure 29. EN/DEN block diagram


Figure 30. EN/DEN block diagram


Figure 31. EN/DEN block diagram


ERRN/DEN pin

The device is able to report a detected failure in its driven load and react to a fault detected by another LED driver in the system if a shared error network is implemented (i.e. driving LED chains of the same light function). This is possible with the usage of an external pull-up resistor, allowing multiple devices to share the open-drain diagnostic output pin ERRN/DEN. All devices sharing a common error network are capable to detect the fault from any of the channels driven by the Basic+ family.

The device is able to report a detected failure in one of its driven loads and react to a fault detected by another LED driver in the system if a shared error network is implemented (i.e. driving LED chains of the same light function). This is possible with the usage of an external pull-up resistor, allowing multiple devices to share the open-drain diagnostic output pin ERRN/DEN. All devices sharing a common error network are capable to detect the fault from any of the channels driven by the Basic+ family.

The device is able to report a detected failure in one of its driven loads via the ERRN/DEN network.

The open-drain ERRN/DEN pin applies a pull-down resistance RERRN(ON) towards GND when a fault condition is detected for at least a filter time tfault. Therefore, an active low state can be detected at ERRN/DEN pin when VERRN < VERRN(fault) and the relative faulty output channel is switched off.

Similarly, when the fault is removed, ERRN/DEN pin is back in high impedance state and the channel reactivation is completed as illustrated in Figure 32.

Figure 32. ERRN/DEN pin block diagram


To enable direct connection from a microcontroller to the EN/DENx pins to apply independent PWM signal modulation, the DEN functionality is duplicated on the ERRN/DEN pin. This functionality enables the possibility to decouple the VDENx(th) threshold from the VENx(th) threshold to have the device turning on as soon as needed independently from the VDENx(th) threshold.

To enable the possibility to decouple the VDEN(th) threshold from the VEN(th) threshold to have the device turning on as soon as needed independently from the diagnostic enable threshold, VDEN(th), the DEN functionality is duplicated on the ERRN/DEN pin.

The diagnostic reporting on ERRN/DEN pin and "open load", "short to supply" and the "power shift short to supply" protections are disabled, unless a fault was previously detected, as soon as one of the following condition is verified:

  • The voltage on the ERRN/DEN pin is VERRN(fault) < VERRN/DEN ≤ VERRN(DEN) 
  • The voltage on EN/DEN pin is below VDEN(th)

The diagnostic reporting on ERRN/DEN pin and "open load", "short to supply" and the "power shift short to supply" protections are disabled, unless a fault was previously detected, as soon as one of the following condition is verified:

  • The voltage on the ERRN/DEN pin is VERRN(fault) < VERRN/DEN ≤ VERRN(DEN) the diagnostic is disabled for all the channels
  • The voltage on EN/DENx pin is below VDENx(th) the diagnostic is disabled for the relative channel

The diagnostic reporting on ERRN/DEN pin and "open load" and "short to supply" protections are disabled, unless a fault was previously detected, as soon as one of the following condition is verified:

  • The voltage on the ERRN/DEN pin is VERRN(fault) < VERRN/DEN ≤ VERRN(DEN) the diagnostic is disabled for all the channels
  • The voltage on EN/DENx pin is below VDENx(th) the diagnostic is disabled for the relative channel

In addition the "open load" protection is disabled as well in case the voltage on the ERRN/DEN pin is VERRN/DEN  ≤ VERRN(fault) on all the channels that are not already in a fault condition.

When the ERRN/DEN pin applies a pull-down resistor RERRN(ON) towards GND the VERRN(DEN) threshold is masked to avoid unwanted toggling of the voltages on the ERRN/DEN pin.

D pin

The D pin is designed for two main purposes:

  • To react to error conditions in LED arrays according to the implementation fault management policy, in systems where multiple LED chains are used for a given function as illustrated in Figure 33
  • To extend the channel's deactivation delay time of a value tD, adding a small signal capacitor from the D-pin to GND. In this way, an unstable or noisy fault condition may be prevented from switching off all the channels of a given light function (i.e. driven by several ICs sharing the same error network)

The functionality of the D-pin is shown in the simplified block diagram illustrated in Figure 34.

Figure 33. D pin configurations


Figure 34. D pin block diagram


In normal operative status (no fault) a pull-down current ID(PD) is sunk from the D-pin to GND.

If there is a fault condition (for at least a filter time tfault) in one of the LED channels driven by the IC or in any of the devices sharing the same ERRN error network line, a pull-up current ID(fault) is instead sourced from the D-pin. 

If a capacitive or open load is applied at this pin (1-fail-all-OFF), its voltage starts rising. When VD(th) is reached at D-pin, all the channels driven by the device are switched off and if other devices share the same ERRN/DEN and D-pins nodes, all the devices turn their outputs off.

Alternatively, if the D-pin is tied to GND (1-fail-all-ON), only the channel that has been detected with a fault is safely deactivated.

The capacitor value used at the D-pin, CD, sets the delay times tD(set/reset) according to the following equations:

tD(set)=CD×VD(th)ID(fault)
tD(reset)=CD×(VD(CL)-(VD(th)-VD(hys)))ID(PD)

Fault management

With D pin open or connected with a capacitor to GND configuration, it is possible to switch off all the channels which share a common error network, without the need of an auxiliary microcontroller. For more details refer also to the timing diagram.

If there is a fault condition at the output or the power shift, the ERRN/DEN pin applies a pull-down resistance RERRN(ON) towards GND and (with proper dimensioning of the external pull-up resistor) reaches a voltage level below VERRN(fault). After tD(set), the voltage VD(th) is reached at D pin. The ERRN/DEN low voltage can also be used as input signal for a microcontroller to perform the desired diagnosis policy.

If there is an OL or SC condition at the output, the ERRN/DEN pin applies a pull-down resistance RERRN(ON) towards GND and (with proper dimensioning of the external pull-up resistor) reaches a voltage level below VERRN(fault). After tD(set), the voltage VD(th) is reached at D pin. The ERRN/DEN low voltage can also be used as input signal for a microcontroller to perform the desired diagnosis policy.

The OL and SC error conditions are not latched: as soon as the fault condition is no longer present, for at least a filter time tfault, ERRN/DEN goes back to high impedance. When its voltage is above VERRN(fault), the D pin voltage starts decreasing and after tD(reset) goes below (VD(th) - VD(th,hys)). 

If there is a fault condition on the output or the power shift, the ERRN/DEN pin applies a pull-down resistance RERRN(ON) towards GND and (with proper dimensioning of the external pull-up resistor) reaches a voltage level below VERRN(fault). It turns out that all the channels are switched off, without the need of an auxiliary microcontroller.

The ERRN/DEN low voltage can also be used as input signal for a microcontroller to perform the desired diagnosis policy.

The OL and SC error conditions are not latched: as soon as the fault condition is no longer present (for at least a filter time tfault) ERRN goes back to high impedance. When its voltage is above VERRN(fault), the output stages are activated again.

Figure 35. Open load condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor)


Figure 36. Output short to supply condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor)


Figure 37. Power shift short to supply condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor)


Figure 38. Open load condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor)


Figure 39. Open load condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor) with digital dimming applied on EN/DENx pins


Figure 40. Output short to supply condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor)


Figure 41. Output short to supply condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor) with digital dimming applied on EN/DENx pins


Figure 42. Power shift short to supply condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor)


Figure 43. Open load condition timing diagram example in 1-fail-all-OFF configuration


Figure 44. Open load condition timing diagram example in 1-fail-all-OFF configuration with digital dimming applied on EN/DENx pins


Figure 45. Output short to supply condition timing diagram example in 1-fail-all-OFF configuration


Figure 46. Output short to supply condition timing diagram example in 1-fail-all-OFF configuration with digital dimming applied on EN/DENx pins


Figure 47. Power shift short to supply condition timing diagram example in 1-fail-all-OFF configuration


Figure 48. Power shift short to supply condition timing diagram example in 1-fail-all-OFF configuration with digital dimming applied on EN/DENx pins


With D pin connected to GND, it is possible to deactivate only the channel under fault condition, still sharing ERRN pin in a common error network with other devices of Basic+ family.

If there is a fault condition at the output or the power shift, the ERRN pin applies a pull-down resistance RERRN(ON) to ground and the voltage level on this pin will drop below VERRN(fault) if the external pull-up resistor is properly dimensioned. The ERRN low voltage can also be used as input signal for a µC to perform the desired diagnosis policy.

If there is an OL or SC condition at the output, the ERRN pin applies a pull-down resistance RERRN(ON) to ground and the voltage level on this pin will drop below VERRN(fault) if the external pull-up resistor is properly dimensioned. The ERRN low voltage can also be used as input signal for a µC to perform the desired diagnosis policy.

The OL and SC error conditions are not latched: as soon as the fault condition is no longer present (for at least for a filter time tfault) ERRN/DEN goes back to high impedance and the output stages are activated again.

The OL and SC error conditions are not latched: as soon as the fault condition is no longer present (for at least for a filter time tfault) ERRN/DEN goes back to high impedance and the output stage is activated again.

If there is a fault condition on the output or the power shift, the ERRN/DEN pin applies a pull-down resistance RERRN(ON) towards GND and (with proper dimensioning of the external pull-up resistor) reaches a voltage level below VERRN(fault). Only the channel under fault condition will be deactivated, still sharing ERRN/DEN pin in a common error network with other devices of Basic+ family, without the need of an auxiliary microcontroller.

The ERRN/DEN low voltage can also be used as input signal for a microcontroller to perform the desired diagnosis policy.

The fault status is not latched: as soon as the fault condition is no longer present (for at least for a filter time tfault), ERRN goes back to high impedance and the output stage which was at fault is activated again.

Figure 49. Open load condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND)


Figure 50. Output short to supply condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND)


Figure 51. Power shift short to supply condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND)


Figure 52. Open load condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND)


Figure 53. Open load condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND) with digital dimming applied on EN/DENx pins


Figure 54. Output short to supply condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND)


Figure 55. Output short to supply condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND) with digital dimming applied on EN/DENx pins


Figure 56. Power shift short to supply condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND)


Figure 57. Open load condition timing diagram example in 1-fail-all-ON configuration


Figure 58. Open load condition timing diagram example in 1-fail-all-ON configuration with digital dimming applied on EN/DENx pins


Figure 59. Output short to supply condition timing diagram example in 1-fail-all-ON configuration


Figure 60. Output short to supply condition timing diagram example in 1-fail-all-ON configuration with digital dimming applied on EN/DENx pins


Figure 61. Power shift short to supply condition timing diagram example in 1-fail-all-ON configuration


Figure 62. Power shift short to supply condition timing diagram example in 1-fail-all-ON configuration with digital dimming applied on EN/DENx pins


Electrical characteristics

Table 16. Electrical characteristics

VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or condition P-Number
Min. Typ. Max.

ERRN/DEN pin

ERRN fault threshold

VERRN(fault)

0.7

–

0.9

V

–

PRQ-193

ERRN ON resistance

RERRN(ON)

–

–

350

Ω

IERRN/DEN = 2 mA

Fault condition

VEN/DEN > VDEN(th)

PRQ-379

ERRN ON resistance

 

RERRN(ON)

–

–

350

Ω

IERRN/DEN = 2 mA

Fault condition

VEN/DENx > VDENx(th)

PRQ-378

ERRN diagnosis enable threshold

VERRN(DEN)

2.1

–

2.3

V

–

PRQ-255

ERRN pull-down current

IERRN_PD

–

–

2

µA

No fault condition

VEN/DEN > VDEN(th)

PRQ-380

Diagnosis enable

DEN diagnosis enable threshold

VDEN(th)

2.3

–

2.7

V

–

PRQ-244

DEN diagnosis enable threshold

VDENx(th)

2.3

–

2.7

V

–

PRQ-246

Protections

OL detection threshold

VDR(OL)

0.2

–

0.4

V

VEN/DENx > VDENx(th)

VERRN/DEN > VERRN(DEN)

PRQ-194

OL detection threshold

VDR(OL)

0.2

–

0.4

V

VEN/DEN > VDEN(th)

VERRN/DEN > VERRN(DEN)

PRQ-285

OUT SC detection threshold

VOUT(SC)

0.8

–

1.35

V

VEN/DENx > VDENx(th)

VERRN/DEN > VERRN(DEN)

PRQ-195

OUT SC detection threshold

VOUT(SC)

0.8

–

1.35

V

VEN/DEN > VDEN(th)

VERRN/DEN > VERRN(DEN)

PRQ-286

PS SC detection threshold

VPS(SC)

0.8

–

1.35

V

VEN/DEN > VDEN(th)

VERRN/DEN > VERRN(DEN)

PRQ-292

PS SC detection threshold

VPS(SC)

0.8

–

1.35

V

VEN/DENx > VDENx(th)

VERRN/DEN > VERRN(DEN)

PRQ-293

Fault detection current

IOUT(fault)

–

–

650

µA

OL or SC fault condition

VEN/DENx > VDENx(th)

VERRN/DEN < VERRN(fault)

PRQ-196

Fault detection current

IOUT(fault)

–

–

650

µA

OL or SC fault condition

VEN/DEN > VDEN(th)

VERRN/DEN < VERRN(fault)

PRQ-294

D pin

Threshold voltage for function de-activation

VD(th)

1.4

1.7

2

V

VEN/DENx > VDENx(th)

VERRN/DEN > VERRN(DEN)

PRQ-197

Threshold voltage for function de-activation

VD(th)

1.4

1.7

2

V

VEN/DEN > VDEN(th)

VERRN/DEN > VERRN(DEN)

PRQ-299

Threshold hysteresis

VD(hys)

70

–

–

mV

VEN/DENx > VDEN(th)

VERRN/DEN > VERRN(DEN)

Not subject to production test, specified by design

PRQ-198

Threshold hysteresis

VD(hys)

70

–

–

mV

VEN/DEN > VDEN(th)

VERRN/DEN > VERRN(DEN) 

Not subject to production test, specified by design

PRQ-300

Fault pull-up current

ID(fault)

20

35

50

µA

OL or SC fault condition

VEN/DENx > VDENx(th)

VERRN/DEN < VERRN(fault)

VD = 2 V

PRQ-199

Fault pull-up current

ID(fault)

20

35

50

µA

OL or SC fault condition

VEN/DEN > VDEN(th)

VERRN/DEN < VERRN(fault)

VD = 2 V

PRQ-301

Pull-down current

ID(PD)

40

60

95

µA

No fault conditions

VEN/DENx > VDENx(th)

VERRN/DEN > VERRN(DEN)

VD = 1.4 V

PRQ-200

Pull-down current

ID(PD)

40

60

95

µA

No fault conditions

VEN/DEN > VDEN(th)

VERRN/DEN > VERRN(DEN)

VD = 1.4 V

PRQ-302

Internal clamp voltage

VD(CL)

2

–

3

V

OL or SC fault condition

VEN/DENx > VDENx(th)

VERRN/DEN < VERRN(fault)

D-pin open

PRQ-201

Internal clamp voltage

VD(CL)

2

–

3

V

OL or SC fault condition

VEN/DEN > VDEN(th)

VERRN/DEN < VERRN(fault)

D-pin open

PRQ-303

Timings

Fault to ERRN delay

tfault

40

–

120

µs

VEN/DENx > VDENx(th)

VERRN/DEN > VERRN(DEN)

PRQ-212

Fault to ERRN delay

tfault

40

–

120

µs

VEN/DEN > VDEN(th)

VERRN/DEN > VERRN(DEN)

PRQ-304

Application information

Note:
The following information is given as an example for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.

Application diagram

Note:
This figure is a simplified example of an application circuit. The function must be verified in the application.
Figure 63. Application diagram example in a shared network with "one fail all off" fault management and central thermal derating


Figure 64. Application diagram example in a shared network with "one fail all off" fault management and central thermal derating


Figure 65. Application diagram example for animated light function in a shared network with "one fail all off" fault management and central thermal derating


Figure 66. Application diagram example in a shared network with "one fail all off" fault management and central thermal derating


Figure 67. Application diagram example for a 5 channels light function in a shared network with "one fail all off" fault management and central thermal derating


Figure 68. Application diagram example for a 5 channels light function in a shared network with "one fail all on" fault management and central thermal derating


Figure 69. Application diagram example for a 5 channels light function in a shared network with "one fail all off" fault management and central thermal derating


Figure 70. Application diagram example for animated light function in a shared network with "one fail all off" fault management and central thermal derating


Figure 71. Application diagram example for a 5 channels light function in a shared network with "one fail all on" fault management and central thermal derating


Figure 72. Application diagram example for animated light function in a shared network with "one fail all on" fault management and central thermal derating


Package information

Figure 73. PG-TFDSO-16 package outline png


Revision history

Document version Date of release Description of changes
Rev. 1.00 2024-10-14
  • Initial document release
1 Not subject to production test, specified by design
2

Specified ΨJTOP is derived under natural convention conditions and provide a correlation between the junction temperature and the temperature on the package top surface. TA = 85°C. Total power dissipation = 1.5 W

3

Specified ΨJTOP is derived under natural convention conditions and provide a correlation between the junction temperature and the temperature on the package top surface. TA = 85°C. Total power dissipation = 1.5 W

4

Specified RthJC is simulated at natural convention on a cold plate setup (all pins and exposed pad are fixed at ambient temperature). TA = 85°C. Total power dissipation = 1.5 W

5

Specified RthJC is simulated at natural convention on a cold plate setup (all pins and exposed pad are fixed at ambient temperature). TA = 85°C. Total power dissipation = 1.5 W

6

Specified RthJA1 is generated in accordance with JEDEC JESD51-3 standards at natural convection on FR4 1s0p board. The simulation has been performed on a 76.2 x 114.3 x 1.5 mm board with 70 μm, 300 mm2 cooling area. Total power dissipation 1.5W distributed statically and homogenously over all power stages

7

Specified RthJA1 is generated in accordance with JEDEC JESD51-3 standards at natural convection on FR4 1s0p board. The simulation has been performed on a 76.2 x 114.3 x 1.5 mm board with 70 μm, 300 mm2 cooling area. Total power dissipation 1.5W distributed statically and homogenously over all power stages

8

Specified RthJA2 is generated in accordance with JEDEC JESD51-5,-7 standards at natural convection on FR4 2s2p board. The simulation has been performed on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers ( 2 x 70 μm Cu, 2 x 35 μm Cu). A total of six thermal via (∅ = 0.3 mm, plating 25 μm) is placed under the exposed pad contacting the first inner copper layer. Total power dissipation 1.5W distributed statically and homogenously over all power stages

9

Specified RthJA2 is generated in accordance with JEDEC JESD51-5,-7 standards at natural convection on FR4 2s2p board. The simulation has been performed on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers ( 2 x 70 μm Cu, 2 x 35 μm Cu). A total of six thermal via (∅ = 0.3 mm, plating 25 μm) is placed under the exposed pad contacting the first inner copper layer. Total power dissipation 1.5W distributed statically and homogenously over all power stages

10 Not subject to production test, specified by design
11 Not subject to production test, specified by design
12 Not subject to production test, specified by design
13 Not subject to production test, specified by design
14 Not subject to production test, specified by design
15 Not subject to production test, specified by design
16

Not subject to production test, specified by design

17 Not subject to production test, specified by design
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