TLD1173-1ET | LED Driver ICs

Datasheet

LITIX™ Basic+

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Features

Single channel device with integrated and protected output stage (current sink), optimized to drive LEDs
High output current up to 400 mA
Possibility to offload power consumption via low cost external resistor to allow maximum current driving capability (Power Shift)
Fault management supports both 1-fail-all-OFF and 1-fail-all-ON
Analog output current control input to adjust the output current
Open load (OL), short to battery (SC) and thermal shutdown protections
Intelligent fault management: up to 10 devices can share a common error network with only one external resistor
Thermal derating function via external NTC resistor

Potential applications

Cost effective "stop"/"tail" function with shared and separated LEDs per function
Automotive light functions like turn indicators, position, fog, stop/tail, DRL and side markers
Animated light functions like sequential indicator and "welcome/goodbye" functions
Interior lighting functions like ambient lighting, illumination and dash board lighting
LED indicators for industrial applications and instrumentation

Product validation

Product validation according to AEC-Q100, Grade 1.

Qualified for automotive applications.

Description

The TLD1173-1ET is a single channel low-side driver IC with integrated and protected output stage. It is designed to control LEDs with a current up to 400 mA as linear current sink (LCS). The power shift feature allows the device to reach maximum current driving capability by offloading power consumption to an external low cost resistor. Along with its integrated diagnostic features, it offers a simple and reliable solution compared to discrete solutions. The diagnostic features and thermal derating via external NTC resistor provide a reliable solution for high current applications. The configurable fault management allows up to 10 and more devices to share the same error network and to be combined in applications with other LITIX™ LED drivers, such other LITIX™ Basic+ products and LITIX™ TLD7002-16ES.


Product type	Package	Marking
TLD1173-1ET	TFDSO-16	117

Product description

Table 1. Product summary
Parameter	Symbol	Values
Operating voltage	V_S(func)	5.5 V - 18 V
Extended operating voltage	V_S(ext)	4.5 V - 36 V
Maximum load current	I_SENSE(max)	400 mA
Output current accuracy	V_SENSE(reg)	±4% with V_SENSE = 400 mV
Current consumption in sleep mode	I_{VS(sleep, max)}	3 μA
Maximum current consumption during fault	I_{VS(fault, ERRN)}	850 μA
Maximum dropout voltage	V_DR,CS₍_max)	0.6 V

Block diagram

Figure 1. TLD1173-1ET Block diagram

Pin configuration

Pin assignment

Figure 2. PG-TFDSO-16

Pin definitions and functions

Table 2. Pin definitions and functions
Pin	Symbol	Function
16	VS	Power supply voltage Battery supply input
4	GND	Ground Ground potential. Connect externally close to the chip
8	EN/DEN	Output enable and diagnosis control input Connect to V_S via a resistor divider to enable OUT control and diagnosis capability
9	ERRN/DEN	ERROR flag I/O and diagnosis control input Open drain, active low. Connect to V_S via pull-up resistor for ERROR flag capability only otherwise connect to V_S via a resistor divider to enable diagnosis capability
6	SENSE	Sense input Connect to low ohmic accurate sense resistor
14	OUT	Channel output pin Open drain linear current sink. Connect to the target load
15	PS	Power shift Connect to external power resistor
2	D	Disable/delay error input Connect to a capacitor, leave open or connect to GND depending on the required diagnostic management
5	ACC/PWMI	Analog current control and PWMI input pin Connect to external low power resistor or apply a desired reference voltage to adjust the output current. Connect to external NTC to apply thermal derating. It is possible also to connect to an external open drain PWM controller
3	IREF	Current reference generation Connect to an external accurate low power resistor to generate a current reference
1,7,10, 11,12,13	NC	Not connected Leave these pins open
Exposed pad	EP	Exposed pad Used only for thermal dissipation purpose. Connect externally to GND close to the chip

General product characteristics

Absolute maximum ratings

Table 3. Absolute maximum ratings
T_J = T_J(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter	Symbol	Values			Unit	Note or condition	P-Number
Parameter	Symbol	Min.	Typ.	Max.	Unit	Note or condition	P-Number
Voltages
Supply voltage	V_S	-0.3	–	40	V	–	PRQ-32
EN/DEN voltage	V_EN/DEN	-0.3	–	40	V	–	PRQ-55
Output voltage	V_OUT	-0.3	–	40	V	–	PRQ-56
Power shift voltage	V_PS	-0.3	–	40	V	–	PRQ-59
Sense voltage	V_SENSE	-0.3	–	0.9	V	–	PRQ-63
ERRN/DEN voltage	V_ERRN/DEN	-0.3	–	40	V	–	PRQ-61
D voltage	V_D	-0.3	–	5.5	V	–	PRQ-175
ACC/PWMI voltage	V_ACC/PWMI	-0.3	–	5.5	V	–	PRQ-64
IREF voltage	V_IREF	-0.3	–	5.5	V	–	PRQ-176
Temperatures
Junction temperature	T_{J_ABS}	-40	–	150	°C	–	PRQ-39
Storage temperature	T_STG	-55	–	150	–	–	PRQ-40
ESD robustness
ESD robustness all pins (HBM)	V_ESD(HBM)	-2	–	2	kV	ESD robustness, Human Body Model “HBM” according to AEC Q100-002	PRQ-53
ESD robustness all pins (CDM)	V_ESD(CDM)	-500	–	500	V	ESD robustness, Charged Device Model “CDM” according to AEC Q100-011 Rev.D	PRQ-41
ESD robustness corner pins (CDM)	V_{ESD(CDM) CR}	-750	–	750	V	ESD robustness, Charged Device Model “CDM” according to AEC Q100-011 Rev.D	PRQ-54

Note:

Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.

Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as outside the normal operating range. Protection functions are not designed for continuous repetitive operation.

Functional range

Table 4. Functional rangeT_J = T_J(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter	Symbol	Values			Unit	Note or condition	P-Number
Parameter	Symbol	Min.	Typ.	Max.	Unit	Note or condition	P-Number
Voltages
Supply voltage for operating range	V_S(func)	5.5	–	18	V	–	PRQ-33
Extended supply voltage for operating range	V_S(ext)	4.5	–	36	V	–	PRQ-71
Currents
Channel output current	I_SENSE(func)	5	–	400	mA	–	PRQ-224
Power dissipation
Max. static and dynamic power dissipation	P_max			1.5	W	T_A = 85°C and R_thJA = 42 K/W	PRQ-419
Temperatures
Junction temperature	T_J(func)	-40	–	150	°C	–	PRQ-72

Note:

Within the functional or operating range, the IC operates as described in the circuit description. Within the Extended Operation range, parameters deviations are possible. The electrical characteristics are specified within the conditions given in the electrical characteristics table.

Thermal resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org

Table 5. Thermal resistanceV_S = V_S(func)*, T*_J = T_J(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter	Symbol	Values			Unit	Note or condition	P-Number
Parameter	Symbol	Min.	Typ.	Max.	Unit	Note or condition	P-Number
Junction to top	Ψ_JTOP	–	8	–	K/W		PRQ-34
Junction to case	R_thJC	–	8	–	K/W		PRQ-49
Junction to ambient 1s0p board	R_thJA1	–	64	–	K/W	T_A = 85°C	PRQ-48
Junction to ambient 2s2p board	R_thJA2	–	42	–	K/W	T_A = 85°C	PRQ-180

Internal supply

This chapter describes the internal supply, its main parameters and functionality.

Description

As soon as the voltage applied at the supply pin VS is above V_SUV(th) and the voltage applied at the EN/DEN pin is above V_EN(th), the device is ready to deliver output current from the output stage after the power on reset time t_POR. When the supply voltage V_S is below the threshold V_SUV(th), the internal Power-ON-Reset (POR) function holds the device in reset state.

The power on reset time t_POR has to be taken into account under relevant application conditions, i.e. with PWM control from VS.

Figure 3. Power on reset timing diagram

If the voltage applied at the EN/DEN pin is below V_EN(th) for more than t_SLEEP the device enters sleep mode. In this state all internal functions are switched off and the current consumption is reduced to I_VS(sleep).

Electrical characteristics

Table 6. Electrical characteristics
V_S = V_S(func)*, T*_J = T_J(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter	Symbol	Values			Unit	Note or condition	P-Number
Parameter	Symbol	Min.	Typ.	Max.	Unit	Note or condition	P-Number
Current consumption, sleep mode	I_VS(sleep)	–	–	3	µA	V_EN/DEN = 0 V T_J = 150°C	PRQ-85
Current consumption, active mode (no fault)	I_VS(active)	–	2.5	3.5	mA	V_EN/DEN = 5.5 V V_ACC/PWMI = 2.4 V IREF pin left open	PRQ-154
Current consumption during fault condition (1-fail-all-OFF)	I_{VS(fault, ERRN)}	–	–	850	µA	V_EN/DEN = 5.5 V V_ERRN = 0 V D pin open	PRQ-87
VS undervoltage threshold	V_SUV(th)	3.5	–	4.5	V	–	PRQ-89
EN/DEN outputs enable threshold	V_EN(th)	0.6	–	1.8	V	–	PRQ-159
EN/DEN outputs enable hysteresis	V_EN(hys)	80	120	–	mV		PRQ-160
EN/DEN pull-down current	I_EN/DEN(PD)	–	–	5	µA	V_EN/DEN = 3 V	PRQ-161
EN/DEN pull-down current	I_EN/DEN(PD)	–	–	150	µA	V_EN/DEN = 18 V	PRQ-371
Power on reset delay time	t_POR	–	–	75	µs	V_S rising edge from 0 V to 8 V to 10% of output current V_EN/DEN = 5.5 V V_ACC/PWMI ≥ 2.4 V	PRQ-164
Sleep mode filter time	t_SLEEP	15	–	45	ms	–	PRQ-109

Power stage

The power stage sinks from the OUT pin an output current I_OUT which is a function of the external sense resistor placed at SENSE pin.

The maximum output current is limited by the power dissipation P_max and used cooling areas.

Figure 4. Power stage block diagram

Output current regulation

The output current regulation block controls the LEDs current by regulating the voltage drop V_SENSE(reg) on the external low-side current-sense resistor R_SENSE placed between SENSE pin and GND.

When the LEDs current is in regulation, the LEDs current value can be calculated by using the following equation:

I_{S E N S E} = \frac{V_{S E N S E (r e g)}}{R_{S E N S E}}

For an operating output current control loop, the power stage dropout voltage (V_DR,CS), the V_SENSE(reg) voltage, the forward voltage V_{D_RP}of the reverse polarity protection diode (when used) and the minimum supply voltage have to be considered in the LED string design.

To grant a proper control of the output current the following equation has to be satisfied:

V_{S} \geq V_{S E N S E (r e g)} + V_{D R, C S} + V_{L E D_S T R I N G} + V_{D_R P}

In case the supply voltage drops below the minimum requested, the LEDs current is no longer properly regulated. Consequently, a lower current is delivered and the voltage across the R_SENSE resistor is lower than the expected V_SENSE(reg).

Note:

The R_SENSEhas to be placed as close as possible to the pin VSENSE to avoid current regulation instability.

Thermal protection

A thermal protection function is integrated into the device to prevent IC damage under fault conditions described in the datasheet. Fault conditions are considered as "outside" the normal operating range. Protective functions are not designed for continuous operations.

The thermal protection function is achieved by temperature monitoring of the power stage. As soon as the junction temperature exceeds the overtemperature threshold T_JSD:

The output current is disabled by turning off the power stage
The ERRN/DEN pin is pulled low
The current consumption is below I_{VS(fault, ERRN)}

Once the junction temperature falls below T_JSD - T_J(hys):

The power stage recovers to normal operation
The ERRN/DEN pin is released

Electrical characteristics

Table 7. Electrical characteristics
V_S = V_S(func)*, T*_J = T_J(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter	Symbol	Values			Unit	Note or condition	P-Number
Parameter	Symbol	Min.	Typ.	Max.	Unit	Note or condition	P-Number
Leakage currents
Output leakage current	I_OUT(leak)	–	–	1	µA	T_J = 85°C V_OUT ≤ 16 V V_ACC/PWMI = 0 V V_EN/DEN = 5.5 V	PRQ-116
Output leakage current	I_OUT(leak)	–	–	5	µA	T_J = 150°C V_OUT ≤ 16 V V_ACC/PWMI = 0 V V_EN/DEN = 5.5 V	PRQ-118
Sense regulation voltage accuracy
SENSE voltage regulation accuracy	V_SENSE(reg)	384	400	416	mV	V_ACC/PWMI ≥ 2.4 V	PRQ-120
SENSE voltage regulation accuracy	V_SENSE(reg)	95	100	105	mV	V_ACC/PWMI = 0.9 V	PRQ-121
SENSE voltage regulation accuracy	V_SENSE(reg)	14	20	26	mV	V_ACC/PWMI = 0.5 V	PRQ-123
Power stage drop out
Power stage drop out voltage	V_DR,CS	–	–	0.6	V	I_OUT = 400 mA	PRQ-124
Thermal protection thresholds
Overtemperature shutdown threshold	T_JSD	165	175	185	°C		PRQ-131
Overtemperature hysteresis	T_J(hys)	5	10	15	°C	⁸	PRQ-132

Power shift

The device manages high power dissipation (higher than allowed by the thermal impedance R_thJA of the application) by separating the LED current into two current branches:

One current sink path through an external drop element (power resistor) and the internal power shift
One current sink path through the internal power stage

The current flowing into the power shift path and the one flowing into the power stage path are dynamically adjusted in order to obtain that the sum of I_OUT and I_PS currents is equal to the regulated I_SENSE current.

The distribution of the current between the power shift path and the power stage path is defined by the power shift resistor value, the load and the applied battery voltage V_S.

In order to proper dimension the resistor value the following parameters have to be considered:

Maximum current I_PSintended to flow into the power shift path at maximum battery operative voltage V_S(PEAK)
Forward voltage V_{LED_STRING}of the output LED load and forward voltage V_{D_RP}of the reverse polarity protection diode
Voltage drop on the internal power shift element (V_{PS_INT} = I_PS x R_{PS_INT(ON)})
Regulated V_SENSE voltage

The resistor can then be calculated using the following formula:

R_{P S} = \frac{V_{S (P E A K)} - V_{D_R P} - V_{L E D_S T R I N G} - V_{P S_I N T} - V_{S E N S E}}{I_{P S}}

Figure 5. Power shift resistor diagram

Note:

Please consider that if the R_PSis set to 0 Ω all the LED current flows inside the internal power shift path leading to a possible overheating of the device up to the thermal shut-down.

Electrical characteristics

Table 8. Electrical characteristicsV_S = V_S(func)*, T*_J = T_J(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter	Symbol	Values			Unit	Note or condition	P-Number
Parameter	Symbol	Min.	Typ.	Max.	Unit	Note or condition	P-Number
Power shift ON resistance	R_{PS_INT(ON)}	–	–	3	Ω	I_PS = 400 mA	PRQ-275
Power shift leakage current	I_PS(leak)	–	–	1	µA	⁹ T_J = 85°C V_PS ≤ 16 V V_ACC/PWMI = 0 V V_EN/DEN = 5.5 V	PRQ-277
Power shift leakage current	I_PS(leak)	–	–	3	µA	T_J = 150°C V_PS ≤ 16 V V_ACC/PWMI = 0 V V_EN/DEN = 5.5 V	PRQ-287
Power shift ratio	I_PS/I_SENSE	0.95	–	–	–	V_PS - V_SENSE > 1.5 V V_ACC/PWMI ≥ 0.9 V	PRQ-279
SENSE voltage regulation accuracy	V_SENSE(reg)	384	400	416	mV	V_ACC/PWMI ≥ 2.4 V	PRQ-408
SENSE voltage regulation accuracy	V_SENSE(reg)	95	100	105	mV	V_ACC/PWMI = 0.9 V I_SENSE > 20 mA	PRQ-410
SENSE voltage regulation accuracy	V_SENSE(reg)	14	20	28	mV	V_ACC/PWMI = 0.5 V I_SENSE > 20 mA	PRQ-414

PWM control

PWM dimming is adopted to vary LEDs brightness with greatly reduced chromaticity shift. PWM dimming achieves brightness reduction by varying the duty cycle of a constant current in the LED string.

The PWM modulation is performed via the ACC/PWMI pin. The power stage and the power shift are disabled if the voltage applied on the ACC/PWMI pin is lower than V_PWM(OFF)while they are enabled if the voltage applied on the PWMI/ACC pin is higher than V_PWM(ON).

In Figure 6 two examples of PWM dimming are shown via the ACC/PWMI input pin:

In case a resistor is needed on the ACC/PWMI input pin to apply analog current control (i.e. binning or thermal derating) the PWM signal can be applied using an open drain output from the PWM generator
In case the analog current control function is not needed a push-pull output from the PWM generator can be used to apply the PWM modulation

Figure 6. PWM control via ACC/PWMI input pin

The PWM signal can be applied via the EN/DEN pin as well to allow PWM modulation from the battery line. Indeed by applying a proper filtering on the VS pin to avoid to trigger the VS undervoltage threshold, the t_POR delay time would be applied only on the first PWM pulse generation after the exit from sleep state, like shown in Figure 9.

When applied on the EN/DEN pin the PWM signal has a frequency range f_PWMto avoid to turn-off the channel by triggering the t_SLEEP filter time.

The power stage and the power shift of the channel are enabled if the voltage applied on the EN/DEN pin is higher than V_EN(th)while they are disabled if the voltage applied on the EN/DENx pin is lower than V_EN(th).

Figure 7. PWM control via EN/DEN input pin

When the voltage applied on the ACC/PWMI pin is below V_PWM(OFF), the load diagnostic is disabled unless a fault was previously detected.

As well, when the voltage applied on the EN/DEN pin is below V_DEN(th), the load diagnostic is disabled unless a fault was previously detected.

In particular, if a fault is already present when the voltage applied on the ACC/PWMI pin is below V_PWM(OFF)or the voltage applied on EN/DEN pin is below V_DEN(th) the diagnostic is kept active until the fault condition disappears, after that it is then disabled.

The PWM control block implements a slope control of the V_SENSE voltage in order to improve EMC performances. The slew rate timings are defined by dV/dt_ONand dV/dt_OFFparameters.

Figure 8. PWMI control timing diagram for V_ACC/PWMI ≥ 2.4 V

Figure 9. PWM control on EN/DEN timing diagrams for V_ACC/PWMI ≥ 2.4 V

Electrical characteristics

Table 9. Electrical characteristicsV_S = V_S(func)*, T*_J = T_J(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter	Symbol	Values			Unit	Note or condition	P-Number
Parameter	Symbol	Min.	Typ.	Max.	Unit	Note or condition	P-Number
PWM turn off threshold	V_PWM(OFF)	0.35	0.4	–	V	–	PRQ-145
PWM turn on threshold	V_PWM(ON)	–	–	0.45	V	–	PRQ-261
PWM frequency range	f_PWM	100	–	–	Hz		PRQ-146
PWM turn on time	t_ON	–	–	20	µs	¹⁰ V_SENSE rising to 80% of regulation V_ACC/PWMI ≥ 2.4 V	PRQ-147
PWM turn off time	t_OFF	–	–	20	µs	¹⁰ V_SENSE falling to 20% of regulation V_ACC/PWMI falling from ≥ 2.4 V to less than V_PWM(OFF)	PRQ-148
VSENSE rising slew rate	dV/dt_ON	15	35	50	mV/µs	¹⁰ V_SENSE rising from 20% to 80% of regulation V_ACC/PWMI ≥ 2.4 V	PRQ-149
VSENSE falling slew rate	dV/dt_OFF	-50	-35	-15	mV/µs	¹⁰ V_SENSE falling from 80% to 20% of regulation V_ACC/PWMI falling from ≥ 2.4 V to less than V_PWM(OFF)	PRQ-150

Analog output current control

The analog output current control function adjusts the V_SENSE voltage by sensing the applied voltage on the ACC/PWMI pin V_ACC/PWMI.

As described in Power stage the output current provided by the channel is a direct function of the regulated voltage V_SENSE. In this way by adjusting the voltage applied on the ACC/PWMI pin it is possible to control the output current.

I_{S E N S E} = \frac{0.2 \times V_{A C C / P W M I} - 0.08 V}{R_{S E N S E}}

The relation between the ACC/PWMI voltage V_ACC/PWMI and the respective regulated voltage V_SENSE is shown in the Figure 10.

Figure 10. Analog output current control

The voltage on ACC/PWMI can be set by applying an accurate external resistor on the ACC/PWMI pin. In case the resistor is placed in another PCB (i.e. binning resistor) it is recommended to add capacitor of 220 nF close to the ACC/PWMI pin.

The ACC/PWMI pin outputs a constant current based on the IREF output current and the ACC current ratio I_ACC/I_IREF.

Note:

In case the analog output current control function is not needed it is recommended to put 100 kΩ pull-down resistor on the IREF pin to proper bias the ACC/PWMI voltage to avoid wrong V_SENSE setting.

Figure 11. Analog output current control configurations

Electrical characteristics

Table 10. Electrical characteristicsV_S = V_S(func)*, T*_J = T_J(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter	Symbol	Values			Unit	Note or condition	P-Number
Parameter	Symbol	Min.	Typ.	Max.	Unit	Note or condition	P-Number
ACC current ratio	I_ACC/I_IREF	4.85	5	5.15	–	20 μA ≤ I_IREF≤ 250 μA	PRQ-253

Current reference generation

The current reference generation block, outputs an accurate output reference current with low temperature shift.

The voltage on the IREF pin is regulated in the V_IREF range.

It turns out that the reference current can be set by placing an external resistor from IREF pin to GND and can be calculated using the following formula:

I_{I R E F} = \frac{V_{I R E F}}{R_{I R E F}}

Note:

The R_IREFhas to be placed as close as possible to the pin IREF to avoid current regulation instability.

Electrical characteristics

Table 11. Electrical characteristicsV_S = V_S(func)*, T*_J = T_J(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter	Symbol	Values			Unit	Note or condition	P-Number
Parameter	Symbol	Min.	Typ.	Max.	Unit	Note or condition	P-Number
IREF regulated voltage	V_IREF	1.164	1.2	1.236	V	–	PRQ-268
IREF current range	I_IREF	–	–	250	μA	–	PRQ-269
IREF capacitance	C_IREF	–	–	0.22	nF		PRQ-273

Load diagnostics

Several diagnosis features are integrated:

Open load detection (OL)
Short to supply detection (SC)
Power shift short to supply detection (SC)
Overtemperature thermal detection (OT)

The behavior of the device during overload conditions that lead to an excess of internal heating, up to overtemperature condition, is already described in chapter Thermal protection.

An open load condition is detected if the voltage across the power stage V_DR = V_OUT- V_SENSE is below the threshold V_DR(OL) for at least a filter time t_fault.

A short to supply condition is detected if the output voltage drop over the load V_S - V_OUT is below the threshold V_OUT(SC) for at least a filter time t_fault.

A power shift short to supply condition is detected if the power shift voltage drop V_S - V_PS is below the threshold V_PS(SC) for at least a filter time t_fault.

If an OL condition is detected on the OUT pin or a SC condition is detected on one of the OUT or PS pins, a pull-down current I_OUT(fault) flows inside the OUT pin replacing the configured output current.

Note:

The I_OUT(fault) current is limited by the actual load impedance, e.g. it is reduced to zero with an ideal open load.

Diagnostics enable

As soon as the voltage applied at the supply pin VS is above V_SUV(th) and the voltage applied to the EN/DEN pin is above V_DEN(th), the device is ready to detect and report fault conditions via ERRN/DEN pin.

There are several possibilities to program the output enable and diagnosis enable via EN/DEN pin, like a resistor divider from VS to GND, a Zener diode from EN/DEN to VS and also a logic control pin (e.g. from a microcontroller output).

Figure 12. EN/DEN block diagram

ERRN/DEN pin

The device is able to report a detected failure in its driven load and react to a fault detected by another LED driver in the system if a shared error network is implemented (i.e. driving LED chains of the same light function). This is possible with the usage of an external pull-up resistor, allowing multiple devices to share the open-drain diagnostic output pin ERRN/DEN. All devices sharing a common error network are capable to detect the fault from any of the channels driven by the Basic+ family.

The open-drain ERRN/DEN pin applies a pull-down resistance R_ERRN(ON) towards GND when a fault condition is detected for at least a filter time t_fault. Therefore, an active low state can be detected at ERRN/DEN pin when V_ERRN < V_ERRN(fault) and the relative faulty output channel is switched off.

Similarly, when the fault is removed, ERRN/DEN pin is back in high impedance state and the channel reactivation is completed as illustrated in Figure 13.

Figure 13. ERRN/DEN pin block diagram

To enable the possibility to decouple the V_DEN(th) threshold from the V_EN(th) threshold to have the device turning on as soon as needed independently from the diagnostic enable threshold, V_DEN(th), the DEN functionality is duplicated on the ERRN/DEN pin.

The diagnostic reporting on ERRN/DEN pin and "open load", "short to supply" and the "power shift short to supply" protections are disabled, unless a fault was previously detected, as soon as one of the following condition is verified:

The voltage on the ERRN/DEN pin is V_ERRN(fault)< V_ERRN/DEN≤ V_ERRN(DEN)
The voltage on EN/DEN pin is below V_DEN(th)

When the ERRN/DEN pin applies a pull-down resistor R_ERRN(ON) towards GND the V_ERRN(DEN)threshold is masked to avoid unwanted toggling of the voltages on the ERRN/DEN pin.

D pin

The D pin is designed for two main purposes:

To react to error conditions in LED arrays according to the implementation fault management policy, in systems where multiple LED chains are used for a given function as illustrated in Figure 14
To extend the channel's deactivation delay time of a value t_D, adding a small signal capacitor from the D-pin to GND. In this way, an unstable or noisy fault condition may be prevented from switching off all the channels of a given light function (i.e. driven by several ICs sharing the same error network)

The functionality of the D-pin is shown in the simplified block diagram illustrated in Figure 15.

Figure 14. D pin configurations

Figure 15. D pin block diagram

In normal operative status (no fault) a pull-down current I_D(PD) is sunk from the D-pin to GND.

If there is a fault condition (for at least a filter time t_fault) in one of the LED channels driven by the IC or in any of the devices sharing the same ERRN error network line, a pull-up current I_D(fault) is instead sourced from the D-pin.

If a capacitive or open load is applied at this pin (1-fail-all-OFF), its voltage starts rising. When V_D(th) is reached at D-pin, all the channels driven by the device are switched off and if other devices share the same ERRN/DEN and D-pins nodes, all the devices turn their outputs off.

Alternatively, if the D-pin is tied to GND (1-fail-all-ON), only the channel that has been detected with a fault is safely deactivated.

The capacitor value used at the D-pin, C_D, sets the delay times t_D(set/reset) according to the following equations:

t_{D (s e t)} = \frac{C_{D} \times V_{D (t h)}}{I_{D (f a u l t)}}

t_{D (r e s e t)} = \frac{C_{D} \times (V_{D (C L)} - (V_{D (t h)} - V_{D (h y s)}))}{I_{D (P D)}}

Fault management

With D pin open or connected with a capacitor to GND configuration, it is possible to switch off all the channels which share a common error network, without the need of an auxiliary microcontroller. For more details refer also to the timing diagram.

If there is a fault condition at the output or the power shift, the ERRN/DEN pin applies a pull-down resistance R_ERRN(ON) towards GND and (with proper dimensioning of the external pull-up resistor) reaches a voltage level below V_ERRN(fault). After t_D(set), the voltage V_D(th) is reached at D pin. The ERRN/DEN low voltage can also be used as input signal for a microcontroller to perform the desired diagnosis policy.

The OL and SC error conditions are not latched: as soon as the fault condition is no longer present, for at least a filter time t_fault, ERRN/DEN goes back to high impedance. When its voltage is above V_ERRN(fault), the D pin voltage starts decreasing and after t_D(reset) goes below (V_D(th) - V_D(th,hys)).

Figure 16. Open load condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor)

Figure 17. Output short to supply condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor)

Figure 18. Power shift short to supply condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor)

With D pin connected to GND, it is possible to deactivate only the channel under fault condition, still sharing ERRN pin in a common error network with other devices of Basic+ family.

If there is a fault condition at the output or the power shift, the ERRN pin applies a pull-down resistance R_ERRN(ON) to ground and the voltage level on this pin will drop below V_ERRN(fault) if the external pull-up resistor is properly dimensioned. The ERRN low voltage can also be used as input signal for a µC to perform the desired diagnosis policy.

The OL and SC error conditions are not latched: as soon as the fault condition is no longer present (for at least for a filter time t_fault) ERRN/DEN goes back to high impedance andthe output stage is activated again.

Figure 19. Open load condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND)

Figure 20. Output short to supply condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND)

Figure 21. Power shift short to supply condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND)

Electrical characteristics

Table 12. Electrical characteristics
V_S = V_S(func)*, T*_J = T_J(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter	Symbol	Values			Unit	Note or condition	P-Number
Parameter	Symbol	Min.	Typ.	Max.	Unit	Note or condition	P-Number
ERRN/DEN pin
ERRN fault threshold	V_ERRN(fault)	0.7	–	0.9	V	–	PRQ-193
ERRN ON resistance	R_ERRN(ON)	–	–	350	Ω	I_ERRN/DEN = 2 mA Fault condition V_EN/DEN > V_DEN(th)	PRQ-379
ERRN diagnosis enable threshold	V_ERRN(DEN)	2.1	–	2.3	V	–	PRQ-255
ERRN pull-down current	I_{ERRN_PD}	–	–	2	µA	No fault condition V_EN/DEN > V_DEN(th)	PRQ-380
Diagnosis enable
DEN diagnosis enable threshold	V_DEN(th)	2.3	–	2.7	V	–	PRQ-244
Protections
OL detection threshold	V_DR(OL)	0.2	–	0.4	V	V_EN/DEN > V_DEN(th) V_ERRN/DEN > V_ERRN(DEN)	PRQ-285
OUT SC detection threshold	V_OUT(SC)	0.8	–	1.35	V	V_EN/DEN > V_DEN(th) V_ERRN/DEN > V_ERRN(DEN)	PRQ-286
PS SC detection threshold	V_PS(SC)	0.8	–	1.35	V	V_EN/DEN > V_DEN(th) V_ERRN/DEN > V_ERRN(DEN)	PRQ-292
Fault detection current	I_OUT(fault)	–	–	650	µA	OL or SC fault condition V_EN/DEN > V_DEN(th) V_ERRN/DEN < V_ERRN(fault)	PRQ-294
D pin
Threshold voltage for function de-activation	V_D(th)	1.4	1.7	2	V	V_EN/DEN > V_DEN(th) V_ERRN/DEN > V_ERRN(DEN)	PRQ-299
Threshold hysteresis	V_D(hys)	70	–	–	mV	V_EN/DEN > V_DEN(th) V_ERRN/DEN > V_ERRN(DEN) Not subject to production test, specified by design	PRQ-300
Fault pull-up current	I_D(fault)	20	35	50	µA	OL or SC fault condition V_EN/DEN > V_DEN(th) V_ERRN/DEN < V_ERRN(fault) V_D = 2 V	PRQ-301
Pull-down current	I_D(PD)	40	60	95	µA	No fault conditions V_EN/DEN > V_DEN(th) V_ERRN/DEN > V_ERRN(DEN) V_D = 1.4 V	PRQ-302
Internal clamp voltage	V_D(CL)	2	–	3	V	OL or SC fault condition V_EN/DEN > V_DEN(th) V_ERRN/DEN < V_ERRN(fault) D-pin open	PRQ-303
Timings
Fault to ERRN delay	t_fault	40	–	120	µs	V_EN/DEN > V_DEN(th) V_ERRN/DEN > V_ERRN(DEN)	PRQ-304

Application information

Note:

The following information is given as an example for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.

Application diagram

Note:

This figure is a simplified example of an application circuit. The function must be verified in the application.

Figure 22. Application diagram example in a shared network with "one fail all off" fault management and central thermal derating

Package information

Figure 23. PG-TFDSO-16 package outline png

Revision history


Document version	Date of release	Description of changes
Rev. 1.00	2024-10-14	Initial document release

¹ Not subject to production test, specified by design

Specified Ψ_JTOPis derived under natural convention conditions and provide a correlation between the junction temperature and the temperature on the package top surface. T_A = 85°C. Total power dissipation = 1.5 W

Specified R_thJCis simulated at natural convention on a cold plate setup (all pins and exposed pad are fixed at ambient temperature). T_A = 85°C. Total power dissipation = 1.5 W

⁴

Specified R_thJA1is generated in accordance with JEDEC JESD51-3 standards at natural convection on FR4 1s0p board. The simulation has been performed on a 76.2 x 114.3 x 1.5 mm board with 70 μm, 300 mm² cooling area. Total power dissipation 1.5W distributed statically and homogenously over all power stages

⁵

Specified R_thJA2is generated in accordance with JEDEC JESD51-5,-7 standards at natural convection on FR4 2s2p board. The simulation has been performed on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers ( 2 x 70 μm Cu, 2 x 35 μm Cu). A total of six thermal via (∅ = 0.3 mm, plating 25 μm) is placed under the exposed pad contacting the first inner copper layer. Total power dissipation 1.5W distributed statically and homogenously over all power stages

⁶ Not subject to production test, specified by design

⁷ Not subject to production test, specified by design

⁸ Not subject to production test, specified by design

⁹

Not subject to production test, specified by design

¹⁰

Not subject to production test, specified by design

¹¹ Not subject to production test, specified by design