PSoC™ 6 technical reference manuals
A technical reference manual (TRM) provides detailed technical information on a device family. Architecture TRMs provide a functional description of the various sub-blocks in the device including block features, architecture, and use cases. Register TRMs provide a register level description of the user accessible registers in the device.
The TRMs for the PSoC™ 6 device families are listed below.
| Device Family | Architecture TRM | Registers TRM |
|---|---|---|
| PSoC™ 61 Programmable Line (Single Core Applications CPU: ARM® Cortex®-M4) | ||
| CY8C61x4 | ||
| CY8C61x5 | ||
| CY8C61x6, CY8C61x7 | ||
| CY8C61x8, CY8C61xA | ||
| PSoC™ 62 Performance Line (Dual Core Applications CPU: ARM® Cortex®-M4, ARM® Cortex®-M0+) | ||
| CY8C62x4 | ||
| CY8C62x5 | ||
| CY8C62x6, CY8C62x7 | ||
| CY8C62x8, CY8C62xA | ||
| PSoC™ 63 Bluetooth® Low Energy Connectivity Line (MCUs with on-chip Bluetooth® radio) | ||
| CY8C63x6, CY8C63x7 | ||
| PSoC™ 64 Secure MCU Line (Applications CPU: ARM® Cortex®-M4, Secure CPU: ARM® Cortex®-M0+) | ||
| CYB064x5 Secure Boot | ||
| CYB064x7 Secure Boot | ||
| CYB064xA Secure Boot | ||
| CYB064x7-BL Secure Boot BLE | ||
| CYS064xA Standard Secure | ||