AN230938  PSoC™ 6 MCU low-power analog

Table 1 provides a comparison of CY8C62x4 with other PSoC™ devices.

For more details on low-power operation of analog blocks, see Low-power mode operation of analog resources section.

Along with the rich set of analog blocks, CY8C62x4 provides flexible routing to implement circuit configurations that can be dynamically controlled. Figure 2 illustrates the analog routing diagram.

SARMUX: SARMUX is used by the SAR ADC to connect to different sources such as GPIOs, opamp outputs, and temperature sensor. There are two SARMUX blocks in the device, one for each ADC.

SARBUS: SARBUS is used sby the SAR ADC to connect to Opamps via SARMUX. There are two SARBUS blocks: SARBUS0 and SARBUS1.

Analog Multiplexer Bus (AMUXBUS): AMUXBUS is used to interconnect GPIOs from certain ports and to route signals to/from the peripherals. There are two analog mux buses in the device: AMUXBUSA and AMUXBUSB. These buses can be split to create multiple segments which helps to route more than two signals. Note that AMUXBUS connections are not available in Deep Sleep and Hibernate modes. If Deep Sleep or Hibernate operation is required, the Low-power comparator must be connected to the dedicated pins. This restriction also includes routing of any internally-generated signal, which uses the AMUXBUS for the connection.

Dedicated port pins for the peripherals provide slight advantage over other pins in terms of routing resistance and capacitance. See AN218241 – PSoC™ 6 MCU Hardware Design Considerations for the recommended pins.

SAR ADCs are supported with resources to operate autonomously in System Deep Sleep mode. These resources include the analog reference generator, LPOSC or medium-frequency clock for running both the SAR ADCs, timer for trigger (common for both ADCs), and a FIFO for storing the data.

The ADCs operate in one of the following two modes:

• Always-ON in LP/ULP mode and powered-OFF in System Deep Sleep mode
• Always-ON in LP/ULP mode and duty-cycling in System Deep Sleep mode

Figure 3 illustrates the operation of an ADC in System Deep Sleep mode and the transition from or to LP/ULP mode.

In the LP/ULP mode, the ADC is in an always-on state along with the supporting resources. In the System Deep Sleep mode, the ADC remains powered-off until timer trigger is received. The timer is the only option for an ADC trigger in System Deep Sleep mode. Upon receiving a trigger, a programmable delay (called as power-up delay) is initiated to allow the ADC, the analog reference⁶⁾ and LPOSC clock⁶⁾ to settle before the conversion begins. After this delay, conversion of all enabled channels begins (which corresponds to one scan) and the results are stored in the FIFO. Power for the ADC is then turned OFF and it waits for the next timer trigger.

If both ADCs are used in System Deep Sleep mode, power is not turned OFF until results from both ADCs are moved to their respective FIFOs.

Interrupts are enabled to allow the ADC to wake up the device (see section Interrupts).

Figure 4 illustrates the timing diagram of SAR ADC duty-cycling in System Deep Sleep mode and the resulting average current consumption.

Similar to the ADCs, the opamps can also work in System Deep Sleep mode, in the following modes:

• Always-ON in LP/ULP mode and powered-OFF in System Deep Sleep mode
• Always-ON in LP/ULP mode and duty-cycling in System Deep Sleep mode
• Always-ON in LP/ULP mode and System Deep Sleep mode

Note that the ADC does not have a mode (c) available. Opamp mode (c) is useful to avoid wake up times which could be longer with larger external passive components in the opamp feedback path.

The duty-cycling of opamps is linked to the duty-cycling of the ADCs in System Deep Sleep mode, as Figure 5 shows. Duty-cycling of opamps is possible only when at least one of the ADCs is used in System Deep Sleep mode. The timer trigger wakes up both the opamps and the enabled ADCs. When the conversions are complete, the opamps and ADCs are powered-OFF at the same time. When opamp duty-cycling is not used⁸⁾ or if the ADCs are configured to operate only in LP/ULP mode, the opamps remain ON continuously throughout the System Deep Sleep time.

Analog reference is used by both the SAR ADCs and the opamps; charge pump is used by Opamps to boost its input range. Their state in System Deep Sleep mode depends on the settings of SAR ADCs and Opamps as Table 4 shows.

DAC, in System Deep Sleep mode, can hold its last configured value. It is not possible to change this value during System Deep Sleep mode. This voltage is buffered using CTBm opamp and driven to a pin. This is useful in applications, where voltage is continuously required for biasing.

There is another useful feature of duty-cycling the DAC which works in conjunction with S/H circuit of CTBm. In this method, firmware connects DAC output to Opamp input in order to sample the DAC output and then DAC is disconnected and powered down. Opamp input is held at a certain potential which is periodically refreshed using firmware. Figure 6 shows a simplified diagram of S/H between DAC and opamp. For the detailed configuration, refer the Technical Reference Manual.

The AREF block generates voltage and current references required for SAR ADCs, Opamps, DAC and CAPSENSE™. This block can operate in both System LP/ULP and System Deep Sleep modes. In the System Deep Sleep mode, AREF block can be configured in different modes as Table 6 shows.

AREF current, available to the CTBm opamps, can be configured to either 100 nA or 1 μA which affects the power consumption (see Table 5).

LPCOMP is the only analog block capable of operating even in Hibernate mode. There are two LPCOMPs in the device. It provides an option to generate interrupt so as to wake up the device. The block provides three programmable power levels: normal, low, and ultra-low. The response time of the block increases with the decrease in the power level as Table 7 shows.

Power mode selection also impacts other parameters of the block. Refer the device datasheet for the specifications.

Opamps and LPCOMPs provide configurable power options. Depending on the application requirement, block power can be optimized. Note that lower power levels come with a penalty on the performance. Refer the Opamp section and Low-power comparator (LPCOMP) section for details.

Many applications do not require continuous scanning of analog inputs and the CPU in its operation in the field. In such cases, duty-cycling of analog sources in System Deep Sleep mode yields significant power savings. Following sections describe three scenarios with the use of duty-cycling for SAR ADC and Opamp. Bench current measurement is done using the CY8CKIT-062S4 PSoC™ 62S4 Pioneer Kit.

One scan of SAR ADC involves sampling and conversion of all the enabled channels. When duty-cycling is used, power savings depend on the interval between the two scans triggered by the Timer. Longer the interval, that is lower the scan frequency, lower the power consumption. For applications where the signal to be measured vary slowly, the scan interval should be set longer.

Based on the test settings provided in Example: SAR ADC section (except for the timer clock input; here, WCO is used instead of ILO for better accuracy), Figure 9 shows current numbers with the bench testing with CY8CKIT-062S4 PSoC™ 62S4 Pioneer Kit for different scan frequencies and average sample count while operating in System Deep Sleep mode.

Acquisition time of SAR ADC channels should be set to minimum possible value to reduce the operating time of SAR ADC and power consumption. Acquisition time is selected from one of the four programmable 10-bit fields. If the SAR ADC clock is set to peripheral clock of 36 MHz (maximum frequency), the acquisition time can be set from 83 ns (three clocks) to 28 µs. With 2 MHz LPOSC or Medium Frequency Clock, the acquisition time can be set from 0.5 µs (1 clock) to 512 µs. Selection of the acquisition time depends on the source resistance, input resistance, and input capacitance of SAR ADC.

Figure 10 shows the equivalent diagram of the SAR ADC input. When the acquisition begins with the closing of SW_ACQ, the C_HOLD charges towards the input signal value. For 12-bit resolution, it takes 9RC time to charge within ½ LSB of the final value. Therefore, the minimum acquisition time is as shown below.

T_ACQ ≥ 9 × R × C_HOLD

where,

R = R_SRC + R_SW1 + R_SW2

R_SRC = Source resistance

R_SW1 = SAR sampling switch resistance

R_SW2 = Routing resistance

C = C_HOLD is the SAR input capacitance and it is typically 5pF

If the input is taken from SARMUX port pins, R_SW1 + R_SW2 is typically 1 kΩ. If routing involves SARBUS or AMUX bus, additional resistance should be included which results in increased acquisition time requirement. It is therefore recommended to use SARMUX port pins for SAR ADC inputs.

Each SAR ADC includes a reference buffer to drive its reference. The input options to the reference buffer are the 1.2 V from Analog Reference block and V_DDA/2. The other options (V_DDA and external reference from the GPIO) are connected directly to the reference terminal of SAR ADC and the reference buffer is disabled. Thus, power can be saved if V_DDA or external reference is used. Refer the device datasheet for the current consumption with internal and external reference specifications.

Reference buffer power can be adjusted based on the SAR ADC clock frequency. ModusToolbox™ software automatically configures the buffer power based on the selected clock frequency. If SAR ADC is configured manually, then buffer power should be configured to 100% when operating above 18 MHz, 60% when operating at 3.6 MHz to 18 MHz, and 30% when operating below 3.6 MHz. Refer the Technical Reference Manual for more details.

The reference buffer output can be routed to pin for filtering using a bypass capacitor¹¹⁾. Start up time of the SAR ADC block varies with the capacitor used for the internal reference voltage filtering as Table 10 shows.

SAR ADC is clocked from one of the two options for operating in System Deep Sleep mode. Medium Frequency Clock is derived from System Deep Sleep operable Internal Main Oscillator (IMO) which consumes slightly more current than the LPOSC with the identical accuracy. LPOSC can be duty-cycled as explained in LPOSC duty-cycling section below. Therefore, use the LPOSC for additional power savings.

LPOSC provides an option to duty-cycle along with SAR ADC power, thus, providing power savings while SAR is powered-down in System Deep Sleep mode. If SAR ADC is configured to use Medium Frequency Clock, turn OFF the LPOSC to save power. When duty-cycling is enabled for LPOSC, ensure the Timer (which is the only trigger source in System Deep Sleep mode) is clocked using ILO or WCO.

As described in SAR ADCs section, power-up delay allows the SAR ADC (mainly, the reference buffer), Analog Reference, LPOSC and Opamp (if used with duty-cycling) to settle before sampling and conversion process begins. Power-up delay is an 8-bit configuration value, clocked from either LPOSC or Medium Frequency Clock selected for the SAR ADC; i.e., Power-up delay can range from 0 to 127.5 µs.

The minimum value of power-up delay required is 20 µs. If your design includes external elements that require more settling time, increase the delay until there is no transient in the output. If the maximum delay is reached and output still has transient, modify your design to reduce the settling time required or throw away the initial few samples.

Each SAR ADC in the device is equipped with its own FIFO of 64 samples depth to collect the measurement results in System Deep Sleep mode. FIFO chaining is possible wherein, FIFO associated with the second SAR ADC (SAR ADC 1) is chained to the FIFO of the first SAR ADC (SAR ADC 0), thereby, doubling the depth of the resulting FIFO. Note that this combined FIFO will load results only from SAR ADC 0. It helps to load larger number of results, while being in System Deep Sleep mode; thus, saving the power. Use FIFO chaining whenever faster sampling is used or when CPU processing is performed on large samples at a slower rate.

When the device wakes up, there are two options to read the FIFO data: using CPU or DMA. Using DMA saves the power and is useful when larger samples are required to be accumulated which cannot fit even in the chained FIFO. In this case, DMA can be used to move the FIFO data into memory when the CPU is in Sleep mode. When the required number of samples are accumulated, CPU can then be woken up for processing.