# Microphone¶

group group_board_libs_microphone

The microphone uses the HAL PDM_PCM driver for its initialization.

There is no custom driver for this hardware.

Microphone Setup

To enable the microphone on the shield, these steps must be performed:

1. Initialize a PLL

2. Initialize the audio subsystem clock

3. Configure the PDM support system

note

For the microphone, there are two parameters passed to the shield initialization function:

• cyhal_clock_t* - audio_clock in the example code below

• cyhal_pdm_pcm_cfg_t* - configuration settings to use for the PDM

note

If either of these are NULL, the microphone will not be enabled.

1. Initialize the PLL

note

This example code is for a PSoC 6 device.

cyhal_clock_allocate(&pll_clock, CYHAL_CLOCK_BLOCK_PLL);
cyhal_clock_set_frequency(&pll_clock, &lt;AUDIO_SYS_CLOCK_HZ&gt;, NULL);
cyhal_clock_set_enabled(&pll_clock, true, true);


The value for <AUDIO_SYS_CLOCK_HZ> is discussed below. A typical value is 16384000.

2. Initialize the audio subsystem clock

note

This example code is for a PSoC 6 device.

cyhal_clock_get(&audio_clock, & &lt;AUDIO_CLOCK_RESOURCE&gt;);
cyhal_clock_init(&audio_clock);
cyhal_clock_set_source(&audio_clock, &pll_clock);
cyhal_clock_set_enabled(&audio_clock, true, true);


An appropriate setting for <AUDIO_CLOCK_RESOURCE> is CYHAL_CLOCK_HF[1].

3. Configure the PDM support system

This involves setting the values in the cyhal_pdm_pcm_cfg_t structure. It also involves setting the value of <AUDIO_SYS_CLOCK_HZ>, referred to in example code above.

left_gain, right_gain - Typically set to 0. May be set to other values to implement some sort of volume control.

decimation_rate - Typically set to 32. May be changed to oversample the PDM for non-voice applications. Or to downsample for low power conditions. For example, implementing some kind of pink-noise wake-up.

mode - Typically set to CYHAL_PDM_PCM_MODE_STEREO.

sample_rate and <AUDIO_SYS_CLOCK_HZ> - For many applications, setting the sample_rate to 8000 (Hz) and setting <AUDIO_SYS_CLOCK_HZ> to 16384000 will be appropriate.

The most common audio sample rates are 8, 16, 32, 44.1, and 48 Ksps.

The minimum frequency for the PLL on PSoC 6 is 12.5 MHz. The value of <AUDIO_SYS_CLOCK_HZ> is determined by the sample_rate multiplied by the decimation_rate multiplied by some value (X) that makes the result greater than 12.5 MHz. So, X needs to be at least 64. And that means that the minimum clock frequency from the PLL to achieve the standard sample rates is 16.384 MHz.